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CN102759646A - A kind of testing method and device of harmonic multimeter - Google Patents

A kind of testing method and device of harmonic multimeter Download PDF

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Publication number
CN102759646A
CN102759646A CN201210227980XA CN201210227980A CN102759646A CN 102759646 A CN102759646 A CN 102759646A CN 201210227980X A CN201210227980X A CN 201210227980XA CN 201210227980 A CN201210227980 A CN 201210227980A CN 102759646 A CN102759646 A CN 102759646A
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pin
capacitor
resistor
voltage comparator
grounded
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李毓宏
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Uni Trend Technology China Co Ltd
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Uni Trend Technology China Co Ltd
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Abstract

The invention discloses a measuring method of a harmonic multimeter, which is characterized by comprising the following steps: (1) arranging a universal meter body and arranging a functional circuit board in the universal meter body; (2) the functional circuit board is provided with a functional test unit, a central processing unit and a power supply unit which are connected with each other; (3) a signal conditioning circuit, a multimeter test circuit and a harmonic test circuit which are mutually connected are arranged in the function test unit; (4) a software control platform is arranged in the central processing unit; (5) power up operates the multimeter. The invention also discloses a device for implementing the method. The invention integrates the universal meter and the harmonic analyzer into a whole, so that the test is more convenient and quicker, and the carrying is convenient.

Description

A kind of method of testing of harmonic wave multimeter and device
Technical field
The present invention relates to electronic information field, also relate to the electronic surveying field, the device that is specifically related to a kind of measuring method of harmonic wave multimeter and realizes this method.
Background technology
The basic reason that harmonic wave produces in electric system is because due to the nonlinear load.When electric current is flowed through load, not linear with added voltage, just form non-sinusoidal current, promptly there is harmonic wave to produce in the circuit.Direct current transportation, the widespread use of high-power single-phase rectifier technology on industrial sector and consumer.Cause current waveform distortion and three-phase imbalance serious day by day, become the key factor that influences the quality of power supply.Impact power load (like electric arc furnaces, direct-current transmission converter station) can make line voltage fluctuate after dropping into operation of power networks, thereby has seriously disturbed the normal operation of fluctuate in the electrical network sensitive load such as illumination, computing machine, precision electronic device etc.Numerous in computing machine, the precise electronic and the power electronic equipment of microprocessor control use in electric system in a large number, and be increasingly high to the sensitivity of power supply quality, and they are more responsive than electromechanical equipment to system interference, and are therefore also higher to the requirement of the quality of power supply.In case power quality problem occurs, gently then cause equipment failure, heavy then cause the damage of total system, the loss that brings thus is difficult to the appraisal.In addition, a large amount of for enhancing productivity, energy savings and reduce environmental pollution and adopt just becoming the main source of power quality problem based on the state-of-the-art facility of Power Electronic Technique.So these problems need harmonic analysis instrument to assist solution.
Multimeter harmonic analyser in the market all is independently, and our electric power and quality testing department etc. in actual detected when using, except the basic parameter test of multimeter (comprises voltage; Frequency, break-make, electric current; Electric capacity and temperature etc.) outside, to carry out the frequency analysis of electrical network toward contact, need choose the various different electronic measuring instruments of difference in functionality like this; Can't be integrated in the different functions measurement on a kind of instrument, make its measuring process more loaded down with trivial details, it is big to measure labour intensity; Increase to measure cost, bring a lot of inconvenience, and the measurement instrument of a plurality of simple functions not only involves great expense but also carries inconvenience to measurement.
So, develop a kind of frequency analysis function and function of multimeter in the instrument of one, just become comparatively exigence.
Summary of the invention
The objective of the invention is in order effectively to solve measurement instrument function singleness problem; Combine multimeter harmonic analyser in the market simultaneously and develop a kind of measuring method and device of harmonic wave multimeter, this multimeter has intelligent high; Degree of accuracy is high, easy to use, characteristics efficiently.
The present invention for realizing the technical scheme that above-mentioned purpose adopted is:
A kind of measuring method of harmonic wave multimeter, it may further comprise the steps:
(1) a multimeter body is set, and portion is provided with a functional circuit plate within it;
(2) on said functional circuit plate, interconnective functional test unit, CPU and power supply unit are set;
(3) in described functional test unit, interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit are set; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit;
(4) a software control platform is set in described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module;
(5) power up and start working, at first, by the software control platform according to the program that pre-sets; Selection is tested in the functional test unit, after project to be tested is selected, use the multimeter probe to begin the signal that the Information Monitoring source is sent; Through signal conditioning circuit, after the signal of being gathered nursed one's health, transfer in the pairing test circuit of selected test function; After test circuit is tested signal; Test data is transferred to CPU, and test data is exported test result after the CPU computational analysis.
Described step (5) also comprises: when selecting the multimeter test function, described function selecting module is according to user's selection; Corresponding test function is provided; Then information source is gathered, after signal conditioning circuit carries out pre-service to the signal of gathering, transfer among the ASIC; After communicating and handle through ASIC and CPU then, the output signal; When selecting the frequency analysis function; Harmonic signal obtains the frequency of fundamental signal after the signal conditioning circuit conditioning, this signal transfers to CPU behind the fundamental frequency test circuit; CPU obtains corresponding SF according to the high-speed ADC Acquisition Circuit; Then through CPU, calculate corresponding harmonic wave size and other parameters after, the output result.
Software control platform described in the step (4) is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
The described signal conditioning circuit of step (3) comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
The described fundamental frequency test circuit of step (3) comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
The described power circuit of step (3) comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
A kind of device of implementing the right said method, it comprises a multimeter body, and is positioned at the circuit part of body interior, described circuit part comprises interconnective functional test unit, CPU and power supply unit; Described functional test unit comprises interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit; One software control platform is set in the described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module; Go back correspondence on the described multimeter body and be provided with function conversion knob; And following a plurality of additional function buttons: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test button; When using the signal that the multimeter probe begins to be sent in the Information Monitoring source, test function is selected, behind the intact signal to be collected; After nursing one's health through signal conditioning circuit; Transfer in the pairing test circuit of selected test function, test circuit transfers to CPU with test data after signal is tested; Test data is exported test result after the CPU computational analysis.
Described multimeter body is provided with function conversion knob, and following a plurality of additional function buttons: the HOLD data keep, MAX/MIN maximum/minimum value; RANGE switches automatically and hand range; LIGHT is backlight, SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
Described signal conditioning circuit comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
Described fundamental frequency test circuit comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
Described power circuit comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
Described CPU comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
The TMS320C25 chip that described dsp chip adopts TI company to produce, this chip is high performance monolithic signal processor; Described fpga chip adopts panasonic semiconductor CLAy31 chip; The multiplication speed of this each multiplier of chip is with MHz; And the percentage of implementing the required FPGA of multiplier is recently arranged; Cooperate dsp chip to use,, thereby improved the work efficiency of multimeter the arithmetic capability that improves multimeter of the present invention greatly.
The present invention becomes one with multimeter harmonic analyser; Make the user the time, need not to use two surveying instruments, and use the present invention just can reach the measurement purpose analysis of harmonic and other functional tests; And the combination additional function, thereby can realize measuring accurately, convenient and quick.
Description of drawings
Fig. 1 is a hardware capability module map of the present invention;
Fig. 2 is signal conditioning circuit figure of the present invention;
Fig. 3 is fundamental frequency test circuit figure of the present invention;
Fig. 4 is a power circuit diagram of the present invention;
Fig. 5 is central processing circuit of the present invention and ADC Acquisition Circuit.
Embodiment
Embodiment: referring to Fig. 1 to Fig. 5, present embodiment provides a kind of measuring method of harmonic wave multimeter, and it may further comprise the steps:
(1) a multimeter body is set, and portion is provided with a functional circuit plate within it;
(2) on said functional circuit plate, interconnective functional test unit, CPU and power supply unit are set;
(3) in described functional test unit, interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit are set; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit;
(4) a software control platform is set in described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module;
(5) power up and start working, at first, by the software control platform according to the program that pre-sets; Selection is tested in the functional test unit, after project to be tested is selected, use the multimeter probe to begin the signal that the Information Monitoring source is sent; Through signal conditioning circuit, after the signal of being gathered nursed one's health, transfer in the pairing test circuit of selected test function; After test circuit is tested signal; Test data is transferred to CPU, and test data is exported test result after the CPU computational analysis.
Described step (5) also comprises: when selecting the multimeter test function, described function selecting module is according to user's selection; Corresponding test function is provided; Then information source is gathered, after signal conditioning circuit carries out pre-service to the signal of gathering, transfer among the ASIC; After communicating and handle through ASIC and CPU then, the output signal; When selecting the frequency analysis function; Harmonic signal obtains the frequency of fundamental signal after the signal conditioning circuit conditioning, this signal transfers to CPU behind the fundamental frequency test circuit; CPU obtains corresponding SF according to the high-speed ADC Acquisition Circuit; Then through CPU, calculate corresponding harmonic wave size and other parameters after, the output result.
Software control platform described in the step (4) is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
The described signal conditioning circuit of step (3) comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
The described fundamental frequency test circuit of step (3) comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
The described power circuit of step (3) comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
A kind of device of implementing the right said method, it comprises a multimeter body, and is positioned at the circuit part of body interior, described circuit part comprises interconnective functional test unit, CPU and power supply unit; Described functional test unit comprises interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit; One software control platform is set in the described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module; Go back correspondence on the described multimeter body and be provided with function conversion knob; And following a plurality of additional function buttons: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test button; When using the signal that the multimeter probe begins to be sent in the Information Monitoring source, test function is selected, behind the intact signal to be collected; After nursing one's health through signal conditioning circuit; Transfer in the pairing test circuit of selected test function, test circuit transfers to CPU with test data after signal is tested; Test data is exported test result after the CPU computational analysis.
Described multimeter body is provided with function conversion knob, and following a plurality of additional function buttons: the HOLD data keep, MAX/MIN maximum/minimum value; RANGE switches automatically and hand range; LIGHT is backlight, SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
Described signal conditioning circuit comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
Described fundamental frequency test circuit comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
Described power circuit comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
The TMS320C25 chip that described dsp chip adopts TI company to produce, this chip is high performance monolithic signal processor; Described fpga chip adopts panasonic semiconductor CLAy31 chip; The multiplication speed of this each multiplier of chip is with MHz; And the percentage of implementing the required FPGA of multiplier is recently arranged; Cooperate dsp chip to use,, thereby improved the work efficiency of multimeter the arithmetic capability that improves multimeter of the present invention greatly.
This electronic measuring device can be connected with PC through the usb communication module, operation virtual digit multimeter software on PC; USB control is desired the multi-path digital amount output unit generation measurement conversion and the range of data acquisition module and is changed needed control signal; After multi-analog is changed through A/D converter; Be transferred to PC through usb bus,, on PC, show measured data through the data processing of PC software.
Multimeter major function measurement range of the present invention: alternating voltage is 0V ~ 1000V, and frequency response is 45Hz ~ 1000Hz, measuring accuracy is ± (2%+3); DC voltage is 0 ~ 1000V, measuring accuracy is ± (2%+3); Alternating current is 0 ~ 1A, and frequency response is 45Hz ~ 1000Hz, measuring accuracy is ± (2%+5); DC current is 0 ~ 1A, measuring accuracy is ± (2%+3); Resistance is 0 ~ 40M Ω, measuring accuracy is ± (1%+3); Electric capacity is 0 ~ 1000 μ F, measuring accuracy is ± (3%+5); Frequency is 0.01Hz ~ 1MHz, measuring accuracy is ± (0.1%+3); Temperature is-40 ℃ ~ 1000 ℃, measuring accuracy is ± (3%+5).
Frequency analysis functional measurement scope of the present invention: frequency analysis voltage range: 30V ~ 600V; Frequency analysis range of current: 5A ~ 100A; Frequency analysis frequency response (fundamental frequency): 50Hz~60Hz; Measuring accuracy: 1 subharmonic: ± (3%+10); 2 ~ 6 subharmonic: ± (3.5%+10); 7 ~ 8 subharmonic: ± (4.5%+10); 9 ~ 10 subharmonic: ± (5%+10); 11 ~ 15 subharmonic: ± (7%+10); 16 ~ 21 subharmonic: ± (10%+10).
Advantage of the present invention is: integrate multimeter harmonic analyser, make that test is convenient, quick, in conjunction with additional function of the present invention; Feasible use is intelligent more; And improved measuring accuracy and measuring speed greatly, easy to carry, also practiced thrift purchase cost simultaneously.
But the above is merely preferable possible embodiments of the present invention, is not in order to limit to claim of the present invention, so the equivalent structure that all utilizations instructions of the present invention and accompanying drawing content are done changes, all to be included in protection scope of the present invention.

Claims (10)

1.一种谐波万用表的测量方法,其特征在于,其包括以下步骤:1. a measuring method of harmonic multimeter, is characterized in that, it comprises the following steps: (1)设置一万用表本体,并在其内部设置一功能电路板;(1) Set a multimeter body, and set a functional circuit board inside it; (2)在所述功能电路板上,设置相互连接的功能测试单元、中央处理单元和电源单元;(2) On the functional circuit board, a functional test unit, a central processing unit and a power supply unit connected to each other are arranged; (3)在所述的功能测试单元内,设置相互连接的信号调理电路、万用表测试电路和谐波测试电路;其中所述万用表测试电路为一万用表专用集成芯片,所述的谐波测试电路包括基频测试电路和高速ADC采集电路;(3) In the functional test unit, a signal conditioning circuit, a multimeter test circuit and a harmonic test circuit connected to each other are set; wherein the multimeter test circuit is a special integrated chip for a multimeter, and the harmonic test circuit includes Fundamental frequency test circuit and high-speed ADC acquisition circuit; (4)在所述的中央处理单元内设置一软件控制平台,所述的软件控制平台设置有如下附加功能模块:HOLD数据保持,MAX/MIN最大/最小值,RANGE切换自动和手动量程,LIGHT背光,SAVE存储,RECALL读存储的数据和LOCK漏电开关锁定测试模块;(4) A software control platform is set in the central processing unit, and the software control platform is provided with the following additional functional modules: HOLD data retention, MAX/MIN maximum/minimum value, RANGE switching between automatic and manual ranges, LIGHT Backlight, SAVE storage, RECALL read stored data and LOCK leakage switch lock test module; (5)加电开始工作,首先,由软件控制平台根据预先设置好的程序,对功能测试单元进行测试选择,待测试项目选定后,使用万用表探针开始采集信息源所发出的信号;当选择万用表测试功能时,所述的功能选择模块,根据用户的选择,提供相应的测试功能,然后对信息源进行采集,经信号调理电路对采集的信号进行预处理后,传输至ASIC中,然后通过ASIC与中央处理单元进行通信和处理后,输出信号;当选择谐波分析功能时,谐波信号经信号调理电路调理后得到基波信号的频率,该信号经基频测试电路后,传输至中央处理单元,中央处理单元根据高速ADC采集电路得到相应的采样频率,然后通过中央处理单元,算出相应的谐波大小和其他参数后,输出结果。(5) Power up and start working. First, the software control platform will test and select the functional test unit according to the preset program. After the test item is selected, use the multimeter probe to start collecting the signal from the information source; when When the multimeter test function is selected, the function selection module provides a corresponding test function according to the user's selection, and then collects the information source, and after the signal conditioning circuit preprocesses the collected signal, it is transmitted to the ASIC, and then After communicating and processing with the central processing unit through ASIC, the signal is output; when the harmonic analysis function is selected, the frequency of the fundamental signal is obtained after the harmonic signal is conditioned by the signal conditioning circuit, and the signal is transmitted to the The central processing unit, the central processing unit obtains the corresponding sampling frequency according to the high-speed ADC acquisition circuit, and then calculates the corresponding harmonic magnitude and other parameters through the central processing unit, and outputs the result. 2.根据权利要求1所述的谐波万用表的测量方法,其特征在于,步骤(3)所述的信号调理电路包括电阻(R1)、电阻(R2)、电阻(R3)、电阻(R4)、电阻(R5)、电阻(R6)、电压比较器(U8A)、线性器件(U7)、信号输入端子(V1_A)和信号输入端子(V1_B),其中所述的线性器件U7的第6脚和第8脚接地,第7脚接电源VEE,第16脚接电源VCC,第9脚与信号输入端子V1_B相连,第10脚与信号输入端子V1A相连,第11脚与电阻R3的一端及电阻R4的一端相连,第15脚与电阻R3的另一端及电阻R2的一端相连,第14脚与电阻R2的另一端及电阻R1的一端相连,第12脚与R1的另一端相连,第13脚与电压比较器U8A的第2脚相连接,电压比较器的第1脚输出信号,电压比较器的第3脚与电阻R5的一端及电阻R6的一端相连,电阻R5的另一端连接万用表Voltage接口,电阻R6的另一端与万用表COM端相连并接地。2. The measurement method of a harmonic multimeter according to claim 1, characterized in that the signal conditioning circuit in step (3) includes a resistor (R1), a resistor (R2), a resistor (R3), and a resistor (R4) , resistor (R5), resistor (R6), voltage comparator (U8A), linear device (U7), signal input terminal (V1_A) and signal input terminal (V1_B), wherein the 6th pin of the linear device U7 and The 8th pin is grounded, the 7th pin is connected to the power supply VEE, the 16th pin is connected to the power supply VCC, the 9th pin is connected to the signal input terminal V1_B, the 10th pin is connected to the signal input terminal V1A, the 11th pin is connected to one end of the resistor R3 and the resistor R4 Connected to one end of the resistor R3, the 15th pin is connected to the other end of the resistor R3 and one end of the resistor R2, the 14th pin is connected to the other end of the resistor R2 and one end of the resistor R1, the 12th pin is connected to the other end of R1, and the 13th pin is connected to the other end of the resistor R1. The second pin of the voltage comparator U8A is connected, the first pin of the voltage comparator outputs a signal, the third pin of the voltage comparator is connected to one end of the resistor R5 and one end of the resistor R6, and the other end of the resistor R5 is connected to the voltage interface of the multimeter. The other end of the resistor R6 is connected to the COM terminal of the multimeter and grounded. 3.根据权利要求1所述的谐波万用表的测量方法,其特征在于,步骤(3)所述的基频测试电路包括电阻(R7)、电阻(R8)、电阻(R9)、电阻(R10)、电阻(R11)、电阻(R12)、电阻(R13)、电阻(R14)、电阻(R15)、电压比较器(U9A)、电压比较器(U10A)、电压比较器(U11A)、电压比较器(U12A)、电压比较器(U13A)、电压比较器(U14A)、电容(C1)、电容(C2)、电容(C3)、电容(C4)、电容(C5)、电容(C6)和电容(C7),其中所述的电压比较器U9A的第2脚连接信号输入端,第1脚与第3脚及电阻R7的一端相连,电压比较其U10A的第2脚与电阻R7的另一端及电容C1的一端相连,第1脚与第3脚及电阻R8的一端相连,电容C1的另一端接地,电阻R8的另一端与电容C5的一端及电阻R9的一端相连,电压比较器U11A的第2脚与电阻R9的另一端及电容C2的一端相连,第1脚与第3脚、电容C5的另一端及电阻R10的一端相连,电容C2的另一端接地,电阻R10的另一端与电容C6的一端及电阻R11的一端相连,电压比较器U12A的第2脚与电阻R11的另一端及电容C3的一端相连,第1脚与第3脚、电容C6的另一端及电阻R12的一端相连,电容C3另一端接地,电阻R12的另一端与电容C7的一端及电阻R13的一端连接,电压比较器U13A的第2脚与电阻R13的另一端及电容C4的一端相连,第1脚与第3脚、电容C7的另一端及电压比较器U14A的第2脚相连,电容C4的另一端接地,电压比较器U14A的第3脚与电阻R14的一端及电阻R15的一端相连,第1脚与电阻R15的另一端相连,并输出信号,电阻R14的另一端接地。3. The measurement method of the harmonic multimeter according to claim 1, characterized in that the fundamental frequency test circuit in step (3) includes a resistor (R7), a resistor (R8), a resistor (R9), a resistor (R10 ), resistor (R11), resistor (R12), resistor (R13), resistor (R14), resistor (R15), voltage comparator (U9A), voltage comparator (U10A), voltage comparator (U11A), voltage comparator (U12A), voltage comparator (U13A), voltage comparator (U14A), capacitor (C1), capacitor (C2), capacitor (C3), capacitor (C4), capacitor (C5), capacitor (C6) and capacitor (C7), wherein the second pin of the voltage comparator U9A is connected to the signal input terminal, the first pin is connected to the third pin and one end of the resistor R7, and the voltage is compared between the second pin of U10A and the other end of the resistor R7 and One end of the capacitor C1 is connected, the first pin is connected with the third pin and one end of the resistor R8, the other end of the capacitor C1 is grounded, the other end of the resistor R8 is connected with one end of the capacitor C5 and one end of the resistor R9, the first end of the voltage comparator U11A Pin 2 is connected to the other end of resistor R9 and one end of capacitor C2, pin 1 is connected to pin 3, the other end of capacitor C5 and one end of resistor R10, the other end of capacitor C2 is grounded, and the other end of resistor R10 is connected to capacitor C6 One end of the voltage comparator U12A is connected to one end of the resistor R11, the second pin of the voltage comparator U12A is connected to the other end of the resistor R11 and one end of the capacitor C3, the first pin is connected to the third pin, the other end of the capacitor C6 and one end of the resistor R12, The other end of the capacitor C3 is grounded, the other end of the resistor R12 is connected to one end of the capacitor C7 and one end of the resistor R13, the second pin of the voltage comparator U13A is connected to the other end of the resistor R13 and one end of the capacitor C4, and the first pin is connected to the third Pin, the other end of capacitor C7 is connected to the second pin of voltage comparator U14A, the other end of capacitor C4 is grounded, the third pin of voltage comparator U14A is connected to one end of resistor R14 and one end of resistor R15, and the first pin is connected to resistor The other end of R15 is connected to output a signal, and the other end of resistor R14 is grounded. 4.根据权利要求1所述的谐波万用表的测量方法,其特征在于,步骤(3)所述的电源电路包括线性器件(U4)、线性器件(U5)、线性器件(U6)、三极管(Q1)、三极管(Q2)、三极管(Q3)、二极管(D1)、二极管(D2)、二极管(D3)、二极管(D4)、电容(C8)、电容(C9)、电容(C10)、电容(C11)、电容(C12)、电容(C13)、电容(C14)、电容(C15)、电容(C16)、电容(C17)、电容(C18)、按键(S1)、电阻(R16)、电阻(R17)、电阻(R18)、电阻(R19)、电阻(R20)、电阻(R21)、电感(L1)和电源(BATT),其中所述的电源BATT负极接地,正极与二极管D1正极连接,二极管D1负极与电阻R17的一端及三极管Q1的发射极相连,电阻R17的另一端与二极管D2的正极、电阻R18的一端及三极管Q2的集电极相连,二极管D2的负极与二极管D3的负极及按键S1的一端连接,按键S1的另一端接地,二极管D3的正极连接电阻R16的一端,并与开关信号端相连,电阻R16的另一端接电源VCC1,三极管Q1的基极与电阻R18的另一端连接,三极管Q2的发射极接地,基极与电阻R19的一端及三极管Q3的集电极相连,电阻R19的另一端与电阻R20的一端相接,并连接电源VCC1,三极管Q3的发射极接地,基极连接电阻R21的一端,电阻R21的另一端连接电阻R20的另一端,并与电源输入端相连,三极管Q1的集电极与电容C8的正极及线性器件U4的第7脚相连,并连接+9V电源,电容C8的负极接地,线性器件U4的第6脚接地,第1脚连接电容C18的一端,第4脚与电容C9及线性器件U5的第1脚相连,第8脚与电容C8的另一端、二极管D4的负极及电感L1的一端相连,电容C9的负极接地,二极管D4的正极接地,电感L1的另一端连接电容C10的正极,并提供电源VCC,电容C10的负极接地,线性器件U5的第2脚连接电容C12的一端,第4脚连接电容C12的另一端,第3脚接地,第5脚连接电容C13的一端连接,并输出电源VEE,第8脚连接电容C11的一端连接,电容C11与C13的另一端接地均接地,线性器件U6的第1脚与电容C14的一端及电容C15的正极相连,并接电源VCC,第2脚接地,第3脚与电容C16的正极及电容C17的一端连接,并输出电源VCC1,电容C14的另一端、C15的负极、C16的负极和C17的另一端均接地。4. The measurement method of harmonic multimeter according to claim 1, characterized in that the power supply circuit in step (3) includes a linear device (U4), a linear device (U5), a linear device (U6), a triode ( Q1), transistor (Q2), transistor (Q3), diode (D1), diode (D2), diode (D3), diode (D4), capacitor (C8), capacitor (C9), capacitor (C10), capacitor ( C11), capacitor (C12), capacitor (C13), capacitor (C14), capacitor (C15), capacitor (C16), capacitor (C17), capacitor (C18), button (S1), resistor (R16), resistor ( R17), resistor (R18), resistor (R19), resistor (R20), resistor (R21), inductor (L1) and power supply (BATT), wherein the negative pole of the power supply BATT is grounded, the positive pole is connected to the positive pole of the diode D1, and the diode The negative pole of D1 is connected with one end of the resistor R17 and the emitter of the transistor Q1, the other end of the resistor R17 is connected with the positive pole of the diode D2, one end of the resistor R18 and the collector of the transistor Q2, and the negative pole of the diode D2 is connected with the negative pole of the diode D3 and the button S1 One end of the button S1 is connected to the ground, the anode of the diode D3 is connected to one end of the resistor R16 and connected to the switch signal end, the other end of the resistor R16 is connected to the power supply VCC1, the base of the transistor Q1 is connected to the other end of the resistor R18, The emitter of the transistor Q2 is grounded, the base is connected to one end of the resistor R19 and the collector of the transistor Q3, the other end of the resistor R19 is connected to one end of the resistor R20, and connected to the power supply VCC1, the emitter of the transistor Q3 is grounded, and the base is connected to One end of the resistor R21, the other end of the resistor R21 is connected to the other end of the resistor R20 and connected to the input terminal of the power supply, the collector of the transistor Q1 is connected to the positive pole of the capacitor C8 and the seventh pin of the linear device U4, and connected to the +9V power supply, The negative pole of the capacitor C8 is grounded, the sixth pin of the linear device U4 is grounded, the first pin is connected to one end of the capacitor C18, the fourth pin is connected to the capacitor C9 and the first pin of the linear device U5, the eighth pin is connected to the other end of the capacitor C8, The negative pole of the diode D4 is connected to one end of the inductor L1, the negative pole of the capacitor C9 is grounded, the positive pole of the diode D4 is grounded, the other end of the inductor L1 is connected to the positive pole of the capacitor C10, and the power supply VCC is provided, the negative pole of the capacitor C10 is grounded, and the first pole of the linear device U5 Pin 2 is connected to one end of capacitor C12, pin 4 is connected to the other end of capacitor C12, pin 3 is grounded, pin 5 is connected to one end of capacitor C13 to output power VEE, pin 8 is connected to one end of capacitor C11, capacitor C11 The other end of C13 is grounded, the first pin of the linear device U6 is connected to one end of the capacitor C14 and the positive pole of the capacitor C15, and connected to the power supply VCC, the second pin is grounded, and the third pin is connected to the positive pole of the capacitor C16 and the positive pole of the capacitor C17 Connect one end and output the power supply VCC1, the other end of capacitor C14, the negative pole of C15, C The negative pole of 16 and the other end of C17 are both grounded. 5.根据权利要求1所述的谐波万用表的测量方法,其特征在于,步骤(2)所述的中央处理单元包括一DSP芯片和一FPGA芯片,其中所述的DSP芯片的A15-A0脚与FPGA芯片的A15-A0脚通过BUS总线相接,DSP芯片的/IS脚与FPGA芯片的/EN脚相接,DSP芯片的/STRB脚与FPGA芯片的/STRB脚相接,DSP芯片的R/W脚与FPGA芯片的R/W脚相接,DSP芯片的READY脚与FPGA芯片的READY脚相接,DSP芯片的/MSC脚与FPGA芯片的/MSC脚相接,DSP芯片的/INTn脚与高速ADC芯片的BUSY脚相接,DSP芯片的D0-D15脚与高速ADC芯片的D0-D15脚通过BUS总线相接,FPGA芯片的/CS脚与高速ADC芯片的/CS脚相接,FPGA芯片的A0脚与高速ADC芯片的A0脚相接,FPGA芯片的/READ脚与高速ADC芯片的/READ脚相接。5. The measurement method of a harmonic multimeter according to claim 1, wherein the central processing unit in step (2) includes a DSP chip and an FPGA chip, wherein the A15-A0 pins of the DSP chip It is connected with the A15-A0 pin of the FPGA chip through the BUS bus, the /IS pin of the DSP chip is connected with the /EN pin of the FPGA chip, the /STRB pin of the DSP chip is connected with the /STRB pin of the FPGA chip, and the R The /W pin is connected to the R/W pin of the FPGA chip, the READY pin of the DSP chip is connected to the READY pin of the FPGA chip, the /MSC pin of the DSP chip is connected to the /MSC pin of the FPGA chip, and the /INTn pin of the DSP chip is connected It is connected with the BUSY pin of the high-speed ADC chip, the D0-D15 pin of the DSP chip is connected with the D0-D15 pin of the high-speed ADC chip through the BUS bus, the /CS pin of the FPGA chip is connected with the /CS pin of the high-speed ADC chip, and the FPGA chip is connected with the /CS pin of the high-speed ADC chip. The A0 pin of the chip is connected with the A0 pin of the high-speed ADC chip, and the /READ pin of the FPGA chip is connected with the /READ pin of the high-speed ADC chip. 6.一种实施权利要求1-5之一所述方法的装置,其包括一万用表本体,及位于本体内部的电路部分,其特征在于,所述的电路部分包括相互连接的功能测试单元、中央处理单元和电源单元;所述的功能测试单元,包括相互连接的信号调理电路、万用表测试电路和谐波测试电路;其中所述万用表测试电路为一万用表专用集成芯片,所述的谐波测试电路包括基频测试电路和高速ADC采集电路;所述的中央处理单元内设置一软件控制平台,所述的软件控制平台设置有如下附加功能模块:HOLD数据保持,MAX/MIN最大/最小值,RANGE切换自动和手动量程,LIGHT背光,SAVE存储,RECALL读存储的数据和LOCK漏电开关锁定测试模块;所述的万用表本体上还对应设有一功能转换旋钮,及如下多个附加功能按键:HOLD数据保持,MAX/MIN最大/最小值,RANGE切换自动和手动量程,LIGHT背光,SAVE存储,RECALL读存储的数据和LOCK漏电开关锁定测试按键;使用万用表探针开始采集信息源所发出的信号时,对测试功能进行选择,待采集完信号后,通过信号调理电路进行调理后,传输至所选定的测试功能所对应的测试电路中,测试电路对信号进行测试后,将测试数据传输至中央处理单元,测试数据经中央处理单元计算分析后,将测试结果输出。6. A device for implementing the method according to one of claims 1-5, comprising a multimeter body, and a circuit part positioned inside the body, characterized in that, the circuit part includes interconnected functional test units, a central Processing unit and power supply unit; Described function test unit, comprises the signal conditioning circuit of interconnection, multimeter test circuit and harmonic test circuit; Wherein described multimeter test circuit is a multimeter ASIC, and described harmonic test circuit Including a fundamental frequency test circuit and a high-speed ADC acquisition circuit; a software control platform is set in the central processing unit, and the software control platform is provided with the following additional functional modules: HOLD data retention, MAX/MIN maximum/minimum value, RANGE Switch between automatic and manual ranges, LIGHT backlight, SAVE storage, RECALL to read stored data and LOCK leakage switch to lock the test module; the multimeter body is also equipped with a function conversion knob and the following additional function buttons: HOLD data hold , MAX/MIN maximum/minimum value, RANGE switch between automatic and manual range, LIGHT backlight, SAVE storage, RECALL read stored data and LOCK leakage switch lock test button; The test function is selected. After the signal is collected, it is conditioned by the signal conditioning circuit and then transmitted to the test circuit corresponding to the selected test function. After the test circuit tests the signal, the test data is transmitted to the central processing unit. , after the test data is calculated and analyzed by the central processing unit, the test result is output. 7.根据权利要求6所述的谐波万用表的测量装置,其特征在于,所述的信号调理电路包括电阻(R1)、电阻(R2)、电阻(R3)、电阻(R4)、电阻(R5)、电阻(R6)、电压比较器(U8A)、线性器件(U7)、信号输入端子(V1A)和信号输入端子(V1B),其中所述的线性器件U7的第6脚和第8脚接地,第7脚接电源VEE,第16脚接电源VCC,第9脚与信号输入端子V1B相连,第10脚与信号输入端子V1_A相连,第11脚与电阻R3的一端及电阻R4的一端相连,第15脚与电阻R3的另一端及电阻R2的一端相连,第14脚与电阻R2的另一端及电阻R1的一端相连,第12脚与R1的另一端相连,第13脚与电压比较器U8A的第2脚相连接,电压比较器的第1脚输出信号,电压比较器的第3脚与电阻R5的一端及电阻R6的一端相连,电阻R5的另一端连接万用表Voltage接口,电阻R6的另一端与万用表COM端相连并接地。7. The measuring device of the harmonic multimeter according to claim 6, characterized in that the signal conditioning circuit includes a resistor (R1), a resistor (R2), a resistor (R3), a resistor (R4), a resistor (R5 ), resistor (R6), voltage comparator (U8A), linear device (U7), signal input terminal (V1A) and signal input terminal (V1B), wherein the 6th and 8th pins of the linear device U7 are grounded , the 7th pin is connected to the power supply VEE, the 16th pin is connected to the power supply VCC, the 9th pin is connected to the signal input terminal V1B, the 10th pin is connected to the signal input terminal V1_A, the 11th pin is connected to one end of the resistor R3 and one end of the resistor R4, Pin 15 is connected to the other end of resistor R3 and one end of resistor R2, pin 14 is connected to the other end of resistor R2 and one end of resistor R1, pin 12 is connected to the other end of R1, pin 13 is connected to voltage comparator U8A The 2nd pin of the voltage comparator is connected, the 1st pin of the voltage comparator outputs the signal, the 3rd pin of the voltage comparator is connected with one end of the resistor R5 and one end of the resistor R6, the other end of the resistor R5 is connected with the voltage interface of the multimeter, and the other end of the resistor R6 One end is connected to the COM terminal of the multimeter and grounded. 8.根据权利要求6所述的谐波万用表的测量装置,其特征在于,所述的基频测试电路包括电阻(R7)、电阻(R8)、电阻(R9)、电阻(R10)、电阻(R11)、电阻(R12)、电阻(R13)、电阻(R14)、电阻(R15)、电压比较器(U9A)、电压比较器(U10A)、电压比较器(U11A)、电压比较器(U12A)、电压比较器(U13A)、电压比较器(U14A)、电容(C1)、电容(C2)、电容(C3)、电容(C4)、电容(C5)、电容(C6)和电容(C7),其中所述的电压比较器U9A的第2脚连接信号输入端,第1脚与第3脚及电阻R7的一端相连,电压比较其U10A的第2脚与电阻R7的另一端及电容C1的一端相连,第1脚与第3脚及电阻R8的一端相连,电容C1的另一端接地,电阻R8的另一端与电容C5的一端及电阻R9的一端相连,电压比较器U11A的第2脚与电阻R9的另一端及电容C2的一端相连,第1脚与第3脚、电容C5的另一端及电阻R10的一端相连,电容C2的另一端接地,电阻R10的另一端与电容C6的一端及电阻R11的一端相连,电压比较器U12A的第2脚与电阻R11的另一端及电容C3的一端相连,第1脚与第3脚、电容C6的另一端及电阻R12的一端相连,电容C3另一端接地,电阻R12的另一端与电容C7的一端及电阻R13的一端连接,电压比较器U13A的第2脚与电阻R13的另一端及电容C4的一端相连,第1脚与第3脚、电容C7的另一端及电压比较器U14A的第2脚相连,电容C4的另一端接地,电压比较器U14A的第3脚与电阻R14的一端及电阻R15的一端相连,第1脚与电阻R15的另一端相连,并输出信号,电阻R14的另一端接地。8. The measuring device of the harmonic multimeter according to claim 6, characterized in that, the fundamental frequency test circuit includes a resistor (R7), a resistor (R8), a resistor (R9), a resistor (R10), a resistor ( R11), resistor (R12), resistor (R13), resistor (R14), resistor (R15), voltage comparator (U9A), voltage comparator (U10A), voltage comparator (U11A), voltage comparator (U12A) , voltage comparator (U13A), voltage comparator (U14A), capacitor (C1), capacitor (C2), capacitor (C3), capacitor (C4), capacitor (C5), capacitor (C6) and capacitor (C7), The second pin of the voltage comparator U9A is connected to the signal input terminal, the first pin is connected to the third pin and one end of the resistor R7, and the voltage is compared between the second pin of U10A and the other end of the resistor R7 and one end of the capacitor C1 The first pin is connected to the third pin and one end of the resistor R8, the other end of the capacitor C1 is grounded, the other end of the resistor R8 is connected to one end of the capacitor C5 and one end of the resistor R9, the second pin of the voltage comparator U11A is connected to the resistor The other end of R9 is connected to one end of capacitor C2, the first pin is connected to third pin, the other end of capacitor C5 and one end of resistor R10, the other end of capacitor C2 is grounded, the other end of resistor R10 is connected to one end of capacitor C6 and the resistor One end of R11 is connected, the second pin of the voltage comparator U12A is connected with the other end of the resistor R11 and one end of the capacitor C3, the first pin is connected with the third pin, the other end of the capacitor C6 and one end of the resistor R12, and the other end of the capacitor C3 Grounding, the other end of the resistor R12 is connected to one end of the capacitor C7 and one end of the resistor R13, the second pin of the voltage comparator U13A is connected to the other end of the resistor R13 and one end of the capacitor C4, the first pin is connected to the third pin, and the capacitor C7 The other end of the voltage comparator U14A is connected to the second pin of the voltage comparator U14A, the other end of the capacitor C4 is grounded, the third pin of the voltage comparator U14A is connected to one end of the resistor R14 and one end of the resistor R15, and the first pin is connected to the other end of the resistor R15 Connected and output signal, the other end of resistor R14 is grounded. 9.根据权利要求6所述的谐波万用表的测量装置,其特征在于,所述的电源单元为一电源电路,该电源电路包括线性器件(U4)、线性器件(U5)、线性器件(U6)、三极管(Q1)、三极管(Q2)、三极管(Q3)、二极管(D1)、二极管(D2)、二极管(D3)、二极管(D4)、电容(C8)、电容(C9)、电容(C10)、电容(C11)、电容(C12)、电容(C13)、电容(C14)、电容(C15)、电容(C16)、电容(C17)、电容(C18)、按键(S1)、电阻(R16)、电阻(R17)、电阻(R18)、电阻(R19)、电阻(R20)、电阻(R21)、电感(L1)和电源(BATT),其中所述的电源BATT负极接地,正极与二极管D1正极连接,二极管D1负极与电阻R17的一端及三极管Q1的发射极相连,电阻R17的另一端与二极管D2的正极、电阻R18的一端及三极管Q2的集电极相连,二极管D2的负极与二极管D3的负极及按键S1的一端连接,按键S1的另一端接地,二极管D3的正极连接电阻R16的一端,并与开关信号端相连,电阻R16的另一端接电源VCC1,三极管Q1的基极与电阻R18的另一端连接,三极管Q2的发射极接地,基极与电阻R19的一端及三极管Q3的集电极相连,电阻R19的另一端与电阻R20的一端相接,并连接电源VCC1,三极管Q3的发射极接地,基极连接电阻R21的一端,电阻R21的另一端连接电阻R20的另一端,并与电源输入端相连,三极管Q1的集电极与电容C8的正极及线性器件U4的第7脚相连,并连接+9V电源,电容C8的负极接地,线性器件U4的第6脚接地,第1脚连接电容C18的一端,第4脚与电容C9及线性器件U5的第1脚相连,第8脚与电容C8的另一端、二极管D4的负极及电感L1的一端相连,电容C9的负极接地,二极管D4的正极接地,电感L1的另一端连接电容C10的正极,并提供电源VCC,电容C10的负极接地,线性器件U5的第2脚连接电容C12的一端,第4脚连接电容C12的另一端,第3脚接地,第5脚连接电容C13的一端连接,并输出电源VEE,第8脚连接电容C11的一端连接,电容C11与C13的另一端接地均接地,线性器件U6的第1脚与电容C14的一端及电容C15的正极相连,并接电源VCC,第2脚接地,第3脚与电容C16的正极及电容C17的一端连接,并输出电源VCC1,电容C14的另一端、C15的负极、C16的负极和C17的另一端均接地。9. The measuring device of the harmonic multimeter according to claim 6, characterized in that, the power supply unit is a power supply circuit, and the power supply circuit includes a linear device (U4), a linear device (U5), a linear device (U6 ), transistor (Q1), transistor (Q2), transistor (Q3), diode (D1), diode (D2), diode (D3), diode (D4), capacitor (C8), capacitor (C9), capacitor (C10 ), capacitor (C11), capacitor (C12), capacitor (C13), capacitor (C14), capacitor (C15), capacitor (C16), capacitor (C17), capacitor (C18), button (S1), resistor (R16 ), resistance (R17), resistance (R18), resistance (R19), resistance (R20), resistance (R21), inductance (L1) and power supply (BATT), wherein the negative pole of the power supply BATT is grounded, and the positive pole is connected to the diode D1 The anode is connected, the cathode of the diode D1 is connected to one end of the resistor R17 and the emitter of the transistor Q1, the other end of the resistor R17 is connected to the anode of the diode D2, one end of the resistor R18 and the collector of the transistor Q2, and the cathode of the diode D2 is connected to the collector of the diode D3 The negative electrode is connected to one end of the button S1, the other end of the button S1 is grounded, the positive electrode of the diode D3 is connected to one end of the resistor R16 and connected to the switch signal end, the other end of the resistor R16 is connected to the power supply VCC1, the base of the transistor Q1 is connected to the resistor R18 The other end is connected, the emitter of the transistor Q2 is grounded, the base is connected with one end of the resistor R19 and the collector of the transistor Q3, the other end of the resistor R19 is connected with one end of the resistor R20, and connected to the power supply VCC1, and the emitter of the transistor Q3 is grounded , the base is connected to one end of the resistor R21, the other end of the resistor R21 is connected to the other end of the resistor R20, and connected to the power input end, the collector of the triode Q1 is connected to the positive pole of the capacitor C8 and the 7th pin of the linear device U4, and connected to +9V power supply, the negative pole of capacitor C8 is grounded, the sixth pin of linear device U4 is grounded, the first pin is connected to one end of capacitor C18, the fourth pin is connected to capacitor C9 and the first pin of linear device U5, and the eighth pin is connected to capacitor C8 The other end of the diode D4, the negative pole of the diode D4, and one end of the inductor L1 are connected, the negative pole of the capacitor C9 is grounded, the positive pole of the diode D4 is grounded, the other end of the inductor L1 is connected to the positive pole of the capacitor C10, and the power supply VCC is provided, and the negative pole of the capacitor C10 is grounded, linear The 2nd pin of the device U5 is connected to one end of the capacitor C12, the 4th pin is connected to the other end of the capacitor C12, the 3rd pin is grounded, the 5th pin is connected to one end of the capacitor C13, and the output power VEE is connected, and the 8th pin is connected to one end of the capacitor C11 Connection, the other ends of the capacitors C11 and C13 are both grounded, the first pin of the linear device U6 is connected to one end of the capacitor C14 and the positive pole of the capacitor C15, and connected to the power supply VCC, the second pin is grounded, and the third pin is connected to the positive pole of the capacitor C16 Connect with one end of capacitor C17, and output power supply VCC1, the other end of capacitor C14, C The negative pole of 15, the negative pole of C16 and the other end of C17 are all grounded. 10.根据权利要求6所述的谐波万用表的测量装置,其特征在于,所述的中央处理单元包括一DSP芯片和一FPGA芯片,其中所述的DSP芯片的A15-A0脚与FPGA芯片的A15-A0脚通过BUS总线相接,DSP芯片的/IS脚与FPGA芯片的/EN脚相接,DSP芯片的/STRB脚与FPGA芯片的/STRB脚相接,DSP芯片的R/W脚与FPGA芯片的R/W脚相接,DSP芯片的READY脚与FPGA芯片的READY脚相接,DSP芯片的/MSC脚与FPGA芯片的/MSC脚相接,DSP芯片的/INTn脚与高速ADC芯片的BUSY脚相接,DSP芯片的D0-D15脚与高速ADC芯片的D0-D15脚通过BUS总线相接,FPGA芯片的/CS脚与高速ADC芯片的/CS脚相接,FPGA芯片的A0脚与高速ADC芯片的A0脚相接,FPGA芯片的/READ脚与高速ADC芯片的/READ脚相接。10. the measuring device of harmonic multimeter according to claim 6, is characterized in that, described central processing unit comprises a DSP chip and an FPGA chip, and the A15-A0 pin of wherein said DSP chip and FPGA chip The A15-A0 pins are connected through the BUS bus, the /IS pin of the DSP chip is connected to the /EN pin of the FPGA chip, the /STRB pin of the DSP chip is connected to the /STRB pin of the FPGA chip, and the R/W pin of the DSP chip is connected to the /STRB pin of the FPGA chip. The R/W pin of the FPGA chip is connected, the READY pin of the DSP chip is connected with the READY pin of the FPGA chip, the /MSC pin of the DSP chip is connected with the /MSC pin of the FPGA chip, and the /INTn pin of the DSP chip is connected with the high-speed ADC chip The BUSY pins of the DSP chip are connected to the D0-D15 pins of the high-speed ADC chip through the BUS bus, the /CS pin of the FPGA chip is connected to the /CS pin of the high-speed ADC chip, and the A0 pin of the FPGA chip It is connected to the A0 pin of the high-speed ADC chip, and the /READ pin of the FPGA chip is connected to the /READ pin of the high-speed ADC chip.
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Application publication date: 20121031