CN102759646A - A kind of testing method and device of harmonic multimeter - Google Patents
A kind of testing method and device of harmonic multimeter Download PDFInfo
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- CN102759646A CN102759646A CN201210227980XA CN201210227980A CN102759646A CN 102759646 A CN102759646 A CN 102759646A CN 201210227980X A CN201210227980X A CN 201210227980XA CN 201210227980 A CN201210227980 A CN 201210227980A CN 102759646 A CN102759646 A CN 102759646A
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Abstract
The invention discloses a measuring method of a harmonic multimeter, which is characterized by comprising the following steps: (1) arranging a universal meter body and arranging a functional circuit board in the universal meter body; (2) the functional circuit board is provided with a functional test unit, a central processing unit and a power supply unit which are connected with each other; (3) a signal conditioning circuit, a multimeter test circuit and a harmonic test circuit which are mutually connected are arranged in the function test unit; (4) a software control platform is arranged in the central processing unit; (5) power up operates the multimeter. The invention also discloses a device for implementing the method. The invention integrates the universal meter and the harmonic analyzer into a whole, so that the test is more convenient and quicker, and the carrying is convenient.
Description
Technical field
The present invention relates to electronic information field, also relate to the electronic surveying field, the device that is specifically related to a kind of measuring method of harmonic wave multimeter and realizes this method.
Background technology
The basic reason that harmonic wave produces in electric system is because due to the nonlinear load.When electric current is flowed through load, not linear with added voltage, just form non-sinusoidal current, promptly there is harmonic wave to produce in the circuit.Direct current transportation, the widespread use of high-power single-phase rectifier technology on industrial sector and consumer.Cause current waveform distortion and three-phase imbalance serious day by day, become the key factor that influences the quality of power supply.Impact power load (like electric arc furnaces, direct-current transmission converter station) can make line voltage fluctuate after dropping into operation of power networks, thereby has seriously disturbed the normal operation of fluctuate in the electrical network sensitive load such as illumination, computing machine, precision electronic device etc.Numerous in computing machine, the precise electronic and the power electronic equipment of microprocessor control use in electric system in a large number, and be increasingly high to the sensitivity of power supply quality, and they are more responsive than electromechanical equipment to system interference, and are therefore also higher to the requirement of the quality of power supply.In case power quality problem occurs, gently then cause equipment failure, heavy then cause the damage of total system, the loss that brings thus is difficult to the appraisal.In addition, a large amount of for enhancing productivity, energy savings and reduce environmental pollution and adopt just becoming the main source of power quality problem based on the state-of-the-art facility of Power Electronic Technique.So these problems need harmonic analysis instrument to assist solution.
Multimeter harmonic analyser in the market all is independently, and our electric power and quality testing department etc. in actual detected when using, except the basic parameter test of multimeter (comprises voltage; Frequency, break-make, electric current; Electric capacity and temperature etc.) outside, to carry out the frequency analysis of electrical network toward contact, need choose the various different electronic measuring instruments of difference in functionality like this; Can't be integrated in the different functions measurement on a kind of instrument, make its measuring process more loaded down with trivial details, it is big to measure labour intensity; Increase to measure cost, bring a lot of inconvenience, and the measurement instrument of a plurality of simple functions not only involves great expense but also carries inconvenience to measurement.
So, develop a kind of frequency analysis function and function of multimeter in the instrument of one, just become comparatively exigence.
Summary of the invention
The objective of the invention is in order effectively to solve measurement instrument function singleness problem; Combine multimeter harmonic analyser in the market simultaneously and develop a kind of measuring method and device of harmonic wave multimeter, this multimeter has intelligent high; Degree of accuracy is high, easy to use, characteristics efficiently.
The present invention for realizing the technical scheme that above-mentioned purpose adopted is:
A kind of measuring method of harmonic wave multimeter, it may further comprise the steps:
(1) a multimeter body is set, and portion is provided with a functional circuit plate within it;
(2) on said functional circuit plate, interconnective functional test unit, CPU and power supply unit are set;
(3) in described functional test unit, interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit are set; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit;
(4) a software control platform is set in described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module;
(5) power up and start working, at first, by the software control platform according to the program that pre-sets; Selection is tested in the functional test unit, after project to be tested is selected, use the multimeter probe to begin the signal that the Information Monitoring source is sent; Through signal conditioning circuit, after the signal of being gathered nursed one's health, transfer in the pairing test circuit of selected test function; After test circuit is tested signal; Test data is transferred to CPU, and test data is exported test result after the CPU computational analysis.
Described step (5) also comprises: when selecting the multimeter test function, described function selecting module is according to user's selection; Corresponding test function is provided; Then information source is gathered, after signal conditioning circuit carries out pre-service to the signal of gathering, transfer among the ASIC; After communicating and handle through ASIC and CPU then, the output signal; When selecting the frequency analysis function; Harmonic signal obtains the frequency of fundamental signal after the signal conditioning circuit conditioning, this signal transfers to CPU behind the fundamental frequency test circuit; CPU obtains corresponding SF according to the high-speed ADC Acquisition Circuit; Then through CPU, calculate corresponding harmonic wave size and other parameters after, the output result.
Software control platform described in the step (4) is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
The described signal conditioning circuit of step (3) comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
The described fundamental frequency test circuit of step (3) comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
The described power circuit of step (3) comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
A kind of device of implementing the right said method, it comprises a multimeter body, and is positioned at the circuit part of body interior, described circuit part comprises interconnective functional test unit, CPU and power supply unit; Described functional test unit comprises interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit; One software control platform is set in the described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module; Go back correspondence on the described multimeter body and be provided with function conversion knob; And following a plurality of additional function buttons: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test button; When using the signal that the multimeter probe begins to be sent in the Information Monitoring source, test function is selected, behind the intact signal to be collected; After nursing one's health through signal conditioning circuit; Transfer in the pairing test circuit of selected test function, test circuit transfers to CPU with test data after signal is tested; Test data is exported test result after the CPU computational analysis.
Described multimeter body is provided with function conversion knob, and following a plurality of additional function buttons: the HOLD data keep, MAX/MIN maximum/minimum value; RANGE switches automatically and hand range; LIGHT is backlight, SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
Described signal conditioning circuit comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
Described fundamental frequency test circuit comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
Described power circuit comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
Described CPU comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
The TMS320C25 chip that described dsp chip adopts TI company to produce, this chip is high performance monolithic signal processor; Described fpga chip adopts panasonic semiconductor CLAy31 chip; The multiplication speed of this each multiplier of chip is with MHz; And the percentage of implementing the required FPGA of multiplier is recently arranged; Cooperate dsp chip to use,, thereby improved the work efficiency of multimeter the arithmetic capability that improves multimeter of the present invention greatly.
The present invention becomes one with multimeter harmonic analyser; Make the user the time, need not to use two surveying instruments, and use the present invention just can reach the measurement purpose analysis of harmonic and other functional tests; And the combination additional function, thereby can realize measuring accurately, convenient and quick.
Description of drawings
Fig. 1 is a hardware capability module map of the present invention;
Fig. 2 is signal conditioning circuit figure of the present invention;
Fig. 3 is fundamental frequency test circuit figure of the present invention;
Fig. 4 is a power circuit diagram of the present invention;
Fig. 5 is central processing circuit of the present invention and ADC Acquisition Circuit.
Embodiment
Embodiment: referring to Fig. 1 to Fig. 5, present embodiment provides a kind of measuring method of harmonic wave multimeter, and it may further comprise the steps:
(1) a multimeter body is set, and portion is provided with a functional circuit plate within it;
(2) on said functional circuit plate, interconnective functional test unit, CPU and power supply unit are set;
(3) in described functional test unit, interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit are set; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit;
(4) a software control platform is set in described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module;
(5) power up and start working, at first, by the software control platform according to the program that pre-sets; Selection is tested in the functional test unit, after project to be tested is selected, use the multimeter probe to begin the signal that the Information Monitoring source is sent; Through signal conditioning circuit, after the signal of being gathered nursed one's health, transfer in the pairing test circuit of selected test function; After test circuit is tested signal; Test data is transferred to CPU, and test data is exported test result after the CPU computational analysis.
Described step (5) also comprises: when selecting the multimeter test function, described function selecting module is according to user's selection; Corresponding test function is provided; Then information source is gathered, after signal conditioning circuit carries out pre-service to the signal of gathering, transfer among the ASIC; After communicating and handle through ASIC and CPU then, the output signal; When selecting the frequency analysis function; Harmonic signal obtains the frequency of fundamental signal after the signal conditioning circuit conditioning, this signal transfers to CPU behind the fundamental frequency test circuit; CPU obtains corresponding SF according to the high-speed ADC Acquisition Circuit; Then through CPU, calculate corresponding harmonic wave size and other parameters after, the output result.
Software control platform described in the step (4) is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
The described signal conditioning circuit of step (3) comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
The described fundamental frequency test circuit of step (3) comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
The described power circuit of step (3) comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.
The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
A kind of device of implementing the right said method, it comprises a multimeter body, and is positioned at the circuit part of body interior, described circuit part comprises interconnective functional test unit, CPU and power supply unit; Described functional test unit comprises interconnective signal conditioning circuit, multimeter test circuit harmonic test circuit; Wherein said multimeter test circuit is a multimeter special integrated chip, and described harmonic wave test circuit comprises fundamental frequency test circuit and high-speed ADC Acquisition Circuit; One software control platform is set in the described CPU; Described software control platform is provided with following additional function modules: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test module; Go back correspondence on the described multimeter body and be provided with function conversion knob; And following a plurality of additional function buttons: the HOLD data keep; MAX/MIN maximum/minimum value, RANGE switches automatically and hand range, and LIGHT is backlight; The SAVE storage, data that RECALL reads to store and LOCK leakage switch locking test button; When using the signal that the multimeter probe begins to be sent in the Information Monitoring source, test function is selected, behind the intact signal to be collected; After nursing one's health through signal conditioning circuit; Transfer in the pairing test circuit of selected test function, test circuit transfers to CPU with test data after signal is tested; Test data is exported test result after the CPU computational analysis.
Described multimeter body is provided with function conversion knob, and following a plurality of additional function buttons: the HOLD data keep, MAX/MIN maximum/minimum value; RANGE switches automatically and hand range; LIGHT is backlight, SAVE storage, the data that RECALL reads to store and LOCK leakage switch locking test.
Described signal conditioning circuit comprises resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, voltage comparator U8A, linear unit U7, signal input terminal V1_A and signal input terminal V1_B, the 6th pin of wherein said linear unit U7 and the 8th pin ground connection, and the 7th pin meets power supply VEE; The 16th pin meets power supply VCC; The 9th pin links to each other with signal input terminal V1_B, and the 10th pin links to each other with signal input terminal V1_A, and the 11st pin links to each other with an end of resistance R 3 and an end of resistance R 4; The 15th pin links to each other with the other end of resistance R 3 and an end of resistance R 2; The 14th pin links to each other with the other end of resistance R 2 and an end of resistance R 1, and the 12nd pin links to each other with the other end of R1, and the 13rd pin is connected with the 2nd pin of voltage comparator U8A; The 1st pin output signal of voltage comparator; The 3rd pin of voltage comparator links to each other with an end of an end of resistance R 5 and resistance R 6, and the other end of resistance R 5 connects multimeter Voltage interface, and the other end of resistance R 6 links to each other and ground connection with multimeter COM end;
Described fundamental frequency test circuit comprises resistance R 7, resistance R 8, resistance R 9, resistance R 10, resistance R 11, resistance R 12, resistance R 13, resistance R 14, resistance R 15, voltage comparator U9A, voltage comparator U10A, voltage comparator U11A, voltage comparator U12A, voltage comparator U13A, voltage comparator U14A, capacitor C 1, capacitor C 2, capacitor C 3, capacitor C 4, capacitor C 5, capacitor C 6 and capacitor C 7; The 2nd pin of wherein said voltage comparator U9A connects signal input part; The 1st pin links to each other with an end of the 3rd pin and resistance R 7; Voltage ratio links to each other with the other end of resistance R 7 and an end of capacitor C 1 than the 2nd pin of its U10A, and the 1st pin links to each other with an end of the 3rd pin and resistance R 8, the other end ground connection of capacitor C 1; The other end of resistance R 8 links to each other with an end of capacitor C 5 and an end of resistance R 9; The 2nd pin of voltage comparator U11A links to each other with an end of the other end of resistance R 9 and capacitor C 2, and the 1st pin links to each other the other end ground connection of capacitor C 2 with the other end of the 3rd pin, capacitor C 5 and an end of resistance R 10; The other end of resistance R 10 links to each other with an end of capacitor C 6 and an end of resistance R 11; The 2nd pin of voltage comparator U12A links to each other with an end of the other end of resistance R 11 and capacitor C 3, and the 1st pin links to each other with the other end of the 3rd pin, capacitor C 6 and an end of resistance R 12, capacitor C 3 other end ground connection; The other end of resistance R 12 is connected with an end of capacitor C 7 and an end of resistance R 13; The 2nd pin of voltage comparator U13A links to each other with an end of the other end of resistance R 13 and capacitor C 4, and the 1st pin links to each other the other end ground connection of capacitor C 4 with the other end of the 3rd pin, capacitor C 7 and the 2nd pin of voltage comparator U14A; The 3rd pin of voltage comparator U14A links to each other with an end of an end of resistance R 14 and resistance R 15; The 1st pin links to each other with the other end of resistance R 15, and the output signal, the other end ground connection of resistance R 14.
Described power circuit comprises linear unit U4, linear unit U5, linear unit U6, triode Q1, triode Q2, triode Q3, diode D1, diode D2, diode D3, diode D4, capacitor C 8, capacitor C 9, capacitor C 10, capacitor C 11, capacitor C 12, capacitor C 13, capacitor C 14, capacitor C 15, capacitor C 16, capacitor C 17, capacitor C 18, button S1, resistance R 16, resistance R 17, resistance R 18, resistance R 19, resistance R 20, resistance R 21, inductance L 1 and power supply BATT, wherein said power supply BATT minus earth, and positive pole is connected with diode D1 is anodal; Diode D1 negative pole links to each other with an end of resistance R 17 and the emitter of triode Q1, and the other end of resistance R 17 links to each other with the positive pole of diode D2, an end of resistance R 18 and the collector of triode Q2, and the negative pole of diode D2 is connected with the negative pole of diode D3 and the end of button S1; The other end ground connection of button S1, the positive pole of diode D3 connects an end of resistance R 16, and links to each other with the switching signal end; Another termination power VCC1 of resistance R 16, the base stage of triode Q1 is connected with the other end of resistance R 18, the grounded emitter of triode Q2; Base stage links to each other with an end of resistance R 19 and the collector of triode Q3, and an end of the other end of resistance R 19 and resistance R 20 joins, and connects power supply VCC1; The grounded emitter of triode Q3, base stage connects an end of resistance R 21, and the other end of resistance R 21 connects the other end of resistance R 20; And link to each other with power input, the collector of triode Q1 links to each other with the positive pole of capacitor C 8 and the 7th pin of linear unit U4, and connection+9V power supply; The minus earth of capacitor C 8, the 6th pin ground connection of linear unit U4, the 1st pin connects an end of capacitor C 18; The 4th pin links to each other with the 1st pin of capacitor C 9 and linear unit U5, and the 8th pin links to each other the minus earth of capacitor C 9 with the other end of capacitor C 8, the negative pole of diode D4 and an end of inductance L 1; The plus earth of diode D4, the other end of inductance L 1 connects the positive pole of capacitor C 10, and power supply VCC is provided; The minus earth of capacitor C 10; The 2nd pin of linear unit U5 connects an end of capacitor C 12, and the 4th pin connects the other end of capacitor C 12, the 3rd pin ground connection; The end that the 5th pin connects capacitor C 13 connects; And out-put supply VEE, the end that the 8th pin connects capacitor C 11 connects, the equal ground connection of other end ground connection of capacitor C 11 and C13; The 1st pin of linear unit U6 links to each other with the positive pole of an end of capacitor C 14 and capacitor C 15; And meet power supply VCC, and the 2nd pin ground connection, the 3rd pin is connected with the positive pole of capacitor C 16 and an end of capacitor C 17; And out-put supply VCC1, the equal ground connection of the other end of the negative pole of the other end of capacitor C 14, the negative pole of C15, C16 and C17.The described CPU of step (2) comprises a dsp chip and a fpga chip; The A15-A0 pin of wherein said dsp chip and the A15-A0 pin of fpga chip join through the BUS bus; Dsp chip /IS pin and fpga chip /the EN pin joins; Dsp chip /STRB pin and fpga chip /the STRB pin joins, and the R/W pin of dsp chip and the R/W pin of fpga chip join, and the READY pin of dsp chip and the READY pin of fpga chip join; Dsp chip /MSC pin and fpga chip /the MSC pin joins; Dsp chip /the BUSY pin of INTn pin and high-speed ADC chip joins, and the D0-D15 pin of dsp chip and the D0-D15 pin of high-speed ADC chip join through the BUS bus, fpga chip /CS pin and high-speed ADC chip /the CS pin joins; The A0 pin of fpga chip and the A0 pin of high-speed ADC chip join, fpga chip /READ pin and high-speed ADC chip /the READ pin joins.
The TMS320C25 chip that described dsp chip adopts TI company to produce, this chip is high performance monolithic signal processor; Described fpga chip adopts panasonic semiconductor CLAy31 chip; The multiplication speed of this each multiplier of chip is with MHz; And the percentage of implementing the required FPGA of multiplier is recently arranged; Cooperate dsp chip to use,, thereby improved the work efficiency of multimeter the arithmetic capability that improves multimeter of the present invention greatly.
This electronic measuring device can be connected with PC through the usb communication module, operation virtual digit multimeter software on PC; USB control is desired the multi-path digital amount output unit generation measurement conversion and the range of data acquisition module and is changed needed control signal; After multi-analog is changed through A/D converter; Be transferred to PC through usb bus,, on PC, show measured data through the data processing of PC software.
Multimeter major function measurement range of the present invention: alternating voltage is 0V ~ 1000V, and frequency response is 45Hz ~ 1000Hz, measuring accuracy is ± (2%+3); DC voltage is 0 ~ 1000V, measuring accuracy is ± (2%+3); Alternating current is 0 ~ 1A, and frequency response is 45Hz ~ 1000Hz, measuring accuracy is ± (2%+5); DC current is 0 ~ 1A, measuring accuracy is ± (2%+3); Resistance is 0 ~ 40M Ω, measuring accuracy is ± (1%+3); Electric capacity is 0 ~ 1000 μ F, measuring accuracy is ± (3%+5); Frequency is 0.01Hz ~ 1MHz, measuring accuracy is ± (0.1%+3); Temperature is-40 ℃ ~ 1000 ℃, measuring accuracy is ± (3%+5).
Frequency analysis functional measurement scope of the present invention: frequency analysis voltage range: 30V ~ 600V; Frequency analysis range of current: 5A ~ 100A; Frequency analysis frequency response (fundamental frequency): 50Hz~60Hz; Measuring accuracy: 1 subharmonic: ± (3%+10); 2 ~ 6 subharmonic: ± (3.5%+10); 7 ~ 8 subharmonic: ± (4.5%+10); 9 ~ 10 subharmonic: ± (5%+10); 11 ~ 15 subharmonic: ± (7%+10); 16 ~ 21 subharmonic: ± (10%+10).
Advantage of the present invention is: integrate multimeter harmonic analyser, make that test is convenient, quick, in conjunction with additional function of the present invention; Feasible use is intelligent more; And improved measuring accuracy and measuring speed greatly, easy to carry, also practiced thrift purchase cost simultaneously.
But the above is merely preferable possible embodiments of the present invention, is not in order to limit to claim of the present invention, so the equivalent structure that all utilizations instructions of the present invention and accompanying drawing content are done changes, all to be included in protection scope of the present invention.
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