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CN102752038B - Satellite responder - Google Patents

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CN102752038B
CN102752038B CN201210222833.3A CN201210222833A CN102752038B CN 102752038 B CN102752038 B CN 102752038B CN 201210222833 A CN201210222833 A CN 201210222833A CN 102752038 B CN102752038 B CN 102752038B
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phase
clock
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CN102752038A (en
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吉欣
张谨
翟盛华
朱舸
任经纬
张廷新
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China Academy of Space Technology CAST
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Abstract

本发明涉及一种卫星应答机,属于卫星测量控制技术领域。包括接收通道部分、数字处理部分、发射通道部分和频率综合器;接收通道部分包括下混频器A、滤波器和下混频器B;数字处理部分包括模拟数字变换器A/D、数字频率合成器DDS1、数字频率合成器DDS2和FPGA;发射通道部分包括调制器;频率综合器包括倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D、移频锁相A、移频锁相B、时钟源选择器和上混频器。本发明数字技术实现相干转发功能和非相干转发功能;提高了发射机频谱纯度和稳定性;可以直接切换到外部高稳时钟源,无需经过频率转换,不产生相噪损失,射频相噪特性更好;成本低。

The invention relates to a satellite transponder and belongs to the technical field of satellite measurement and control. Including receiving channel part, digital processing part, transmitting channel part and frequency synthesizer; receiving channel part includes down-mixer A, filter and down-mixer B; digital processing part includes analog-to-digital converter A/D, digital frequency Synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; transmit channel part includes modulator; frequency synthesizer includes frequency multiplication phase lock A, frequency multiplication phase lock B, frequency multiplication phase lock C, frequency multiplication phase lock D, frequency shift lock Phase A, Frequency Shift Lock B, Clock Source Selector and Up Mixer. The digital technology of the present invention realizes coherent forwarding function and non-coherent forwarding function; improves the spectrum purity and stability of the transmitter; can directly switch to an external high-stable clock source without frequency conversion, does not generate phase noise loss, and has better radio frequency phase noise characteristics Good; low cost.

Description

一种卫星应答机A satellite transponder

技术领域 technical field

本发明涉及一种卫星应答机,属于卫星测量控制技术领域。The invention relates to a satellite transponder and belongs to the technical field of satellite measurement and control.

背景技术 Background technique

我国目前已经开展研制更新的探测器,用于对更遥远的天体进行探测,包括金星、火星、木星等。月球到地球的最远距离约40万公里,而火星到地球的最远距离约4亿公里,距离拓展了1000倍。如此遥远的距离,对星上应答机的灵敏度提出了更高的要求。根据预算,星上应答机的灵敏度需要优于-150dBm。而目前已经飞行的月球卫星CE-1/2上应答机的接收灵敏度只达到了-125dBm。At present, our country has developed newer detectors to detect more distant celestial bodies, including Venus, Mars, and Jupiter. The farthest distance from the moon to the earth is about 400,000 kilometers, while the furthest distance from Mars to the earth is about 400 million kilometers, which is a 1,000-fold increase in distance. Such a long distance puts forward higher requirements on the sensitivity of the on-board transponder. According to the budget, the sensitivity of the on-board transponder needs to be better than -150dBm. However, the receiving sensitivity of the transponder on the lunar satellite CE-1/2 already in flight has only reached -125dBm.

发明内容 Contents of the invention

本发明的目的是为了克服现有技术的不足,提出一种卫星应答机。The purpose of the invention is to propose a satellite transponder in order to overcome the deficiencies in the prior art.

本发明的目的是通过以下技术方案实现的。The purpose of the present invention is achieved through the following technical solutions.

本发明的一种卫星应答机,包括接收通道部分、数字处理部分、发射通道部分和频率综合器;A satellite transponder of the present invention includes a receiving channel part, a digital processing part, a transmitting channel part and a frequency synthesizer;

接收通道部分包括下混频器A、滤波器和下混频器B;上行射频信号和从频率综合器中倍频锁相A发出的本振信号1经过下混频器A的混合形成低频信号,低频信号经过滤波器过滤,经过滤波器过滤的信号和从频率综合器中移频锁相A发出的本振信号2经过下混频器B的混合,形成中频信号输入给数字处理部分;The receiving channel part includes a down-mixer A, a filter and a down-mixer B; the uplink radio frequency signal and the local oscillator signal 1 sent from the frequency multiplication phase-locked A in the frequency synthesizer are mixed by the down-mixer A to form a low-frequency signal , the low-frequency signal is filtered by the filter, and the signal filtered by the filter and the local oscillator signal 2 sent from the frequency-shift phase-locked A in the frequency synthesizer are mixed by the down-mixer B to form an intermediate frequency signal and input to the digital processing part;

数字处理部分包括模拟数字变换器A/D、数字频率合成器DDS1、数字频率合成器DDS2和FPGA;模拟数字变换器A/D接收从接收通道部分传递过来的中频信号,对信号进行A/D采样,将中频信号变成数字信号,然后将数字信号输送给FPGA,FPGA对接收到的数字信号进行多普勒跟踪锁定和解调,提取多普勒成分,控制数字频率合成器DDS1和DDS2,分别生成多普勒参考信号1和多普勒参考信号2并分别输送给移频锁相A和移频锁相B;多普勒参考信号1与上行射频信号中的多普勒频率成分相干,完成相干载波捕获与跟踪;FPGA通过数字计算产生多普勒参考信号2;当多普勒参考信号2的频率成分与多普勒参考信号1相干时,并且满足预定的比例k,实现系统要求的收发相干功能;当多普勒参考信号2与多普勒参考信号1不相干时,实现系统要求的收发非相干功能;The digital processing part includes analog-to-digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; the analog-to-digital converter A/D receives the intermediate frequency signal transmitted from the receiving channel part, and performs A/D on the signal Sampling, converting the intermediate frequency signal into a digital signal, and then sending the digital signal to the FPGA, FPGA performs Doppler tracking locking and demodulation on the received digital signal, extracts the Doppler component, and controls the digital frequency synthesizer DDS1 and DDS2, Generate Doppler reference signal 1 and Doppler reference signal 2 respectively and send them to frequency shift lock A and frequency shift lock B respectively; Doppler reference signal 1 is coherent with the Doppler frequency component in the uplink radio frequency signal, Complete coherent carrier acquisition and tracking; FPGA generates Doppler reference signal 2 through digital calculation; when the frequency component of Doppler reference signal 2 is coherent with Doppler reference signal 1 and meets the predetermined ratio k, the system requirements are realized Transmit and receive coherent function; when Doppler reference signal 2 and Doppler reference signal 1 are incoherent, realize the non-coherent function of transmitting and receiving required by the system;

发射通道部分包括调制器;调制器接收从频率综合器发送出的本振信号3,对本振信号3用基带数据进行调制,输出下行射频信号;本振信号3是倍频锁相B发出的高频时钟信号和移频锁相B发出的下行多普勒参考信号经过上混频器进行混频后形成的射频信号;The transmit channel part includes a modulator; the modulator receives the local oscillator signal 3 sent from the frequency synthesizer, modulates the local oscillator signal 3 with baseband data, and outputs a downlink radio frequency signal; the local oscillator signal 3 is the high The frequency clock signal and the downlink Doppler reference signal sent by the frequency shift phase lock B are mixed by the up-mixer to form a radio frequency signal;

频率综合器包括倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D、移频锁相A、移频锁相B、时钟源选择器和上混频器;时钟源选择器选择内部温补晶振TCXO时钟和外部超高稳时钟中的一个,将选择到的时钟作为频率综合器的时钟基准;倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D分别将时钟基准倍频形成高频时钟信号;倍频锁相C将形成的高频时钟信号发送给移频锁相A,移频锁相A将接收到的高频时钟信号和多普勒参考信号1进行移频,形成本振信号2;倍频锁相D将形成的高频时钟信号发送给移频锁相B,移频锁相B将接收到的高频时钟信号和多普勒参考信号2进行移频,形成下行多普勒参考信号。The frequency synthesizer includes frequency multiplication phase lock A, frequency multiplication phase lock B, frequency multiplication phase lock C, frequency multiplication phase lock D, frequency shift phase lock A, frequency shift phase lock B, clock source selector and up-mixer; The clock source selector selects one of the internal temperature-compensated crystal oscillator TCXO clock and the external ultra-high stability clock, and uses the selected clock as the clock reference of the frequency synthesizer; frequency multiplication phase-locking A, frequency multiplication phase-locking B, frequency multiplication phase-locking C. Frequency multiplication and phase locking D respectively multiply the frequency of the clock reference to form a high frequency clock signal; Clock signal and Doppler reference signal 1 are frequency shifted to form local oscillator signal 2; frequency multiplication phase lock D sends the formed high frequency clock signal to frequency shift lock B, frequency shift lock B receives high frequency The clock signal and the Doppler reference signal 2 are frequency-shifted to form a downlink Doppler reference signal.

有益效果Beneficial effect

本发明数字技术实现相干转发功能和非相干转发功能,具有“软件切换”的特性,增强了灵活性;利用数字频率综合技术,产生所需要的工作频点,可以根据任务需求实现不同的射频频点,拓展了功能;提高了发射机频谱纯度和稳定性;可以直接切换到外部高稳时钟源,无需经过频率转换,不产生相噪损失,射频相噪特性更好;成本低。The digital technology of the present invention realizes the coherent forwarding function and the non-coherent forwarding function, has the characteristic of "software switching", and enhances the flexibility; uses the digital frequency synthesis technology to generate the required working frequency points, and can realize different radio frequency frequencies according to the task requirements. The function is expanded; the spectrum purity and stability of the transmitter are improved; it can be directly switched to an external high-stable clock source without frequency conversion, no phase noise loss, and better RF phase noise characteristics; low cost.

附图说明 Description of drawings

图1为本发明的卫星应答机的组成示意图;Fig. 1 is the composition schematic diagram of satellite transponder of the present invention;

图2为倍频锁相A的组成示意图;Fig. 2 is the composition schematic diagram of multiplication phase lock A;

图3为倍频锁相C的组成示意图;Fig. 3 is the composition schematic diagram of frequency multiplication phase-locked C;

图4为移频锁相A的组成示意图;FIG. 4 is a schematic diagram of the composition of frequency-shifted phase-locked A;

图5为倍频锁相B的组成示意图;Fig. 5 is the composition schematic diagram of frequency multiplication phase lock B;

图6为倍频锁相D的组成示意图;Fig. 6 is the composition schematic diagram of frequency multiplication phase-locking D;

图7为移频锁相B的组成示意图。FIG. 7 is a schematic diagram of the composition of the frequency-shift phase-lock B.

具体实施方式 Detailed ways

下面结合附图和实施例对本发明作进一步说明。The present invention will be further described below in conjunction with drawings and embodiments.

实施例Example

以X频段收发应答机为例,系统要求的转发比K=下行射频信号的频率/上行射频信号的频率=880/749;设计上行射频信号的频率为7115.5MHz,则要求下行射频信号的频率为8360MHz,其中8360/7115.5=K。在相干模式下,如果应答机接收到的上行射频信号的频率存在一定的多普勒频偏fd=74.9KHz,则上行射频信号的频率变为7115.5MHz+fd=7115.5749MHz,那么应答机发射的下行射频信号的频率应当随之变为8360.088MHz,始终保持下行射频信号的频率/上行射频信号的频率=K。而在非相干模式下,应答机发射的下行频率应当始终保持为8360MHz。Taking the X-band transponder as an example, the forwarding ratio K=the frequency of the downlink radio frequency signal/the frequency of the uplink radio frequency signal=880/749 required by the system; the frequency of the uplink radio frequency signal is designed to be 7115.5MHz, and the frequency of the downlink radio frequency signal is required to be 8360MHz, where 8360/7115.5=K. In coherent mode, if there is a certain Doppler frequency offset fd=74.9KHz in the frequency of the uplink radio frequency signal received by the transponder, the frequency of the uplink radio frequency signal becomes 7115.5MHz+fd=7115.5749MHz, then the transponder transmits The frequency of the downlink radio frequency signal should then be changed to 8360.088MHz, and the frequency of the downlink radio frequency signal/the frequency of the uplink radio frequency signal=K. In the non-coherent mode, the downlink frequency transmitted by the transponder should always be 8360MHz.

卫星应答机,如图1所示,包括接收通道部分、数字处理部分、发射通道部分和频率综合器;The satellite transponder, as shown in Figure 1, includes a receiving channel part, a digital processing part, a transmitting channel part and a frequency synthesizer;

内部时钟源设计TCXO频率设计为100MHz,外部超高稳时钟源频率为10MHz。当参考时钟选择器选择TCXO作为时钟基准时,得到以下设计参数。The internal clock source design TCXO frequency is designed to be 100MHz, and the external ultra-high stability clock source frequency is 10MHz. When the reference clock selector selects TCXO as the clock reference, the following design parameters are obtained.

倍频锁相A输出的本振信号1的频率设计为7000MHz,倍频锁相A的组成示意图如图2所示;倍频锁相A的工作过程为:倍频锁相A的输入时钟来自频率源选择器,频率为100MHz;输入时钟经过软件控制的10分频器,频率降到10MHz;压控振荡器(VCO)的初始输出信号频率在7000MHz,经过700分频器,频率降到10MHz;这两路10MHz信号进入鉴相器(PD),生成鉴相误差信号,经过环路滤波器(Loop Filter)进行低通滤波,滤波后的误差信号用于调节VCO的输出频率;经过这个倍频锁相A电路,使得VCO的输出频率与100MHz时钟保持锁定,即得到7000MHz的本振信号1;The frequency of the local oscillator signal 1 output by frequency multiplication phase lock A is designed to be 7000MHz. The schematic diagram of the composition of frequency multiplication phase lock A is shown in Figure 2; the working process of frequency multiplication phase lock A is: Frequency source selector, the frequency is 100MHz; the input clock passes through the software-controlled 10 frequency divider, and the frequency is reduced to 10MHz; the initial output signal frequency of the voltage-controlled oscillator (VCO) is 7000MHz, and the frequency is reduced to 10MHz through the 700 frequency divider ; These two 10MHz signals enter the phase detector (PD) to generate a phase detector error signal, which is low-pass filtered through the loop filter (Loop Filter), and the filtered error signal is used to adjust the output frequency of the VCO; The frequency phase lock A circuit keeps the output frequency of the VCO locked with the 100MHz clock, that is, the local oscillator signal 1 of 7000MHz is obtained;

倍频锁相C的组成示意图如图3所示;输出时钟频率为90MHz,其工作过程同倍频锁相A。The schematic diagram of the composition of frequency multiplication phase lock C is shown in Figure 3; the output clock frequency is 90MHz, and its working process is the same as that of frequency multiplication phase lock A.

移频锁相A的组成示意图如图4所示;移频锁相A的工作过程为:来自倍频锁相C的频率为90MHz,来自DDS1的频率为10M+fd;VCO的初始输出频率在100MHz,与来自倍频锁相C的90MHz时钟进行下混频后,形成10MHz的低频信号。该低频信号与来自于DDS1的10M+fd信号进入鉴相器(PD),鉴相生成的误差信号经过环路滤波器(Loop Filter)进行低通滤波,滤波后的误差信号用于调节VCO的输出频率。经过移频锁相A电路,使得VCO的输出频率等于倍频锁相C与DDS1的输出频率之和,即得到本振信号2的频率=DDS1的频率+倍频锁相C的频率=100M+fd;The schematic diagram of the composition of frequency shift lock A is shown in Figure 4; the working process of frequency shift lock A is: the frequency from multiplier phase lock C is 90MHz, and the frequency from DDS1 is 10M+fd; the initial output frequency of VCO is at 100MHz, after down-mixing with the 90MHz clock from the multiplier phase-locked C, a 10MHz low-frequency signal is formed. The low-frequency signal and the 10M+fd signal from DDS1 enter the phase detector (PD), and the error signal generated by the phase detector is low-pass filtered by the loop filter (Loop Filter), and the filtered error signal is used to adjust the VCO. Output frequency. After the frequency-shifted phase-locked A circuit, the output frequency of the VCO is equal to the sum of the output frequencies of the multiplied phase-locked C and DDS1, that is, the frequency of the local oscillator signal 2 = the frequency of DDS1 + the frequency of the multiplied phase-locked C = 100M+ fd;

接收通道部分包括下混频器A、滤波器和下混频器B;上行射频信号和从频率综合器中倍频锁相A发出的本振信号1经过下混频器A的混合形成低频信号,低频信号经过滤波器过滤,经过滤波器过滤的信号和从频率综合器中移频锁相A发出的本振信号2经过下混频器B的混合,形成中频信号输入给数字处理部分;The receiving channel part includes a down-mixer A, a filter and a down-mixer B; the uplink radio frequency signal and the local oscillator signal 1 sent from the frequency multiplication phase-locked A in the frequency synthesizer are mixed by the down-mixer A to form a low-frequency signal , the low-frequency signal is filtered by the filter, and the signal filtered by the filter and the local oscillator signal 2 sent from the frequency-shift phase-locked A in the frequency synthesizer are mixed by the down-mixer B to form an intermediate frequency signal and input to the digital processing part;

数字处理部分包括模拟数字变换器A/D、数字频率合成器DDS1、数字频率合成器DDS2和FPGA;模拟数字变换器A/D接收从接收通道部分传递过来的中频信号,对信号进行A/D采样,将中频信号变成数字信号,然后将数字信号输送给FPGA,FPGA对接收到的数字信号进行多普勒跟踪锁定和解调,提取多普勒成分,控制数字频率合成器DDS1和DDS2,分别生成多普勒参考信号1和多普勒参考信号2并分别输送给移频锁相A和移频锁相B;多普勒参考信号1与已接收到的上行射频信号中的多普勒频率成分相干,完成相干载波捕获与跟踪;FPGA通过数字计算产生多普勒参考信号2;The digital processing part includes analog-to-digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; the analog-to-digital converter A/D receives the intermediate frequency signal transmitted from the receiving channel part, and performs A/D on the signal Sampling, converting the intermediate frequency signal into a digital signal, and then sending the digital signal to the FPGA, FPGA performs Doppler tracking locking and demodulation on the received digital signal, extracts the Doppler component, and controls the digital frequency synthesizer DDS1 and DDS2, Generate Doppler reference signal 1 and Doppler reference signal 2 respectively and send them to frequency shift lock A and frequency shift lock B respectively; Doppler reference signal 1 and Doppler reference signal in the received uplink radio frequency signal Frequency components are coherent to complete coherent carrier capture and tracking; FPGA generates Doppler reference signal 2 through digital calculation;

多普勒参考信号1的频率为10MHz+fd。其中fd=74.9KHz,则多普勒参考信号1的实际频率为10.0749MHz。The frequency of the Doppler reference signal 1 is 10MHz+fd. Where fd=74.9KHz, the actual frequency of the Doppler reference signal 1 is 10.0749MHz.

在相干模式下,多普勒参考信号2的频率为10MHz+fd*K,其中K=880/749,则多普勒参考信号2的实际频率为10.088MHz。而在非相干模式下,多普勒参考信号2的输出频率固定为10MHz。In the coherent mode, the frequency of the Doppler reference signal 2 is 10 MHz+fd*K, where K=880/749, so the actual frequency of the Doppler reference signal 2 is 10.088 MHz. In the non-coherent mode, the output frequency of the Doppler reference signal 2 is fixed at 10 MHz.

发射通道部分包括调制器;调制器接收从频率综合器发送出的本振信号3,对本振信号3用基带数据进行调制,输出下行射频信号;本振信号3是倍频锁相B发出的高频时钟信号和移频锁相B发出的下行多普勒参考信号经过上混频器进行混频后形成的射频信号;The transmit channel part includes a modulator; the modulator receives the local oscillator signal 3 sent from the frequency synthesizer, modulates the local oscillator signal 3 with baseband data, and outputs a downlink radio frequency signal; the local oscillator signal 3 is the high The frequency clock signal and the downlink Doppler reference signal sent by the frequency shift phase lock B are mixed by the up-mixer to form a radio frequency signal;

频率综合器包括倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D、移频锁相A、移频锁相B、时钟源选择器和上混频器;时钟源选择器选择内部温补晶振TCXO时钟和外部超高稳时钟中的一个,将选择到的时钟作为频率综合器的时钟基准;倍频信号将时钟基准倍频形成高频时钟信号;倍频锁相C将形成的高频时钟信号发送给移频锁相A,移频锁相A将接收到的高频时钟信号和多普勒参考信号1进行移频,形成本振信号2;倍频锁相D将形成的高频时钟信号发送给移频锁相B,移频锁相B将接收到的高频时钟信号和多普勒参考信号2进行移频,形成下行多普勒参考信号;The frequency synthesizer includes frequency multiplication phase lock A, frequency multiplication phase lock B, frequency multiplication phase lock C, frequency multiplication phase lock D, frequency shift phase lock A, frequency shift phase lock B, clock source selector and up-mixer; The clock source selector selects one of the internal temperature-compensated crystal oscillator TCXO clock and the external ultra-high stability clock, and uses the selected clock as the clock reference of the frequency synthesizer; the frequency multiplication signal doubles the frequency of the clock reference to form a high-frequency clock signal; the frequency multiplication Phase lock C sends the formed high-frequency clock signal to frequency-shift phase-lock A, and frequency-shift phase-lock A shifts the frequency of the received high-frequency clock signal and Doppler reference signal 1 to form local oscillator signal 2; frequency multiplication Phase-lock D sends the formed high-frequency clock signal to frequency-shift phase-lock B, and frequency-shift phase-lock B shifts the frequency of the received high-frequency clock signal and Doppler reference signal 2 to form a downlink Doppler reference signal;

倍频锁相B的输出高倍时钟频率设计为8000MHz,倍频锁相B的组成示意图如图5所示;其工作过程同倍频锁相A;The output multiplier clock frequency of frequency multiplication phase lock B is designed to be 8000MHz, and the composition diagram of frequency multiplication phase lock B is shown in Figure 5; its working process is the same as frequency multiplication phase lock A;

倍频锁相D的输出高倍时钟频率设计为350MHz,倍频锁相D的组成示意图如图6所示;其工作过程同倍频锁相A;The output multiplier clock frequency of frequency multiplication phase lock D is designed to be 350MHz, and the composition diagram of frequency multiplication phase lock D is shown in Figure 6; its working process is the same as frequency multiplication phase lock A;

移频锁相B的输入频率为来自倍频锁相D的350MHz和来自DDS2的多普勒参考信号2,移频锁相B的组成示意图如图7所示;其工作过程同移频锁相A;The input frequency of frequency shift lock B is 350MHz from frequency multiplier phase lock D and Doppler reference signal 2 from DDS2. The composition diagram of frequency shift lock B is shown in Figure 7; its working process is the same as frequency shift lock A;

而本振信号3的频率为8000MHz与360MHz+fd*K的混频结果,因此本振3的频率为8360MHz+fd*K。在相干模式下,如果fd=74.9KHz,则本振信号3的频率为8360.088MHz。在非相干模式下,由于DDS2输出的频率固定为10MHz,因此本振信号3的频率为8360MHz。The frequency of the local oscillator signal 3 is the mixing result of 8000MHz and 360MHz+fd*K, so the frequency of the local oscillator 3 is 8360MHz+fd*K. In the coherent mode, if fd=74.9KHz, the frequency of the local oscillator signal 3 is 8360.088MHz. In the non-coherent mode, since the output frequency of the DDS2 is fixed at 10MHz, the frequency of the local oscillator signal 3 is 8360MHz.

当频率综合器选择100MHz的TCXO作为时钟基准时,倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D,的工作参数。根据需要,通过软件控制,星上应答机可以随时将时钟源切换到外部10MHz源,同时各个倍频锁相通过软件指令,将其内部的10分频器改为直通(不分频)。这样各个倍频锁相的输出频率不变,但整体频率都与输入的外部10MHz高稳源保持锁相同步。When the frequency synthesizer selects 100MHz TCXO as the clock reference, the working parameters of frequency multiplication phase lock A, frequency multiplication phase lock B, frequency multiplication phase lock C, and frequency multiplication phase lock D. According to needs, through software control, the on-board transponder can switch the clock source to an external 10MHz source at any time, and at the same time, each frequency multiplier is phase-locked to change its internal 10-frequency divider to a straight-through (no frequency division) through software instructions. In this way, the output frequency of each frequency multiplier phase-locked is unchanged, but the overall frequency is kept phase-locked and synchronized with the input external 10MHz high-stable source.

Claims (3)

1.一种卫星应答机,其特征在于:包括接收通道部分、数字处理部分、发射通道部分和频率综合器;1. A satellite transponder, characterized in that: comprising a receiving channel part, a digital processing part, a transmitting channel part and a frequency synthesizer; 接收通道部分包括下混频器A、滤波器和下混频器B;上行射频信号和从频率综合器中倍频锁相A发出的本振信号1经过下混频器A的混合形成低频信号,低频信号经过滤波器过滤,经过滤波器过滤的信号和从频率综合器中移频锁相A发出的本振信号2经过下混频器B的混合,形成中频信号输入给数字处理部分;The receiving channel part includes a down-mixer A, a filter and a down-mixer B; the uplink radio frequency signal and the local oscillator signal 1 sent from the frequency multiplication phase-locked A in the frequency synthesizer are mixed by the down-mixer A to form a low-frequency signal , the low-frequency signal is filtered by the filter, and the signal filtered by the filter and the local oscillator signal 2 sent from the frequency-shift phase-locked A in the frequency synthesizer are mixed by the down-mixer B to form an intermediate frequency signal and input to the digital processing part; 数字处理部分包括模拟数字变换器A/D、数字频率合成器DDS1、数字频率合成器DDS2和FPGA;模拟数字变换器A/D接收从接收通道部分传递过来的中频信号,对信号进行A/D采样,将中频信号变成数字信号,然后将数字信号输送给FPGA,FPGA对接收到的数字信号进行多普勒跟踪锁定和解调,提取多普勒成分,控制数字频率合成器DDS1和DDS2,分别生成多普勒参考信号1和多普勒参考信号2并分别输送给移频锁相A和移频锁相B;多普勒参考信号1与上行射频信号中的多普勒频率成分相干,完成相干载波捕获与跟踪;FPGA通过数字计算产生多普勒参考信号2;当多普勒参考信号2的频率成分与多普勒参考信号1相干时,并且满足预定的比例k,实现系统要求的收发相干功能;当多普勒参考信号2与多普勒参考信号1不相干时,实现系统要求的收发非相干功能;The digital processing part includes analog-to-digital converter A/D, digital frequency synthesizer DDS1, digital frequency synthesizer DDS2 and FPGA; the analog-to-digital converter A/D receives the intermediate frequency signal transmitted from the receiving channel part, and performs A/D on the signal Sampling, converting the intermediate frequency signal into a digital signal, and then sending the digital signal to the FPGA, FPGA performs Doppler tracking locking and demodulation on the received digital signal, extracts the Doppler component, and controls the digital frequency synthesizer DDS1 and DDS2, Generate Doppler reference signal 1 and Doppler reference signal 2 respectively and send them to frequency shift lock A and frequency shift lock B respectively; Doppler reference signal 1 is coherent with the Doppler frequency component in the uplink radio frequency signal, Complete coherent carrier acquisition and tracking; FPGA generates Doppler reference signal 2 through digital calculation; when the frequency component of Doppler reference signal 2 is coherent with Doppler reference signal 1 and meets the predetermined ratio k, the system requirements are realized Transmit and receive coherent function; when Doppler reference signal 2 and Doppler reference signal 1 are incoherent, realize the non-coherent function of transmitting and receiving required by the system; 在相干模式下,如果应答机接收到的上行射频信号的频率存在一定的多普勒频偏fd,则上行射频信号的频率增加fd,那么应答机发射的下行射频信号的频率增加k×fd,始终保持下行射频信号的频率/上行射频信号的频率=k;而在非相干模式下,应答机发射的下行频率始终保持不变;In the coherent mode, if the frequency of the uplink RF signal received by the transponder has a certain Doppler frequency offset fd, the frequency of the uplink RF signal increases by fd, and the frequency of the downlink RF signal transmitted by the transponder increases by k×fd, Always keep the frequency of the downlink radio frequency signal/frequency of the uplink radio frequency signal=k; and in the non-coherent mode, the downlink frequency transmitted by the transponder remains unchanged; 发射通道部分包括调制器;调制器接收从频率综合器发送出的本振信号3,对本振信号3用基带数据进行调制,输出下行射频信号;本振信号3是倍频锁相B发出的高频时钟信号和移频锁相B发出的下行多普勒参考信号经过上混频器进行混频后形成的射频信号;The transmit channel part includes a modulator; the modulator receives the local oscillator signal 3 sent from the frequency synthesizer, modulates the local oscillator signal 3 with baseband data, and outputs a downlink radio frequency signal; the local oscillator signal 3 is the high The frequency clock signal and the downlink Doppler reference signal sent by the frequency shift phase lock B are mixed by the up-mixer to form a radio frequency signal; 频率综合器包括倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D、移频锁相A、移频锁相B、时钟源选择器和上混频器;时钟源选择器选择内部温补晶振TCXO时钟和外部超高稳时钟中的一个,将选择到的时钟作为频率综合器的时钟基准;倍频锁相A、倍频锁相B、倍频锁相C、倍频锁相D分别将时钟基准倍频形成高频时钟信号;倍频锁相C将形成的高频时钟信号发送给移频锁相A,移频锁相A将接收到的高频时钟信号和多普勒参考信号1进行移频,形成本振信号2;倍频锁相D将形成的高频时钟信号发送给移频锁相B,移频锁相B将接收到的高频时钟信号和多普勒参考信号2进行移频,形成下行多普勒参考信号。The frequency synthesizer includes frequency multiplication phase lock A, frequency multiplication phase lock B, frequency multiplication phase lock C, frequency multiplication phase lock D, frequency shift phase lock A, frequency shift phase lock B, clock source selector and up-mixer; The clock source selector selects one of the internal temperature-compensated crystal oscillator TCXO clock and the external ultra-high stability clock, and uses the selected clock as the clock reference of the frequency synthesizer; frequency multiplication phase-locking A, frequency multiplication phase-locking B, frequency multiplication phase-locking C. Frequency multiplication and phase locking D respectively multiply the frequency of the clock reference to form a high frequency clock signal; Clock signal and Doppler reference signal 1 are frequency shifted to form local oscillator signal 2; frequency multiplication phase lock D sends the formed high frequency clock signal to frequency shift lock B, frequency shift lock B receives high frequency The clock signal and the Doppler reference signal 2 are frequency-shifted to form a downlink Doppler reference signal. 2.根据权利要求1所述的一种卫星应答机,其特征在于:倍频锁相A包括分频器A、分频器B、鉴相器、压控振荡器和环路滤波器;倍频锁相A的输入时钟经过分频器A后得到频率为A的信号;压控振荡器的初始输出信号经过分频器B后得到频率为B的信号,频率为A的信号和频率为B的信号经过鉴相器后生成鉴相误差信号,该误差信号经过环路滤波器进行低通滤波,滤波后的误差信号用于调节压控振荡器的输出频率,该输出频率与输入时钟保持锁定,得到本振信号1。2. A kind of satellite transponder according to claim 1, characterized in that: multiplier phase-locked A comprises frequency divider A, frequency divider B, phase detector, voltage controlled oscillator and loop filter; The input clock of frequency-locked phase A passes through frequency divider A to obtain a signal with frequency A; the initial output signal of the voltage-controlled oscillator passes through frequency divider B to obtain a signal with frequency B, and the signal with frequency A and frequency B After the signal passes through the phase detector, the phase detection error signal is generated. The error signal is low-pass filtered by the loop filter. The filtered error signal is used to adjust the output frequency of the voltage-controlled oscillator. The output frequency is locked with the input clock , get local oscillator signal 1. 3.根据权利要求1所述的一种卫星应答机,其特征在于:移频锁相A包括鉴相器、环路滤波器、压控振荡器和下混频器;压控振荡器的初始输出频率与来自倍频锁相C的时钟进行下混频后形成低频信号;该低频信号与来自DDS1的信号一起进入鉴相器;鉴相生成的误差信号经过环路滤波器进行低通滤波,滤波后的误差信号用于调节压控振荡器的输出频率,即本振信号2;本振信号2的频率等于倍频锁相C与DDS1的输出频率之和。3. A kind of satellite transponder according to claim 1, characterized in that: the frequency-shift phase-locked A comprises a phase detector, a loop filter, a voltage-controlled oscillator and a down-mixer; the initial phase of the voltage-controlled oscillator The output frequency is down-mixed with the clock from the multiplier phase-locked C to form a low-frequency signal; the low-frequency signal enters the phase detector together with the signal from DDS1; the error signal generated by the phase detection is low-pass filtered through the loop filter, The filtered error signal is used to adjust the output frequency of the voltage-controlled oscillator, that is, the local oscillator signal 2; the frequency of the local oscillator signal 2 is equal to the sum of the output frequency of the multiplier phase-locked C and DDS1.
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