CN102739173B - Transconductance amplifier, resistor, inductor and filter - Google Patents

Abstract

The present application discloses a transconductance amplifier, a resistor, an inductor and a filter. The transconductance amplifier of the present application is composed of three sets of source degenerate differential amplifiers, wherein one set of amplifiers consists of the seventh PMOS transistor, the eighth PMOS transistor, the fifth PMOS tube and the sixth PMOS tube, the second group of amplifiers is composed of the ninth PMOS tube, the tenth PMOS tube, the eleventh PMOS tube and the twelfth PMOS tube, the third group of amplifiers is composed of the seventeenth PMOS tube, the tenth PMOS tube Composed of eight PMOS transistors, the nineteenth PMOS transistor and the twentieth PMOS transistor, the output terminals of the three groups of amplifiers are cross-connected, so that the third harmonic can be eliminated by current subtraction, thereby achieving low power consumption and high transconductance amplifier. linearity. Furthermore, the resistance, inductance and the circuit composed of the resistance and/or inductance simulated by the transconductance amplifier can also achieve low power consumption and high linearity.

Description

A transconductance amplifier, resistor, inductor and filter

technical field

The present application relates to the field of circuits, in particular to a transconductance amplifier, a resistor, an inductor and a filter.

Background technique

With the rapid development of communication technology, especially mobile communication technology and computing technology, as a key module in modern receivers, especially zero-IF receivers, the transconductance-capacitance (Gm-C) filter can be used after the mixer Carry out signal filtering processing to provide signals with less spurious spectrum for the variable gain amplifier of the subsequent stage, which can be effectively used in variable gain amplifiers (VGA, VariableGainAmplifier), analog/digital converters (ADC, Analog-to- DigitalConverter) preliminarily processes the signal, and prevents the variable gain amplifier of the subsequent stage from being saturated due to excessive out-of-band signals.

In the mobile digital video broadcasting system, the Gm-C filter located in the intermediate frequency part of the receiver needs to process a large input signal, and the filter is required to ensure high linearity with low power consumption.

Contents of the invention

In view of this, the technical problem to be solved in the present application is to provide a transconductance amplifier, a resistor, an inductor and a filter, which can ensure high linearity of the filter with low power consumption.

For this reason, the embodiment of the application adopts the following technical solutions:

A transconductance amplifier comprising:

The gate of the first NMOS transistor is connected to the tuning voltage input terminal of the transconductance amplifier; the source of the first NMOS transistor is grounded, and the drain is connected to the drain of the second PMOS transistor;

The gates and sources of the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the thirteenth PMOS transistor, the fourteenth PMOS transistor, the fifteenth PMOS transistor, and the sixteenth PMOS transistor are connected correspondingly; and, The gate of the second PMOS transistor is connected to the drain of the second PMOS transistor; the source of the second PMOS transistor is connected to the power supply voltage input terminal of the transconductance amplifier;

The drain of the third PMOS transistor is respectively connected to the drain of the fifth PMOS transistor, the source of the sixth PMOS transistor and the source of the seventh PMOS transistor;

The drain of the fourth PMOS transistor is respectively connected to the source of the fifth PMOS transistor, the drain of the sixth PMOS transistor and the source of the eighth PMOS transistor;

The drain of the thirteenth PMOS transistor is respectively connected to the source of the ninth PMOS transistor, the source of the eleventh PMOS transistor, and the drain of the twelfth PMOS transistor;

The drain of the fourteenth PMOS transistor is respectively connected to the source of the tenth PMOS transistor, the drain of the eleventh PMOS transistor and the source of the twelfth PMOS transistor;

The drain of the fifteenth PMOS transistor is respectively connected to the drain of the seventeenth PMOS transistor, the source of the eighteenth PMOS transistor, and the source of the nineteenth PMOS transistor;

The drain of the sixteenth PMOS transistor is respectively connected to the source of the seventeenth PMOS transistor, the drain of the eighteenth PMOS transistor and the source of the twentieth PMOS transistor;

The grid of the sixth PMOS transistor, the grid of the eighth PMOS transistor, the grid of the ninth PMOS transistor and the grid of the eleventh PMOS transistor are all connected to the non-inverting input terminal of the transconductance amplifier;

The grid of the tenth PMOS transistor, the grid of the twelfth PMOS transistor, the grid of the eighteenth PMOS transistor and the grid of the nineteenth PMOS transistor are all connected to the negative phase input terminal of the transconductance amplifier;

The grid of the fifth PMOS transistor, the grid of the seventh PMOS transistor, the grid of the seventeenth PMOS transistor and the grid of the twentieth PMOS transistor are all grounded;

The gate of the twenty-first NMOS transistor is connected to the gate of the twenty-second NMOS transistor, and is connected to the common-mode feedback voltage terminal of the transconductance amplifier; the source of the twenty-first NMOS transistor and the gate of the twenty-second NMOS transistor source ground;

The drain of the seventh PMOS transistor, the drain of the ninth PMOS transistor, the drain of the nineteenth PMOS transistor and the drain of the twenty-first NMOS transistor are all connected to the negative phase output terminal of the transconductance amplifier;

The drains of the eighth PMOS transistor, the tenth PMOS transistor, the twentieth PMOS transistor and the twenty-second NMOS transistor are all connected to the non-inverting output terminal of the transconductance amplifier.

It also includes: the source of the twenty-third PMOS transistor and the source of the twenty-fourth PMOS transistor are connected to the power supply voltage input end of the transconductance amplifier; the gate of the twenty-third PMOS transistor is connected to the gate of the twenty-fourth PMOS transistor The pole is connected to the bias voltage terminal;

The drain of the twenty-third PMOS transistor is respectively connected to the source of the twenty-fifth PMOS transistor and the source of the twenty-sixth PMOS transistor; the drain of the twenty-fourth PMOS transistor is respectively connected to the source of the twenty-seventh PMOS transistor pole and the source of the twenty-eighth PMOS transistor;

The gate of the twenty-fifth PMOS transistor is connected to the non-inverting output terminal of the transconductance amplifier, and the drain is connected to the drain of the thirtieth NMOS transistor and the drain of the twenty-eighth PMOS transistor;

The gate of the twenty-sixth PMOS transistor is connected to the reference voltage terminal with the gate of the twenty-seventh PMOS transistor, and the drain is respectively connected to the drain of the twenty-seventh PMOS transistor and the drain of the twenty-ninth NMOS transistor;

The gate of the twenty-eighth PMOS transistor is connected to the negative phase output terminal of the transconductance amplifier;

The gate and drain of the twenty-ninth NMOS transistor are connected to the common mode feedback voltage terminal; the source of the twenty-ninth NMOS transistor is grounded;

The gate of the thirtieth NMOS transistor is connected to the drain, and the source is grounded.

A resistor comprising the transconductance amplifier of claim 1, wherein,

The negative phase output terminal of the transconductance amplifier is connected with the common mode feedback voltage terminal of the transconductance amplifier;

The positive phase output terminal of the transconductance amplifier is connected with the negative phase input terminal of the transconductance amplifier, and the connection point of this connection is used as the first end of the resistance;

The negative input terminal of the transconductance amplifier acts as the second terminal of the resistor.

A resistor comprising the transconductance amplifier of claim 2, wherein,

The positive phase input terminal of the transconductance amplifier is connected with the negative phase output terminal of the transconductance amplifier, and the connection point of the connection is used as the first end of the resistance;

The negative-phase input terminal of the transconductance amplifier is connected to the positive-phase output terminal of the transconductance amplifier, and the connection point of the connection serves as the second terminal of the resistor.

An inductance comprising two transconductance amplifiers according to claim 1, being respectively a first transconductance amplifier and a second transconductance amplifier, wherein,

The negative-phase output terminal of the first transconductance amplifier is connected with the common-mode feedback voltage terminal of the first transconductance amplifier; the negative-phase output terminal of the second transconductance amplifier is connected with the common-mode feedback voltage terminal of the second transconductance amplifier;

The first end of the inductance is grounded through the first capacitor, and is respectively connected with the non-inverting output end of the first transconductance amplifier and the non-inverting input end of the second transconductance amplifier; the second end of the inductance is respectively connected with the first transconductance amplifier The non-inverting input terminal and the non-inverting output terminal of the second transconductance amplifier are connected;

The negative phase input terminal of the first transconductance amplifier is grounded, and the negative phase input terminal of the second transconductance amplifier is grounded.

A filter, comprising the transconductance amplifier described in any one of claims 1 to 2, and/or the resistor described in any one of claims 3 to 4, and/or the inductor described in claim 5.

also includes a PLL tuner where,

The output of the voltage controlled oscillator is connected to the first input of the frequency and phase detector, and the second input of the frequency and phase detector receives the reference frequency signal; the output of the frequency and phase detector is connected to the loop filter through the charge pump The input terminal of the loop filter is respectively connected to the input terminal of the voltage controlled oscillator and the tuning voltage input terminal in the filter.

The technical effect analysis for the above-mentioned technical scheme is as follows:

The transconductance amplifier of this application is composed of three sets of source degenerate differential amplifiers, one set of amplifiers consists of the seventh PMOS transistor, the eighth PMOS transistor, the fifth PMOS transistor and the sixth PMOS transistor, and the second set of amplifiers consists of the ninth PMOS transistor tube, the tenth PMOS tube, the eleventh PMOS tube, and the twelfth PMOS tube, and the third group of amplifiers consists of the seventeenth PMOS tube, the eighteenth PMOS tube, the nineteenth PMOS tube, and the twentieth PMOS tube. The output terminals of the three groups of amplifiers are cross-connected, so that the third-order harmonic can be eliminated by means of current subtraction, thereby realizing the low power consumption and high linearity of the transconductance amplifier, and then enabling the filter using the transconductance amplifier to operate High linearity is guaranteed at very low power consumption.

Description of drawings

Fig. 1 is the schematic diagram of the first embodiment of the transconductance amplifier of the present application;

Fig. 2 is a schematic structural diagram of the common mode feedback circuit of the present application;

Fig. 3 is the schematic diagram of the first embodiment of the resistance of the present application;

Fig. 4 is the schematic diagram of the first embodiment of the inductor of the present application;

Fig. 5 is a schematic diagram of the third embodiment of the resistor of the present application;

Fig. 6 is a schematic structural diagram of a 7th-order elliptic filter of the present application;

Fig. 7 is a schematic diagram of the first embodiment of the filter of the present application;

FIG. 8 is a schematic diagram of a second embodiment of the filter of the present application;

FIG. 9 is a simplified circuit structure diagram of the transconductance amplifier described in the present application.

detailed description

Hereinafter, the implementation of the transconductance amplifier, resistor, inductor and filter of the present application will be described in detail with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of the structure of the transconductance amplifier of the present application, as described in Fig. 1, the transconductance amplifier includes:

The gate of the first NMOS transistor M1 is connected to the tuning voltage input terminal VTUNE of the transconductance amplifier; the source of the first NMOS transistor M1 is grounded, and the drain is connected to the drain of the second PMOS transistor M2;

The gate and source of the second PMOS transistor M2, the third PMOS transistor M3, the fourth PMOS transistor M4, the thirteenth PMOS transistor M13, the fourteenth PMOS transistor M14, the fifteenth PMOS transistor M15, and the sixteenth PMOS transistor M16 and the gate of the second PMOS transistor M2 is connected to the drain of the second PMOS transistor M2; the source of the second PMOS transistor M2 is connected to the power supply voltage input terminal VC of the transconductance amplifier;

The drain of the third PMOS transistor M3 is respectively connected to the drain of the fifth PMOS transistor M5, the source of the sixth PMOS transistor M6 and the source of the seventh PMOS transistor M7;

The drain of the fourth PMOS transistor M4 is respectively connected to the source of the fifth PMOS transistor M5, the drain of the sixth PMOS transistor M6, and the source of the eighth PMOS transistor M8;

The drain of the thirteenth PMOS transistor M13 is respectively connected to the source of the ninth PMOS transistor M9, the source of the eleventh PMOS transistor M11, and the drain of the twelfth PMOS transistor M12;

The drain of the fourteenth PMOS transistor M14 is respectively connected to the source of the tenth PMOS transistor M10, the drain of the eleventh PMOS transistor M11, and the source of the twelfth PMOS transistor M12;

The drain of the fifteenth PMOS transistor M15 is respectively connected to the drain of the seventeenth PMOS transistor M17, the source of the eighteenth PMOS transistor M18, and the source of the nineteenth PMOS transistor M19;

The drain of the sixteenth PMOS transistor M16 is respectively connected to the source of the seventeenth PMOS transistor M17, the drain of the eighteenth PMOS transistor M18, and the source of the twentieth PMOS transistor M20;

The gate of the sixth PMOS transistor M6, the gate of the eighth PMOS transistor M8, the gate of the ninth PMOS transistor M9, and the gate of the eleventh PMOS transistor M11 are all connected to the non-inverting input terminal VINP of the transconductance amplifier;

The gate of the tenth PMOS transistor M10, the gate of the twelfth PMOS transistor M12, the gate of the eighteenth PMOS transistor M18, and the gate of the nineteenth PMOS transistor M19 are all connected to the negative phase input terminal VINN of the transconductance amplifier ;

The gate of the fifth PMOS transistor M5, the gate of the seventh PMOS transistor M7, the gate of the seventeenth PMOS transistor M17, and the gate of the twentieth PMOS transistor M20 are all grounded;

The gate of the twenty-first NMOS transistor M21 is connected to the gate of the twenty-second NMOS transistor M22, and connected to the common-mode feedback voltage terminal VCMFB of the transconductance amplifier; the source of the twenty-first NMOS transistor M21 and the twenty-second The source of the NMOS transistor M22 is grounded;

The drain of the seventh PMOS transistor M7, the drain of the ninth PMOS transistor M9, the drain of the nineteenth PMOS transistor M19, and the drain of the twenty-first NMOS transistor M21 are all connected to the negative phase output terminal VOUTN of the transconductance amplifier ;

The drain of the eighth PMOS transistor M8, the drain of the tenth PMOS transistor M10, the drain of the twentieth PMOS transistor M20, and the drain of the twenty-second NMOS transistor M22 are all connected to the non-inverting output terminal VOUTP of the transconductance amplifier .

The structure of the transconductance amplifier shown in Figure 1 is composed of three sets of source degenerate differential amplifiers, one of which is composed of the seventh PMOS transistor M7, the eighth PMOS transistor M8, the fifth PMOS transistor M5 and the sixth PMOS transistor M6, and the sixth PMOS transistor M6. The second group of amplifiers consists of the ninth PMOS transistor M9, the tenth PMOS transistor M10, the eleventh PMOS transistor M11 and the twelfth PMOS transistor M12, and the third group of amplifiers consists of the seventeenth PMOS transistor, the eighteenth PMOS transistor, the tenth PMOS transistor Nine PMOS tubes and 20 PMOS tubes are composed, and the output terminals of the three sets of amplifiers are cross-connected, so that the third-order harmonics can be eliminated by current subtraction, thereby achieving low power consumption and high linearity of the transconductance amplifier.

Furthermore, when the transconductance amplifier is applied to a filter, such as a Gm-C filter, low power consumption and high linearity of the filter can be achieved.

In the actual application scenario of the transconductance amplifier shown in Figure 1, when the transconductance amplifier needs to realize double-ended input and single-ended output, the negative phase output terminal of the transconductance amplifier can be connected to the common-mode feedback voltage terminal VCMFB of the transconductance amplifier, Realize double-ended input and single-ended output of transconductance amplifier.

Or, in practical application scenarios, when a transconductance amplifier is required to achieve dual-terminal input and dual-terminal output, it is generally necessary to control the common-mode level of the transconductance amplifier shown in Figure 1, that is, the common-mode feedback of the transconductance amplifier The voltage of the voltage terminal VCMFB is controlled. At this time, the transconductance amplifier shown in FIG. 1 can further include a common-mode feedback circuit as shown in FIG. 2 to form another transconductance amplifier structure, as shown in FIG. The common-mode feedback circuit consists of:

The source of the twenty-third PMOS transistor M23 and the source of the twenty-fourth PMOS transistor M24 are connected to the power supply voltage input terminal VC of the transconductance amplifier; the gate of the twenty-third PMOS transistor M23 is connected to the twenty-fourth PMOS transistor M24 The gate of the transconductance amplifier is connected to the bias voltage terminal VBIAS;

The drain of the twenty-third PMOS transistor M23 is respectively connected to the source of the twenty-fifth PMOS transistor M25 and the source of the twenty-sixth PMOS transistor M26; the drain of the twenty-fourth PMOS transistor M24 is connected to the twenty-seventh PMOS transistor M24 respectively. the source of the PMOS transistor M27 and the source of the twenty-eighth PMOS transistor M28;

The gate of the twenty-fifth PMOS transistor M25 is connected to the non-inverting output terminal VOUTP of the transconductance amplifier, and the drain is connected to the drain of the thirtieth NMOS transistor M30 and the drain of the twenty-eighth PMOS transistor M28;

The gate of the twenty-sixth PMOS transistor M26 and the gate of the twenty-seventh PMOS transistor M27 are connected to the reference voltage terminal VREF of the transconductance amplifier, and the drains are connected to the drain of the twenty-seventh PMOS transistor M27 and the twenty-ninth PMOS transistor M27 respectively. The drain of the NMOS transistor M29;

The gate of the twenty-eighth PMOS transistor M28 is connected to the negative phase output terminal VOUTN of the transconductance amplifier;

The gate and drain of the twenty-ninth NMOS transistor M29 are connected to the common-mode feedback voltage terminal VCMFB of the transconductance amplifier; the source of the twenty-ninth NMOS transistor M29 is grounded;

The gate of the thirtieth NMOS transistor M30 is connected to the drain, and the source is grounded.

For the circuits shown in Figure 1 and Figure 2, the voltage input by the tuning voltage input terminal VTUNE of the transconductance amplifier can be a certain constant voltage, or it can also be an adjustable voltage within a certain range, and the specific voltage value can be in In actual application, it is determined according to the application environment, and there is no limitation here.

Generally, the bias voltage terminal VBIAS can be connected to the gate of the second PMOS transistor M2, so that the voltage of the bias voltage terminal VBIAS changes with the voltage value of the tuning voltage input terminal VTUNE; or, it can also be the bias voltage terminal VBIAS inputs a voltage with a certain fixed value, and the specific voltage value can be determined according to the application environment in practical applications, and is not limited here.

Generally, a certain fixed value voltage can be input for the reference voltage terminal VREF, and the specific voltage value can be determined according to the application environment in practical applications, and is not limited here.

The power supply voltage input terminal VC is generally connected to the power supply of the transconductance amplifier, and is used to supply power to each device in the transconductance amplifier.

Wherein, when a resistor or an inductor is required in a practical application such as a circuit such as a filter, the transconductance amplifier shown in FIG. 1 above, or the transconductance amplifier obtained by combining FIG. 1 and FIG. 2 can be used to simulate the resistance or inductance.

Specifically, in the application scenario where a transconductance amplifier with double-ended input and single-ended output is required, the resistance or inductance can be simulated through the transconductance amplifier shown in Figure 1, so that the resistance and inductance in the circuit change from passive components to active components. Source device; As shown in Figure 4, it is a schematic diagram of the resistance structure obtained by the simulation of the transconductance amplifier of Figure 1, and as shown in Figure 5, it is a schematic diagram of the structure of the inductor obtained by the simulation of the transconductance amplifier of Figure 1;

In the application scenario where a transconductance amplifier with double-ended input and double-ended output is required, the transconductance amplifier obtained by combining Figure 1 and Figure 2 can be used to simulate resistance or inductance; Figure 6 shows the combination of Figure 1 and Figure 2 Schematic diagram of the resistor structure obtained from the simulation of the transconductance amplifier.

As shown in Figure 3, the resistance structure simulated by the transconductance amplifier includes:

Transconductance amplifier gm, described transconductance amplifier gm can use the structure shown in Fig. 1 to realize;

Additionally, this resistor includes:

The negative phase output terminal of the transconductance amplifier gm is connected to the common-mode feedback voltage terminal of the transconductance amplifier gm (not shown in the figure);

The positive phase output terminal of the transconductance amplifier gm is connected with the negative phase input terminal of the transconductance amplifier gm, and the connection point of the connection is used as the first end of the resistance;

The non-inverting input terminal of the transconductance amplifier gm acts as the second terminal of the resistor.

Wherein, the resistance can be used as a grounding resistance or a floating resistance. When one of the first end and the second end of the resistance described in FIG. 3 is grounded, and the other end is connected to other devices, the resistance is a grounding resistance; When both the terminal and the second terminal are connected to other devices, the resistance is a floating resistance.

Fig. 4 is the inductance simulated by the transconductance amplifier shown in Fig. 1. As shown in Fig. 4, the inductance includes:

Two transconductance amplifiers shown in Fig. 1 are respectively the first transconductance amplifier gm1 and the second transconductance amplifier gm2, wherein,

The negative phase output terminal of the first transconductance amplifier gm1 is connected with the common mode feedback voltage end of the first transconductance amplifier gm1 (not shown in the figure); The negative phase output terminal of the second transconductance amplifier gm2 is connected with the second transconductance amplifier gm1 The common mode feedback voltage terminal connection of gm2 (not shown in the figure);

The first end of the inductance is grounded through the first capacitor C1, and is respectively connected to the non-inverting output end of the first transconductance amplifier gm1 and the non-inverting input end of the second transconductance amplifier gm2; the second end of the inductance is respectively connected to the first transconductance amplifier gm1 The non-inverting input end of a transconductance amplifier gm1 and the non-inverting output end of the second transconductance amplifier gm2 are connected;

The negative phase input terminal of the first transconductance amplifier gm1 is grounded, and the negative phase input terminal of the second transconductance amplifier gm2 is grounded.

Figure 5 is a schematic diagram of the resistance obtained from the simulation of the transconductance amplifier, including:

Transconductance amplifier gm, this transconductance amplifier can be realized by combining the transconductance amplifier obtained in Fig. 1 and Fig. 2;

This resistor also includes:

The positive phase input terminal of the transconductance amplifier gm is connected with the negative phase output terminal of the transconductance amplifier gm, and the connection point of the connection is used as the first end of the resistance;

The negative-phase input terminal of the transconductance amplifier gm is connected to the positive-phase output terminal of the transconductance amplifier gm, and the connection point of this connection serves as the second terminal of the resistor.

The resistors and inductors shown in Figure 3 to Figure 5 above are all active devices, which can correspond to the passive resistors and passive inductors in the replacement circuit in practical applications, for example, in the 7th-order elliptic filter structure shown in Figure 6 , that is, the resistors R1 and R2 in Figure 6 can be realized using the resistors shown in Figure 3 or Figure 5 instead of passive resistors, and the inductors L1, L2, and L3 in Figure 6 can be realized using the inductors in Figure 4 instead Use passive inductors. Due to the low power consumption and high linearity of the transconductance amplifier therein, the low power consumption and high linearity of the resistance and inductance realized by the transconductance amplifier are guaranteed, and then compared with the use of passive resistance and/or Inductive circuits, such as filters, the cut-off frequency and linearity of the filter including the resistors and/or inductors are not affected by factors such as temperature and process angle, so that the filter has low power consumption and high linearity.

Of course, the filter shown in FIG. 6 is only an example, and the resistors and inductors of the present application can also be applied to other filters, or even other circuit structures including resistors and/or inductors, which can also reduce the power consumption of these circuits. Improve linearity.

For the filter comprising the resistance and/or inductance described in the present application, the filter may further include: a phase-locked loop tuner, as shown in FIG. 7, the phase-locked loop tuner may include:

The output end of the voltage controlled oscillator 810 is connected to the first input end of the frequency and phase detector 820, and the second input end of the frequency and phase detector 820 receives the reference frequency signal; The input end of the loop filter 840 is connected, and the output end of the loop filter 840 is respectively connected with the input end of the voltage controlled oscillator 810 and the tuning voltage input end VTUNE of each transconductance amplifier in the filter.

The VCO 810 is used to generate a signal source. The oscillation frequency of the voltage-controlled oscillator 810 varies with the cutoff frequency of the filter.

The transconductance amplifier described in the embodiment of the present application forms two undamped integrators, which are connected in a positive feedback form to form the voltage-controlled oscillator 810 . Its oscillation frequency changes with various characteristics of the transconductance amplifier, such as gain-bandwidth product, common-mode rejection ratio, etc., so that its output voltage frequency tracks and reflects the overall cut-off frequency characteristics of the transconductance amplifier and filter.

The frequency and phase detector 820 is used to compare the frequency and phase of the output signal output by the voltage-controlled oscillator 810 and the reference frequency signal in the digital domain, output a series of digital high and low signals, and control the charging of the charge pump 830 through the digital high and low signals and discharge.

The charge pump 830 is used to charge and discharge under the control of the output signal of the frequency and phase detector 820. Specifically, the digital signal is converted into an analog signal, and then the analog signal is filtered by the loop filter 840 and fed back to the voltage regulator. controlled oscillator 810 to form a closed-loop operation.

The loop filter 840 is used for smoothing and filtering the analog signal output by the charge pump 830 .

The filtering can reduce the burr and signal jitter of the analog signal output by the charge pump 830, thereby reducing phase noise and improving the accuracy of the entire phase-locked loop tuning circuit.

Wherein, the voltage-controlled oscillator 810, the frequency and phase detector 820, the charge pump 830 and the loop filter 840 constitute a phase-locked loop tuner, which can realize the tuning of the input voltage in the tuning voltage input terminal VTUNE in the transconductance amplifier , so as to ensure the tuning accuracy and the accuracy of the cutoff frequency of the filter under the condition of smaller power consumption.

For example, the phase-locked loop tuner can specifically be realized through the structure shown in FIG. 8, wherein:

The output terminal of the voltage-controlled oscillator is connected to the first input terminal of the multiplier, the second input terminal of the multiplier receives the reference frequency signal, the output terminal of the multiplier is connected to the input terminal of the low-pass filter, and the first output of the low-pass filter The terminal is connected to the input terminal of the voltage-controlled oscillator, and the second output terminal of the low-pass filter is connected to the tuning voltage input terminals of each transconductance amplifier in the filter. The loop filter 840 is implemented by the low-pass filter, and the frequency and phase detector 820 and the charge pump 830 are implemented by the multiplier.

Finally, the principle that the transconductance amplifier shown in Figure 1 can eliminate the third-order harmonic is explained:

To simplify the analysis, the transconductance amplifier circuit shown in Figure 1 is simplified to the circuit diagram structure shown in Figure 9. Each small block represents a group of differential amplifiers in the transconductance amplifier, and the values on it represent the relative proportion of their transconductance.

Since the input signal is composed of differential mode signal and common mode signal components, it can be seen from Figure 9 that one of the input terminals of the two differential amplifiers is grounded. It can be known by derivation that due to the cross-coupling connection mode of the output, the overall circuit can still be used as a fully differential circuit use.

Assuming that the magnitude and flow of the current are shown in Figure 1, the total output current i _o of the transconductance amplifier is:

i _o =i ₀₁ -i ₀₂ -i ₀₃ (1)

Among them, i _o represents the total output current of the transconductance amplifier. Since the transconductance amplifier in Fig. 1 adopts the form of double-ended input and double-ended output, the total output current i _o is the difference between the three output branch currents, i _o1 represents half of the output current of the first group of amplifiers composed of the seventh PMOS transistor M7 and the eighth PMOS transistor M8, i _o2 represents half of the output current of the second group of amplifiers composed of the ninth PMOS transistor M9 and the tenth PMOS transistor M10; i _o3 represents half of the output current of the second group of amplifiers formed by the nineteenth PMOS transistor M9 and the twentieth PMOS transistor M10; the purpose of defining the output currents of the three amplifiers here is to demonstrate the feasibility of high linearity mathematically.

Assuming that all MOS transistors in the circuit work in the saturation region, according to the leakage current saturation region formula:

i _d ＝K(v _g -v _s -V _th ) ² (2)

$\mathrm{<span\; class="notranslate">\; K</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;C</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; x</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Among them, _id represents the drain output current of a single MOS tube; K represents the current coefficient of the MOS tube in a certain process, which is a parameter determined by the process and the width-to-length ratio W/L of the MOS tube, as long as the process and width The length ratio is determined, it is a fixed value; Vg refers to the gate voltage of the MOS tube; Vs refers to the source voltage of the MOS tube; Vth refers to the threshold voltage of the MOS tube, which is also a parameter determined by the process; Width, L represents the length of the MOS tube; μ is the carrier mobility, and C _ox is the capacitance of the gate oxide region per unit area.

According to the relationship between g _m and DC saturation voltage:

g _m =2KV _dssat (4)

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; the\; s</span>}\mathrm{<span\; class="notranslate">\; a</span>}\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; =</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; K</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

Among them, W represents the width of the MOS tube, L represents the length of the MOS tube; V _dssat represents the DC saturation voltage of the MOS tube, in Figure 1, each MOS tube has its DC saturation voltage, and this DC saturation voltage will affect The working state of each MOS tube (saturation region, linear region, sub-threshold region, cut-off region), and then affect the performance of the transconductance amplifier.

In order to simplify the analysis process, using Taylor series to expand v _in at v _in = 0 can be obtained

${\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}}{<span\; class="notranslate">\; \&Sigma;</span>}{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; no</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

in $G_{mj}=\frac{g_m}{2^{2(j-1)}{V_{d\mathrm{the\; s}\mathrm{the\; s}at}}^{j-1}}---\left(7\right);$

Define the source degeneracy factor $N_{r1,2}=G_{m1}\&Center\; Dot;\frac{1}{g_{m5,6,11,12,17,18}},$ in It is the equivalent resistance of the fifth PMOS transistor M5, the sixth PMOS transistor M6, the eleventh PMOS transistor M11, the twelfth PMOS transistor M12, the seventeenth PMOS transistor M17, and the eighteenth PMOS transistor M18 working in the deep triode region. Substituting formula (6) and formula (7) into (1) for simplified analysis can be obtained (only the first-order item and the third-order item are considered):

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}<span\; class="notranslate">\; )</span>\\ <span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 4</span>}}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span>\\ <span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 7</span>}}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{<span\; class="notranslate">\; (</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{<span\; class="notranslate">\; (</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; )</span>\end{array}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

Simplification can be obtained:

$\begin{array}{c}{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}\\ <span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 6</span>}}{\mathrm{<span\; class="notranslate">\; 7</span>}}\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 4</span>}}}{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}\mathrm{<span\; class="notranslate">\; m</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}\\ <span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 13</span>}}{\mathrm{<span\; class="notranslate">\; 112</span>}}\frac{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 7</span>}}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 5</span>}}\end{array}$

In the deep submicron process, if v _cm is much smaller than 1, the third harmonic term of the transconductance amplifier can be approximately eliminated, leaving only the smaller fifth harmonic component, and the total harmonic distortion (THD) will be greatly reduced. Total Harmonic Distortion can be approximated as follows:

$\mathrm{<span\; class="notranslate">\; T</span>}\mathrm{<span\; class="notranslate">\; h</span>}\mathrm{<span\; class="notranslate">\; D.</span>}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 13</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; +</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 3</span>}{{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 3</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 28</span>}{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; G</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; 18</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 6</span>}}}{{\mathrm{<span\; class="notranslate">\; v</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 4</span>}}<span\; class="notranslate">\; .</span>$

Based on the above analysis, it can be seen that the transconductance amplifier shown in Figure 1 can approximately eliminate the third harmonic term and improve THD. Furthermore, high linearity can be secured at low power consumption.

In addition, the transconductance amplifier of the embodiment of the present application is formed by cross-coupling three source-degenerate transconductance amplifiers with different ratios, which can achieve high linearity with low power consumption under the condition of deep submicron CMOS technology degree, and its linearity varies little with environmental conditions.

The transconductance amplifier and/or resistance and/or inductance of the embodiment of the present application can be applied to various existing circuits, especially filters, such as Gm-C filters, to meet the requirements of receiver systems, especially zero-IF The receiver system requires high linearity; in addition, the transconductance amplifier can also be applied to mobile video signal transmission and switched capacitor circuits to meet the high linearity requirements of both. Moreover, when applied to a Gm-C filter, the tuning accuracy and filter cutoff frequency accuracy can be guaranteed under the condition of relatively small power consumption.

The components of the transconductance amplifier circuit all use CMOS transistors, and no other components such as resistors are used, so that better on-chip matching can be achieved.

In addition, the transconductance amplifier of the embodiment of the present application can adapt to a lower power supply voltage under the deep submicron CMOS standard process, which conforms to the current low-voltage CMOS trend, and the lower power supply voltage helps to improve the linearity of the transconductance amplifier.

The above description is only the preferred embodiment of the present application, and it should be pointed out that for those of ordinary skill in the art, some improvements and modifications can also be made without departing from the principle of the application. It should be regarded as the protection scope of this application.

Claims (7)

1. a trsanscondutance amplifier, is characterized in that, comprising:

The grid of the first NMOS tube connects the tuning voltage input of trsanscondutance amplifier; The source ground of the first NMOS tube, the drain electrode of drain electrode connection second PMOS;

Second PMOS, the 3rd PMOS, the 4th PMOS, the 13 PMOS, the 14 PMOS, the 15 PMOS, the grid of the 16 PMOS, source electrode are connected respectively; And the grid of the second PMOS is connected with the drain electrode of the second PMOS; The source electrode of the second PMOS connects the power voltage input terminal of trsanscondutance amplifier;

The drain electrode of the 3rd PMOS connects the source electrode of the drain electrode of the 5th PMOS, the source electrode of the 6th PMOS and the 7th PMOS respectively;

The drain electrode of the 4th PMOS connects the source electrode of the source electrode of the 5th PMOS, the drain electrode of the 6th PMOS and the 8th PMOS respectively;

The drain electrode of the 13 PMOS connects the source electrode of the 9th PMOS, the source electrode of the 11 PMOS and the drain electrode of the 12 PMOS respectively;

The drain electrode of the 14 PMOS connects the source electrode of the tenth PMOS, the drain electrode of the 11 PMOS and the source electrode of the 12 PMOS respectively;

The drain electrode of the 15 PMOS connects the drain electrode of the 17 PMOS, the source electrode of the 18 PMOS and the source electrode of the 19 PMOS respectively;

The drain electrode of the 16 PMOS connects the source electrode of the 17 PMOS, the drain electrode of the 18 PMOS and the source electrode of the 20 PMOS respectively;

The grid of the 6th PMOS, the grid of the 8th PMOS, the grid of the 9th PMOS and the grid of the 11 PMOS are all connected with the normal phase input end of trsanscondutance amplifier;

The grid of the grid of the tenth PMOS, the grid of the 12 PMOS, the grid of the 18 PMOS and the 19 PMOS is all connected with the negative-phase input of trsanscondutance amplifier;

The grid of the 5th PMOS, the grid of the 7th PMOS, the grid of the 17 PMOS and the equal ground connection of grid of the 20 PMOS;

The grid of the 21 NMOS tube is connected with the grid of the 22 NMOS tube, and connects the common mode feedback voltage end of trsanscondutance amplifier; The source electrode of the 21 NMOS tube and the source ground of the 22 NMOS tube;

The drain electrode of the 7th PMOS, the drain electrode of the 9th PMOS, the drain electrode of the 19 PMOS and the drain electrode of the 21 NMOS tube are all connected with the negative output of trsanscondutance amplifier;

The drain electrode of the 8th PMOS, the drain electrode of the tenth PMOS, the drain electrode of the 20 PMOS and the drain electrode of the 22 NMOS tube are all connected with the positive output end of trsanscondutance amplifier.

2. trsanscondutance amplifier according to claim 1, is characterized in that, also comprises:

The source electrode of the 23 PMOS and the source electrode of the 24 PMOS connect the power voltage input terminal of trsanscondutance amplifier; The grid of the 23 PMOS is connected biased electrical pressure side with the grid of the 24 PMOS;

The drain electrode of the 23 PMOS connects the source electrode of the 25 PMOS and the source electrode of the 26 PMOS respectively; The drain electrode of the 24 PMOS connects the source electrode of the 27 PMOS and the source electrode of the 28 PMOS respectively;

The grid of the 25 PMOS connects the positive output end of trsanscondutance amplifier, the drain electrode of drain electrode connection the 30 NMOS tube and the drain electrode of the 28 PMOS;

The grid of the 26 PMOS is connected reference voltage end with the grid of the 27 PMOS, and drain electrode connects the drain electrode of the 27 PMOS and the drain electrode of the 29 NMOS tube respectively;

The grid of the 28 PMOS connects the negative output of trsanscondutance amplifier;

The grid of the 29 NMOS tube is connected common mode feedback voltage end with drain electrode; The source ground of the 29 NMOS tube;

The grid of the 30 NMOS tube is connected with drain electrode, source ground.

3. a resistance, is characterized in that, comprises trsanscondutance amplifier according to claim 1, wherein,

The negative output of trsanscondutance amplifier is connected with the common mode feedback voltage end of trsanscondutance amplifier;

The positive output end of trsanscondutance amplifier is connected with the negative-phase input of trsanscondutance amplifier, and the tie point of this connection is as the first end of resistance;

The normal phase input end of trsanscondutance amplifier is as the second end of resistance.

4. a resistance, is characterized in that, comprises trsanscondutance amplifier according to claim 2, wherein,

The normal phase input end of trsanscondutance amplifier is connected with the negative output of trsanscondutance amplifier, and the tie point of this connection is as the first end of described resistance;

The negative-phase input of trsanscondutance amplifier is connected with the positive output end of trsanscondutance amplifier, and the tie point of this connection is as the second end of described resistance.

5. an inductance, is characterized in that, comprises two trsanscondutance amplifiers according to claim 1, is respectively the first trsanscondutance amplifier and the second trsanscondutance amplifier, wherein,

The negative output of the first trsanscondutance amplifier is connected with the common mode feedback voltage end of the first trsanscondutance amplifier; The negative output of the second trsanscondutance amplifier is connected with the common mode feedback voltage end of the second trsanscondutance amplifier;

The first end of inductance by the first capacity earth, and is connected with the positive output end of the first trsanscondutance amplifier, the normal phase input end of the second trsanscondutance amplifier respectively; Second end of inductance is connected with the normal phase input end of the first trsanscondutance amplifier, the positive output end of the second trsanscondutance amplifier respectively;

The negative-phase input ground connection of the first trsanscondutance amplifier, the negative-phase input ground connection of the second trsanscondutance amplifier.

6. a filter, is characterized in that, comprises the trsanscondutance amplifier described in any one of claim 1 to 2, and/or, the resistance described in any one of claim 3 to 4, and/or, inductance according to claim 5.

7. filter as claimed in claim 6, is characterized in that, also comprise phase-locked loop tuner, wherein,

The output of voltage controlled oscillator connects the first input end of phase frequency detector, and the second input of phase frequency detector receives reference frequency signal; The output of phase frequency detector is by the input of charge pump linkloop filter, and the output of loop filter connects the tuning voltage input in the input of voltage controlled oscillator and filter respectively.