CN102739167B - Design method of microwave amplifier - Google Patents

Abstract

The invention discloses a design method of a microwave amplifier, and belongs to the technical field of circuit design. The method comprises fitting an input or output impedance of the transistor within a target frequency range; obtaining an equivalent network of input or output impedance by adopting a numerical calculation method; constructing a conjugate network corresponding to the equivalent network, and connecting the conjugate network with the transistor; optimizing the conjugate network to obtain the optimal input or output conjugate network; obtaining an optimal input or output equivalent network according to the optimal input or output 'conjugate' network; matching the optimal input or output equivalent network to the terminating impedance to obtain an optimal matching network; and connecting the optimal matching network with the transistor to complete the design of the amplifier. The method has high design efficiency, is favorable for visually representing the mutual influence between input or output and can fully exert the performance of the transistor.

Description

A Design Method of Microwave Amplifier

technical field

The invention relates to the technical field of circuit design, in particular to a design method of a microwave amplifier.

Background technique

In modern microwave systems, the amplifier is one of the most basic and widespread microwave functional circuits. Early microwave amplifiers relied on tubes such as klystrons and traveling wave tubes or solid-state reflective amplifiers based on the negative resistance properties of tunnel diodes or varactors. But since the 1970s, most RF and microwave amplifiers have used transistor devices such as Si, SiGe BJTs, GaAs HBTs, GaAs, InP FETs, and GaN HEMTs.

The essence of microwave circuits is the transmission or transformation of energy. The core issue is to correctly deal with the relationship between the impedance, frequency and power of the circuit. The three are independent and affect each other. Therefore, in RF/microwave circuits, the design of impedance matching network is very important. At the same time, due to the gain roll-off characteristics of semiconductor transistors, the design of high-frequency amplifiers requires more careful consideration.

In the design of traditional microwave amplifiers, the commonly used method is to use EDA tools to design the initial input or output impedance matching network at the center frequency point according to the design indicators of the amplifier, and then connect the matching network to the transistor and optimize it. Typically used in single-stage amplifiers or amplifier designs with matching networks with fewer components. However, if the structure of the amplifier is complex, such as multi-stage cascade connection, the amplifier has at least one inter-stage matching network in addition to the input or output matching network. Sometimes, due to broadband design or other performance considerations, a multi-stage matching network is required. At this time, the number of matching components will increase rapidly. Since the characteristics of transistors changing with frequency are different from the simple linear characteristics of passive components, in this case, if Still using EDA tools to design the entire circuit, the efficiency is very low, and it is not conducive to intuitively reflect the mutual influence between the input or output and to fully utilize the performance of the transistor, resulting in the waste of the precious gain of the high-frequency transistor.

Contents of the invention

In order to solve the above problems, the present invention proposes a design method of a microwave amplifier that improves design efficiency, is beneficial to intuitively reflect the mutual influence between input and output, and can fully utilize the transistor performance.

The design method of the microwave amplifier provided by the invention comprises the following steps:

Fitting the input or output impedance of the transistor over the frequency range of interest;

Obtaining the equivalent network of the input or output impedance by numerical calculation method;

constructing a "conjugate" network corresponding to the equivalent network, and connecting the "conjugate" network to the transistor;

Optimizing the "conjugate" network to obtain the best input or output "conjugate" network;

obtaining an optimal input or output equivalent network from said optimal input or output "conjugated" network;

Matching the optimal input or output equivalent network to the termination impedance to obtain the optimal matching network; connecting the optimal matching network to a transistor to complete the design of the amplifier.

Preferably, when the amplifier is a multi-stage amplifier, it also includes an inter-stage optimal matching network, and the inter-stage optimal matching network is to match the best input matching network of the latter stage to the best output matching network of the previous stage. network got.

Preferably, the input or output impedance of the fitting transistor within the target frequency range includes the following steps:

Use EDA tools to obtain the input or output impedance of the transistor at different frequencies;

A multiparameter equivalent network is used to fit the input or output impedance of a transistor over the frequency range of interest.

Preferably, said multi-parameter equivalent network includes resistance and reactance elements.

Preferably, the reactance element includes a capacitor.

Preferably, the reactance element further includes an inductor.

Preferably, the "conjugate" network of the equivalent network is obtained by taking "negative" values of the reactive elements in the equivalent network under the condition that the topology connection mode of the equivalent network remains unchanged.

Preferably, the optimal input or output equivalent network is to take the reactive element in the optimal input or output "conjugate" network as "negative" in value under the condition that the equivalent network topology connection mode remains unchanged "owned.

Preferably, the transistor includes a bare die, a packaged die, a pre-matched die, or a die with a feedback element at the source, gate or drain.

The design method of the microwave amplifier provided by the invention has high design efficiency, is beneficial to intuitively reflect the mutual influence between input and output, and can fully exert the performance of the transistor.

Description of drawings

Fig. 1 is a schematic diagram of the principle structure of a two-stage cascaded amplifier designed according to a microwave amplifier design method provided by an embodiment of the present invention;

FIG. 2 is a schematic diagram of a two-parameter input impedance equivalent network topology in the microwave amplifier design method provided by an embodiment of the present invention;

3 is a schematic diagram of a two-parameter output impedance equivalent network topology in the microwave amplifier design method provided by an embodiment of the present invention;

4 is a schematic diagram of a three-parameter input impedance equivalent network topology in the design method of a microwave amplifier provided by an embodiment of the present invention;

5 is a schematic diagram of a three-parameter output impedance equivalent network topology in the microwave amplifier design method provided by an embodiment of the present invention;

Fig. 6 is a schematic diagram of a construction method of a "conjugate" network in a microwave amplifier design method provided by an embodiment of the present invention;

FIG. 7 is a schematic structural diagram of a "conjugate" network connected to a transistor in the microwave amplifier design method provided by an embodiment of the present invention;

FIG. 8 is a schematic structural diagram of an input matching network that matches an optimal input equivalent network to a terminating impedance in the microwave amplifier design method provided by an embodiment of the present invention;

9 is a structural schematic diagram of an inter-stage matching network between the best input equivalent network of the latter stage transistor and the best output equivalent network of the former stage transistor in the microwave amplifier design method provided by the embodiment of the present invention;

FIG. 10 is a schematic structural diagram of an output matching network that matches an optimal output equivalent network to a terminating impedance in the microwave amplifier design method provided by an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a two-stage cascaded amplifier designed according to the microwave amplifier design method provided by an embodiment of the present invention;

Fig. 12 is an overall computer simulation small signal S parameter curve before optimization of the two-stage cascaded amplifier designed according to the microwave amplifier design method provided by the embodiment of the present invention, wherein the solid line represents dB(S(2,1)), The dotted line represents dB(S(1,1)) and the dashed line represents dB(S(2,2)).

detailed description

In order to deeply understand the present invention, the present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

The design method of the microwave amplifier provided by the invention comprises the following steps:

Step 1: Fit the input or output impedance of the transistor over the frequency range of interest.

Step 1.1: Use EDA tools to obtain the input or output impedance of FET1 and FET2 at different frequencies. In this embodiment, based on the microwave test of semiconductor transistors, use Smith ChartUtility or Matching Utility in ADS to obtain the resistance and reactance components of the input or output impedance corresponding to FET1 and FET2 versus frequency, and obtain the target of FET1 and FET2 through this curve Frequency Range.

Step 1.2: Fit the input or output impedance of FET1 and FET2 in the frequency range of interest using a multi-parameter equivalent network.

Among them, the multi-parameter equivalent network includes resistive and reactive elements.

Wherein, the reactance element includes a capacitor.

Wherein, the reactance element also includes an inductance, so that the equivalent network of the input or output impedance obtained under the condition of a wide frequency range of the transistor load impedance has a higher matching degree. .

Step 2: Obtain the equivalent network of input or output impedance by numerical calculation method, see attached drawings 2 to 5, wherein, attached drawing 2 is a schematic diagram of the topology structure of the equivalent network of two parameters input impedance including resistance and capacitance, and attached drawing 3 is A schematic diagram of a two-parameter output impedance equivalent network topology that includes resistors and capacitors. Accompanying drawing 4 is a schematic diagram of a three-parameter input impedance equivalent network topology that includes resistors, capacitors, and inductances. Accompanying drawing 5 is a three-parameter network topology that includes resistors, capacitors, and inductances. Schematic diagram of the parametric output impedance equivalent network topology. In practice, the equivalent network topology is selected according to functional requirements, such as imaginary part absorption, bias access, DC blocking, and harmonic suppression.

Step 3: Under the condition that the topology connection mode of the equivalent network remains unchanged, take the value of the reactive element in the equivalent network as "negative" to construct a "conjugate" network corresponding to the equivalent network, see Figure 6, where , "Negative" capacitance or "negative" inductance, only has numerical significance, and does not represent the actual capacitance or inductance value, and connect the "conjugate" network to the transistor, see Figure 7.

Step 4: Optimizing the "conjugate" network, that is, adjusting the value of each parameter in the "conjugate" network to obtain the best input or output "conjugate" network.

Step 5: "Negative" the reactance element in the optimal input or output "conjugate" network to obtain the optimal input or output equivalent network.

Step 6: Match the optimal input or output equivalent network to the termination impedance. In this embodiment, the termination impedance is a resistor of 50Ω to obtain the optimal matching network. The structure diagram of the input matching network matching the best input equivalent network to the termination impedance; Figure 9 is the interstage matching network between the best input equivalent network of the latter stage transistor and the best output equivalent network of the former stage transistor Schematic diagram of the structure; FIG. 10 is a schematic diagram of the structure of the output matching network for the best output equivalent network matching to the termination impedance. Connect the best matching network with the transistor to complete the design of the amplifier, see Figure 1. In this embodiment, referring to FIG. 11 , in the final schematic diagram of the two-stage cascaded amplifier, TL1-TL12 are microstrip lines, and capacitors except C5-C8 are used as bypass capacitors, and other capacitors are involved in matching.

Wherein, the transistor may include a bare die, a packaged die, a pre-matched die, or a die with a feedback element at the source, gate or drain.

The final two-pole cascaded amplifier is directly simulated in ADS without any tuning optimization, and the small-signal S-parameter curve shown in Figure 12 can be obtained. It can be seen from the simulation result diagram that the example two-stage amplifier designed by the method disclosed in the present invention has obtained very good results almost without cumbersome tuning and optimization, the bandwidth exceeds the expected 4GHz (8~12GHz), and the gain flatness is very good Well, the frequency at the middle point m10 is 7.000GHz, and the dB(S(2,1)) is 23.041, and the frequency at the point m15 is 12.50GHz, and the dB(S(1,1)) is 21.224.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (8)

1. a design method of microwave amplifier, is characterized in that, comprises the following steps: Fitting the input or output impedance of the transistor over the frequency range of interest; Obtaining the equivalent network of the input or output impedance by numerical calculation method; constructing a "conjugate" network corresponding to the equivalent network, and connecting the "conjugate" network to the transistor; Optimizing the "conjugate" network by adjusting the value of each parameter in the "conjugate" network to obtain the best input or output "conjugate" network; The optimal input or output equivalent network is obtained by taking the reactive element in the optimal input or output "conjugate" network as "negative"; Matching the optimal input or output equivalent network to the termination impedance to obtain the optimal input or output matching network; connecting the optimal input or output matching network to a transistor to complete the design of the amplifier; in, The "conjugate" network of the equivalent network is obtained by taking "negative" values of the reactance elements in the equivalent network under the condition that the topology connection mode of the equivalent network remains unchanged. 2. The design method according to claim 1, characterized in that, when the amplifier is a multi-stage amplifier, it also includes an inter-stage optimal matching network, and the inter-stage optimal matching network is to optimize the latter stage The input matching network is matched to the best output matching network obtained from the previous stage. 3. The design method according to claim 1, wherein the input or output impedance of the fitting transistor in the target frequency range comprises the following steps: Use EDA tools to obtain the input or output impedance of the transistor at different frequencies; A multiparameter equivalent network is used to fit the input or output impedance of a transistor over the frequency range of interest. 4. The design method according to claim 3, wherein the multi-parameter equivalent network includes resistance and reactance elements. 5. The design method according to claim 4, wherein the reactance element comprises a capacitor. 6. The design method according to claim 5, wherein the reactance element further comprises an inductor. 7. The design method according to claim 1, characterized in that the optimal input or output equivalent network is obtained in the following manner: under the condition that the topological connection mode remains unchanged, in the optimal input or output " The reactive elements in the "conjugate" network are "negative" in value to obtain the optimal input or output equivalent network. 8. The design method according to claim 1, wherein the transistor comprises a bare die, or a packaged die, or a pre-matched die, or a source, gate or drain Very die with feedback elements.