CN102738248B - Optoelectronic device and method for manufacturing thereof - Google Patents
Optoelectronic device and method for manufacturing thereof Download PDFInfo
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- CN102738248B CN102738248B CN201110098663.8A CN201110098663A CN102738248B CN 102738248 B CN102738248 B CN 102738248B CN 201110098663 A CN201110098663 A CN 201110098663A CN 102738248 B CN102738248 B CN 102738248B
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Abstract
The invention provides an optoelectronic device and a method for manufacturing thereof. The optoelectronic device comprises a semiconductor structure combination, a first surface passivation layer formed on an upper surface of the semiconductor structure combination, and a second surface passivation layer formed on the first surface passivation layer. The semiconductor structure combination comprises at least a p-n junction. And especially, interfacial state density of the first surface passivation layer is smaller than that of the second surface passivation layer, and a fixed oxide charge value of the second surface passivation layer is larger than that of the first surface passivation layer.
Description
One, technical field
The invention provides a kind of photoelectric subassembly (optoelectronic device) and manufacture method thereof, such as, the photoelectric subassemblys such as optical detector (photo-detector) or solar cell (solar cell).Further, especially, the invention relates to photoelectric subassembly and manufacture method thereof that one has high-photoelectric transformation efficiency.
Two, background technology
Along with developing rapidly of opto-electronics, various photoelectric subassembly, as light-emitting diode (light-emitting diode), laser diode (laser diode), optical detector and solar cell etc., be widely used in every field.Along with the progress of correlation technique, user is also more and more higher for the requirement of the performance such as luminous efficiency or photoelectric conversion efficiency of photoelectric subassembly.
Generally speaking, form passivation layer (passivation layer) on the surface of photoelectric subassembly, considerably can promote the properties of photoelectric subassembly, such as, luminous efficiency or photoelectric conversion efficiency.For silicon wafer solar cell, the silicon wafer solar cell with high efficiency traditionally can using thermal oxide layer (thermal oxide layer) as surface passivation layer.Its manufacture method is that Silicon Wafer is at high temperature passed into oxygen, makes the surface of Silicon Wafer oxidation occur, to produce silicon dioxide passivation layer.The surface passivation layer be formed on silicon wafer solar cell can provide surface passivation effect, and then promotes the photoelectric conversion efficiency of silicon wafer solar cell.
But the passivation layer formed in the conventional way usually has that THICKNESS CONTROL is not good, surface coverage scarce capacity or defect concentration cross the shortcomings such as high.The passivation layer of this type of bad, for the lifting of photoelectric subassembly properties, can't be very helpful.
In addition, generally the process temperatures of passivation layer is formed often up to hundreds of degree Celsius even more than 1000 DEG C on photoelectric subassembly surface.Too high process temperatures may destroy the structure that photoelectric subassembly surface has been made, and may cause the easy fault of equipment or damage, and then reduces processing procedure reliability and the appropriate rate of equipment.
Therefore, the category of the present invention is to provide a kind of photoelectric subassembly and manufacture method thereof, to solve the problem.
Three, summary of the invention
According to one of the present invention one preferred embodiment photoelectric subassembly, it comprises semiconductor structure combination, a first surface passivation layer and a second surface passivation layer.This semiconductor structure combination comprises at least one p-n junction (p-n junction), and has a upper surface.These first surface passivation series of strata are formed with the upper surface covering this semiconductor structure combination.This first surface passivation layer has one first interface defect density (interfacial state density, Dit) and one first fixing Oxide trapped charge (fixed oxide charge, Qf).These second surface passivation series of strata are formed to cover this first surface passivation layer.This second surface passivation layer has a second contact surface defect concentration and one second fixing Oxide trapped charge.Especially, this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
In a specific embodiment, this semiconductor structure combination and comprise a N-shaped state region, and this N-shaped state region provides this upper surface.Further, this first surface passivation layer provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer is positive charge.
In another specific embodiment, this semiconductor structure combination and comprise a p-type state region, and this p-type state region provides this upper surface.Further, this first surface passivation layer provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer is negative electrical charge.
In a specific embodiment, this semiconductor structure combination has a plurality of nano-pillar structure on this upper surface.Because ald processing procedure (atomic layer deposition) has excellent three-dimensional coverage degree, therefore these first surface passivation series of strata deposit by one first ald processing procedure to cover this plurality of nano-pillar structure on this upper surface.Further, these second surface passivation series of strata deposit by one second ald processing procedure to cover this first surface passivation layer.
One the 3rd surface passivation layer and one the 4th surface passivation layer is comprised further according to the photoelectric subassembly of another preferred embodiment of the present invention.This semiconductor structure combination and there is a lower surface.3rd surface passivation series of strata are formed with this lower surface covering this semiconductor structure combination.3rd surface passivation layer has one the 3rd interface defect density and one the 3rd fixing Oxide trapped charge.4th surface passivation series of strata are formed to cover the 3rd surface passivation layer.4th surface passivation layer has one the 4th interface defect density and one the 4th fixing Oxide trapped charge.Especially, the 3rd interface defect density is less than the 4th interface defect density, and the 4th fixing Oxide trapped charge value is greater than the 3rd fixing Oxide trapped charge value.
Manufacturing the method for a photoelectric subassembly according to the one of the present invention one preferred embodiment, first, is form semiconductor structure combination.This semiconductor structure combination comprises at least one p-n junction, and has a upper surface.Then, form a first surface passivation layer and to be covered on this semiconductor structure combination on the surface according to manufacturer's genealogy of law of the present invention, wherein this first surface passivation layer has one first interface defect density and one first fixing Oxide trapped charge.Finally, form a second surface passivation layer and be covered on this first surface passivation layer according to manufacturer's genealogy of law of the present invention, wherein this second surface passivation layer has a second contact surface defect concentration and one second fixing Oxide trapped charge.Especially, this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
In a specific embodiment, this first surface passivation layer, in being formed on this semiconductor structure combination on the surface, carries out an annealing in process under lying in an annealing temperature further, to reduce the first interface defect density of this first surface passivation layer.
Compare with prior art, effectively can promote the efficiency of photoelectric subassembly according to the photoelectric subassembly of the present invention and manufacture method thereof.
Advantage about the present invention can be further understood by following detailed Description Of The Invention and institute's accompanying drawings with spirit.
Four, accompanying drawing explanation
Fig. 1 system schematically illustrates the photoelectric subassembly 1 according to one of the present invention preferred embodiment.
Positive and negative charge is contained for the schematic diagram that in photoelectric subassembly, p-type and n-type region impacted in Fig. 2 system surface passivation layer.
Fig. 3 to Fig. 5 system schematically illustrates the method for the manufacture photoelectric subassembly 1 as shown in Figure 1 according to one of the present invention preferred embodiment.
Fig. 6 to Fig. 7 system schematically illustrates the method for the manufacture photoelectric subassembly 1 as shown in Figure 1 according to another preferred embodiment of the present invention.
Primary clustering symbol description:
1: photoelectric subassembly 10: semiconductor structure combination
102:p-n junction 104: upper surface
106: lower surface 12: first surface passivation layer
14: second surface passivation layer 16: the three surface passivation layer
18: the four surface passivation layers
Five, embodiment
The preferred embodiment of the present invention below will be described in detail in detail, use the feature, spirit and the advantage that absolutely prove the present invention.
Refer to Fig. 1, Fig. 1 system schematically illustrates the photoelectric subassembly 1 according to one of the present invention preferred embodiment with cross sectional view.In practical application, can be solar cell or optical detector according to the photoelectric subassembly 1 of the present invention.
As shown in Figure 1, semiconductor structure combination 10, one first surface passivation layer 12 and a second surface passivation layer 14 is comprised according to the photoelectric subassembly 1 of the present invention.This semiconductor structure combination 10 comprises at least one p-n junction 102, and has a upper surface 104.A p-n junction 102 is only schematically shown in Fig. 1.
This first surface passivation layer 12 is formed with the upper surface covering this semiconductor structure combination.This first surface passivation layer 12 has one first interface defect density (Dit) and one first fixing Oxide trapped charge (Qf).This second surface passivation layer 14 is formed to cover this first surface passivation layer 12.This second surface passivation layer 14 has a second contact surface defect concentration (Dit) and one second fixing Oxide trapped charge (Qf).Especially, this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
In practical application, according to the photoelectric subassembly 1 of the present invention for silicon wafer solar cell, this upper surface 104 of this semiconductor structure combination 10 is through a surface roughening process (surface texturing), uses the reflectance reduction of sun incident light.
In order to form the good surface passivation layer of quality on the surface in this semiconductor structure combination 10 on surface roughening process, in a specific embodiment, the ald processing procedure (atomic layer deposition, ALD) that the present invention adopts is to form this first surface passivation layer 12 and this second surface passivation layer 14.In the process of ALD thin film deposition, two kinds of chemical reactants (precursor) alternately import in reactive tank, and after being adsorbed in substrate surface, warp is by chemical reaction film former.In ald reaction cycle (ALD cycle) once, first reactant can be adsorbed in whole substrate surfaces, but it can only form at most the absorption of single atomic layer in substrate surface, unnecessary reactant is removed by current-carrying gas (carrier gas).Therefore after the second reactant imports reactive tank, can only single adsorption layer reaction therewith.In other words, an ald reaction cycle is grown up at substrate surface the film of single atomic layer just, and this characteristic is called " certainly limitting film forming " (self-limiting), makes the control precision of film thickness can reach simple layer atomic layer
ald processing procedure of the present invention, also has following advantage: (1) can control the formation of material in atomic level; (2) thickness of film can be controlled more accurately; (3) can large area volume production; (4) the excellent uniformity (uniformity) is had; (5) excellent three-dimensional coverage degree (conformality) is had; (6) without pore space structure; (7) defect concentration is little; And (8) depositing temperature is low ..., etc. process benefit.
In addition, ald processing procedure of the present invention also can be electricity slurry enhancement mode ald (plasma-enhanced atomic layer deposition, PE-ALD) processing procedure.In the middle of the process of deposition oxide film, electricity slurry enhancement mode technique for atomic layer deposition makes electricity consumption starch the oxygen molecule that dissociates, and form oxonium ion as oxidant, therefore can increase the reactivity of chemical reactant, make film density increase, phosphorus content reduces.In addition to the advantages described above, compared to the ald processing procedure of traditional heating type (thermal-mode), electricity starches enhancement mode ald processing procedure can provide following plurality of advantages: (1) electricity slurry enhancement mode technique for atomic layer deposition utilizes electricity to starch the chemical reactant that dissociates, therefore can by chemical composition and the micro-structural changing electricity slurry power control film, reduce impurity density, to promote membrane quality and density; (2) selection of thin-film material and chemical reactant can be increased; (3) can deposit film at a lower temperature, reduce the restriction of temperature on the impact of base material and base material kind; (4) electricity slurry surface treatment (plasma surface treatment) can be implemented on base material, carry out surface cleaning and upgrading.In addition, in the middle of the process of deposited nitride film, electricity slurry enhancement mode technique for atomic layer deposition makes electricity consumption starch the NH that dissociates
3or N
2o gas, forms Nitrogen ion and participates in reaction to form nitride film.
In general CHARGE DISTRIBUTION in surface passivation layer, mainly can be divided into: 1. interface defect density (interfacial statedensity, Dit) electric charge produced, 2. fixing Oxide trapped charge (fixed oxide charge, Qf), 3. oxide layer falls into and catches electric charge (oxide trapped charge, and 4. removable electric charges (mobile charge, Qm) Qot).Hereby be described below:
Interface defect density (Dit): for silicon wafer solar cell, interface defect density is positioned at the interface of silicon substrate and oxide layer.Main reason is that the periodicity of silicon crystal disappears in interface, caused because lattice is discontinuous, can produce interface energy rank being with in (bandgap) of Si.Usually anneal under hydrogeneous atmosphere, effectively can suppress the density on interface energy rank.
Fixing Oxide trapped charge (Qf): be distributed in oxide layer close to interface part.The temperature that oxide layer is grown up and annealing conditions can affect the size of Qf.
Oxide layer falls into and catches electric charge (Qot): be distributed in whole oxide layer, cause primarily of oxide layer internal flaw.Qot can be reduced by the mode of annealing.
Removable electric charge (Qm): alkali metal ion, as sodium, potassium etc., under the operation of high temperature or high pressure, can move back and forth in oxide layer, and the phenomenon causing capacitance-voltage curve to have displacement produces.Therefore must avoid introducing the metal ion produced pollution by process materials or environment.
Wherein the electric charge that produces of interface defect density (Dit) and fixing Oxide trapped charge (Qf) are the topmost contributors of electric charge in surface passivation layer.
Refer to table.Table one is for using hot type (thermal-mode) technique for atomic layer deposition growth Al
2o
3, HfO
2, ZrO
2, with make the Al of electricity consumption slurry type (plasma-mode) technique for atomic layer deposition growth
2o
3, before annealing (as-deposited) with via (forming-gas annealing) film afterwards of annealing under reducing atmosphere, the size of itself Qf and Dit.Wherein q=1.60 × 10
-19coulomb represents electron charge.
Table one
| Q f(q·cm -2) | Hot type Al 2O 3 | Electricity slurry type Al 2O 3 | Hot type HfO 2 | Hot type ZrO 2 |
| Before annealing | 1.08×10 12 | -4.56×10 12 | 4.5×10 12 | 4.0×10 12 |
| After annealing | 6.98×10 11 | -4.23×10 12 | 3.8×10 12 | 2.3×10 12 |
| D it(eV -1·cm -2) | Hot type Al 2O 3 | Electricity slurry type Al 2O 3 | Hot type HfO 2 | Hot type ZrO 2 |
| Before annealing | 4×10 12 | Very large | 2.5×10 12 | 4×10 12 |
| After annealing | 8×10 11 | 7.3×10 12 | 1.5×10 12 | 1×10 12 |
As shown in Table 1, Oxide trapped charge (Qf) is relatively fixed, hot type Al
2o
3, hot type HfO
2with hot type ZrO
2three kinds of films with electric charge be positive charge, its with the size of the quantity of electric charge be hot type HfO
2> hot type ZrO
2> hot type Al
2o
3.And electric slurry type Al
2o
3with electric charge be negative electrical charge.
Equally as shown in Table 1, interface defect density (Dit) is compared, hot type Al
2o
3film, via after annealing under reducing atmosphere, has minimum interface defect density, and electric slurry type Al
2o
3the interface defect density of film is quite high, even if after annealing under reducing atmosphere, and still cannot effectively low interface defect density (Dit).As for hot type HfO
2with hot type ZrO
2film, both interface defect density (Dit) are quite close after reducing annealing, slightly larger than hot type Al
2o
3interface defect density (Dit) value.
In addition, can be found by table one, under reducing atmosphere after annealing, the numerical value of interface defect density (Dit) can significantly reduce, and the decline that fixing Oxide trapped charge (Qf) only can be small size.It can thus be appreciated that annealing can promote the interface quality of surface passivation layer under reducing atmosphere.
In a specific embodiment, this first surface passivation layer 12 can be Al
2o
3, ZrO
2, HfO
2, SiO
2or La
2o
3deng film.And this second surface passivation layer 14 can be Al
2o
3, ZrO
2, HfO
2, SiO
2, La
2o
3, TiO
2, the film such as AlN, SiN, ZnO or the zinc oxide (ZnO:Al) mixing aluminium.
In a specific embodiment, this semiconductor structure combination 10 and comprise a N-shaped state region, and this N-shaped state region provides this upper surface 104.Especially, this first surface passivation layer 12 provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer 14 is positive charge.
In another specific embodiment, this semiconductor structure combination 10 and comprise a p-type state region, and this p-type state region provides this upper surface 104.Especially, this first surface passivation layer 12 provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer 14 is negative electrical charge.
For silicon wafer solar cell, surface passivation layer with electric charge can affect the efficiency of solar cell, this effect is called field effect surface passivation (field-effect surface passivation).Positive and negative charge is contained for photoelectric subassembly, the schematic diagram that namely in silicon wafer solar cell, p-type and n-type region impacted in Fig. 2 system surface passivation layer.As shown in Figure 2, if with positive charge (as Fig. 2 left side) in surface passivation layer, positive charge can repel the minority carrier electricity hole of n+ emitter-base bandgap grading, the probability making carrier that compound (recombination) occur at interface declines to a great extent, and reaches the effect increasing the minority carrier lifetime; If with negative electrical charge (on the right of Fig. 2) in film, negative electrical charge can repel the minority carrier electronics of p-type substrate, and the probability making carrier that compound occur at interface declines to a great extent, and therefore can increase the minority carrier lifetime.It can thus be appreciated that, if positively charged at the surface passivation layer at n+ emitter-base bandgap grading place, if or electronegative at the surface passivation layer of p-type substrate back, the efficiency of silicon wafer solar cell can be increased.Therefore, in the selection of surface passivation layer material, positively charged film of must growing up on n+ emitter-base bandgap grading surface, on the other hand, electronegative film that p-type substrate must be grown up, just can reach best surface passivation effect.
In a specific embodiment, this semiconductor structure combination 10 has a plurality of nano-pillar structure on this upper surface 104, incident for sun light reflectance is more reduced by this.But this semiconductor structure combination 10 has the upper surface 104 of plurality of nanostructures, the depth-to-width ratio of its surface profile is significantly increase compared with the depth-to-width ratio of the surface profile on the surface through general roughening process.So the ald processing procedure with excellent three-dimensional coverage degree must be utilized to form this first surface passivation layer 12 and this second surface passivation layer 14.Therefore, this first surface passivation layer 12 is to cover this plurality of nano-pillar structure on this upper surface 104 by one first ald processing procedure deposition.Further, this second surface passivation layer 14 is to cover this first surface passivation layer 12 by one second ald processing procedure deposition.The process temperatures of this first ald processing procedure and this second atomic layer processing procedure is good not destroy the temperature of the surperficial structure made of photoelectric subassembly.
Please again consulting Fig. 1, is schematically be illustrated in Fig. 1 with cross sectional view according to the photoelectric subassembly 1 of another preferred embodiment of the present invention.This semiconductor structure combination 10 and there is a lower surface 106.
As shown in Figure 1, this photoelectric subassembly 1 further 1 the 3rd surface passivation layer 16 and one the 4th surface passivation layer 18.3rd surface passivation layer 16 is formed with this lower surface 106 covering this semiconductor structure combination 10.3rd surface passivation layer 16 has one the 3rd interface defect density and one the 3rd fixing Oxide trapped charge.4th surface passivation layer 18 is formed to cover the 3rd surface passivation layer 16.4th surface passivation layer 18 has one the 4th interface defect density and one the 4th fixing Oxide trapped charge.Especially, the 3rd interface defect density is less than the 4th interface defect density, and the 4th fixing Oxide trapped charge value is greater than the 3rd fixing Oxide trapped charge value.
In a specific embodiment, this semiconductor structure combination 10 and comprise a p-type state region, and this p-type state region provides this lower surface 106.Especially, the 3rd surface passivation layer 16 provides lower interface defect density, and the fixing Oxide trapped charge of the 4th surface passivation layer 18 is negative electrical charge.
In another specific embodiment, this semiconductor structure combination 10 and comprise a N-shaped state region, and this N-shaped state region provides this lower surface 106.Especially, the 3rd surface passivation layer 16 provides lower interface defect density, and the fixing Oxide trapped charge of the 4th surface passivation layer 18 is positive charge.
Refer to Fig. 3 to Fig. 5, these graphic systems schematically illustrate the method for the manufacture photoelectric subassembly 1 as shown in Figure 1 according to one of the present invention preferred embodiment with cross sectional view.
As shown in Figure 3, according to the method for this photoelectric subassembly 1 of manufacture of the preferred embodiment of the present invention, first, be form semiconductor structure combination 10.This semiconductor structure combination 10 comprises at least one p-n junction 102, and has a upper surface 104.
Then, as shown in Figure 4, form a first surface passivation layer 12 according to manufacturer's genealogy of law of the present invention and be covered on the upper surface 104 of this semiconductor structure combination 10, wherein this first surface passivation layer 12 has one first interface defect density and one first fixing Oxide trapped charge.
Finally, as shown in Figure 5, form a second surface passivation layer 14 and be covered on this first surface passivation layer 12 according to manufacturer's genealogy of law of the present invention, wherein this second surface passivation layer 14 has a second contact surface defect concentration and one second fixing Oxide trapped charge.Especially, this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
In a specific embodiment, this first surface passivation layer 12 on the upper surface 104 being formed in this semiconductor structure combination 10 after, carry out an annealing in process under lying in a temperature further, to reduce the first interface defect density of this first surface passivation layer 12.
In a specific embodiment, this semiconductor structure combination 10 and comprise a N-shaped state region, this N-shaped state region provides this upper surface 104.This first surface passivation layer 12 provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer 14 is positive charge.
In another specific embodiment, this semiconductor structure combination 10 and comprise a p-type state region, this p-type state region provides this upper surface 104.This first surface passivation layer 12 provides lower interface defect density, and the fixing Oxide trapped charge of this second surface passivation layer 14 is negative electrical charge.
In a specific embodiment, this semiconductor structure combination 10 has a plurality of nano-pillar structure on this upper surface 104, incident for sun light reflectance is more reduced by this.Because ald processing procedure has excellent three-dimensional coverage degree, therefore this first surface passivation layer 12 is to cover this plurality of nano-pillar structure on this upper surface 104 by one first ald processing procedure deposition.And this second surface passivation layer 14 is to cover this first surface passivation layer 12 by one second ald processing procedure.
In a specific embodiment, this first surface passivation layer 12 can be Al
2o
3, ZrO
2, HfO
2, SiO
2or La
2o
3deng film.And this second surface passivation layer 14 can be Al
2o
3, ZrO
2, HfO
2, SiO
2, La
2o
3, TiO
2, the film such as AlN, SiN, ZnO or the zinc oxide (ZnO:Al) mixing aluminium.
In a case, to make silicon wafer solar cell, according to the manufacture method of the present invention, first, be one of Silicon Wafer upper surface done a surface roughening process or make a plurality of nano-pillar structure.Then, lie according to the manufacture method of the present invention and use fabrography or evaporation coating technique plated aluminum as back electrode relative to one of this upper surface back side.Then, annealing in process is carried out to make back surface field (Back surface field) structure according to the manufacture method of the present invention.Then, a front electrode is made by fabrography in this upper surface according to manufacturer's genealogy of law of the present invention.Then, form a first surface passivation layer according to manufacturer's genealogy of law of the present invention by ald processing procedure to be covered on this upper surface.Then, annealing in process is carried out for this first passivation layer under lying in an annealing temperature according to the manufacture method of the present invention.Then, form a second surface passivation layer according to manufacturer's genealogy of law of the present invention by ald processing procedure to be covered on this first surface passivation layer.
Refer to Fig. 6 to Fig. 7, to be schematically illustrated in cross sectional view according to the method system of the manufacture photoelectric subassembly 1 as shown in Figure 1 of another preferred embodiment of the present invention that these are graphic.
As shown in Figure 6, according to the method for this photoelectric subassembly 1 of manufacture of another preferred embodiment of the present invention, further, be formation 1 the 3rd surface passivation layer 16 and be covered on this lower surface 106 of this semiconductor structure combination 10, wherein the 3rd surface passivation layer 16 has one the 3rd interface defect density and one the 3rd fixing Oxide trapped charge.
Finally, as shown in Figure 7, method system according to this photoelectric subassembly 1 of manufacture of another preferred embodiment of the present invention forms one the 4th surface passivation layer 18 and is covered on the 3rd surface passivation layer 16, and wherein the 4th surface passivation layer 18 has one the 4th interface defect density and one the 4th fixing Oxide trapped charge.Especially, the 3rd interface defect density is less than the 4th interface defect density, and the 4th fixing Oxide trapped charge value is greater than the 3rd fixing Oxide trapped charge value.
In a specific embodiment, this semiconductor structure combination 10 and comprise a p-type state region, this p-type state region provides this lower surface 106.Especially, the 3rd surface passivation layer 16 provides lower interface defect density, and the fixing Oxide trapped charge of the 4th surface passivation layer 18 is negative electrical charge.
In another specific embodiment, this semiconductor structure combination 10 and comprise a N-shaped state region, and this N-shaped state region provides this lower surface 106.Especially, the 3rd surface passivation layer 16 provides lower interface defect density, and the fixing Oxide trapped charge of the 4th surface passivation layer 18 is positive charge.
In sum, compared to prior art, the efficiency of photoelectric subassembly effectively can be promoted according to the photoelectric subassembly of the present invention and manufacture method thereof.
By the detailed description of above preferred embodiment, it is desirable to clearly to describe the feature of the present invention and spirit, and not limited with the above-mentioned disclosed category of preferred embodiment to the present invention.On the contrary, its objective is and wish contain in the category being arranged in the scope of the claims of the present invention institute wish application of various change and tool equality.Therefore, the present invention the category of the scope of the claims applied for should do the broadest explanation, with the arrangement causing it to contain all possible change and tool equality according to above-mentioned explanation.
Claims (15)
1. a photoelectric subassembly, comprises:
Semiconductor structure combines, and this semiconductor structure combination comprises at least one p-n junction (p-n junction) and has a upper surface;
The one first surface passivation layer formed with the method for ald, these first surface passivation series of strata are formed with this upper surface covering this semiconductor structure combination, this first surface passivation layer has one first interface defect density (interfacial state density, D
it) fix Oxide trapped charge (fixed oxide charge, Q with one first
f); And
The one second surface passivation layer formed with the method for ald, these second surface passivation series of strata are formed to cover this first surface passivation layer, and this second surface passivation layer has a second contact surface defect concentration and one second fixing Oxide trapped charge;
Wherein, this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
2. photoelectric subassembly as claimed in claim 1, wherein this semiconductor structure combination and comprise a N-shaped state region, this N-shaped state region provides this upper surface, and this second surface passivation layer has positive charge.
3. photoelectric subassembly as claimed in claim 1, wherein this semiconductor structure combination and comprise a p-type state region, this p-type state region provides this upper surface, and this second surface passivation layer has negative electrical charge.
4. photoelectric subassembly as claimed in claim 1, wherein this semiconductor structure combination has a plurality of nano-pillar structure on this upper surface, these first surface passivation series of strata deposit by one first ald (atomic layer deposition) processing procedure to cover this plurality of nano-pillar structure on this upper surface, and these second surface passivation series of strata deposit by one second ald processing procedure to cover this first surface passivation layer.
5. photoelectric subassembly as claimed in claim 1, this semiconductor structure combination and there is a lower surface, this photoelectric subassembly comprises further:
One the 3rd surface passivation layer, the 3rd surface passivation series of strata are formed with this lower surface covering this semiconductor structure combination, and the 3rd surface passivation layer has one the 3rd interface defect density and one the 3rd fixing Oxide trapped charge; And
One the 4th surface passivation layer, the 4th surface passivation series of strata are formed to cover the 3rd surface passivation layer, and the 4th surface passivation layer has one the 4th interface defect density and one the 4th fixing Oxide trapped charge;
Wherein the 3rd interface defect density is less than the 4th interface defect density, and the 4th fixing Oxide trapped charge value is greater than the 3rd fixing Oxide trapped charge value.
6. photoelectric subassembly as claimed in claim 5, wherein this semiconductor structure combination and comprise a p-type state region, this p-type state region provides this lower surface, and the 4th surface passivation layer has negative electrical charge.
7. photoelectric subassembly as claimed in claim 5, wherein this semiconductor structure combination and comprise a N-shaped state region, this N-shaped state region provides this lower surface, and the 4th surface passivation layer has positive charge.
8. the manufacture method of photoelectric subassembly as claimed in claim 1, comprises the following step:
Formation semiconductor structure combines, and this semiconductor structure combination comprises at least one p-n junction (p-n junction) and has a upper surface;
Form a first surface passivation layer with the method for ald and be covered on this upper surface of this semiconductor structure combination, wherein this first surface passivation layer has one first interface defect density (interfacial state density, D
it) fix Oxide trapped charge (fixed oxide charge, Q with one first
f); And
Form a second surface passivation layer with the method for ald and be covered on this first surface passivation layer, wherein this second surface passivation layer has a second contact surface defect concentration and one second fixing Oxide trapped charge;
Wherein this first interface defect density is less than this second contact surface defect concentration, and this second fixing Oxide trapped charge value is greater than this first fixing Oxide trapped charge value.
9. method as claimed in claim 8, wherein this first surface passivation layer is in being formed on this semiconductor structure combination on the surface, an annealing in process is carried out, to reduce the first interface defect density of this first surface passivation layer under lying in an annealing temperature further.
10. method as claimed in claim 8, wherein this semiconductor structure combination and comprise a N-shaped state region, this N-shaped state region provides this upper surface, and this second surface passivation layer has positive charge.
11. methods as claimed in claim 8, wherein this semiconductor structure combination and comprise a p-type state region, this p-type state region provides this upper surface, and this second surface passivation layer has negative electrical charge.
12. methods as claimed in claim 8, wherein this semiconductor structure combination has a plurality of nano-pillar structure on this upper surface, these first surface passivation series of strata by one first ald (atomic layer deposition) processing procedure deposition to cover this plurality of nano-pillar structure on this upper surface, and these second surface passivation series of strata by one second ald processing procedure to cover this first surface passivation layer.
13. methods as claimed in claim 8, this semiconductor structure combination and there is a lower surface, the method comprises the following step further:
Form one the 3rd surface passivation layer and be covered on this lower surface of this semiconductor structure combination, wherein the 3rd surface passivation layer has one the 3rd interface defect density and one the 3rd fixing Oxide trapped charge; And
Form one the 4th surface passivation layer and be covered on the 3rd surface passivation layer, wherein the 4th surface passivation layer has one the 4th interface defect density and one the 4th fixing Oxide trapped charge;
Wherein the 3rd interface defect density is less than the 4th interface defect density, and the 4th fixing Oxide trapped charge value is greater than the 3rd fixing Oxide trapped charge value.
14. methods as claimed in claim 13, wherein this semiconductor structure combination and comprise a p-type state region, this p-type state region provides this lower surface, and the 4th surface passivation layer has negative electrical charge.
15. methods as claimed in claim 13, wherein this semiconductor structure combination and comprise a N-shaped state region, this N-shaped state region provides this lower surface, and the 4th surface passivation layer has positive charge.
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| CN105633213A (en) * | 2016-02-19 | 2016-06-01 | 安徽旭能光伏电力有限公司 | Surface passivating treatment technology for double-sided glass crystalline silicon solar cell |
| CN109087957A (en) * | 2018-08-08 | 2018-12-25 | 浙江师范大学 | Backside passivation layer is aluminium oxide and the PERC battery of hydrogenated silicon nitride aluminium and preparation method thereof |
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