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CN102723917A - Power amplifier - Google Patents

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CN102723917A
CN102723917A CN2011100779318A CN201110077931A CN102723917A CN 102723917 A CN102723917 A CN 102723917A CN 2011100779318 A CN2011100779318 A CN 2011100779318A CN 201110077931 A CN201110077931 A CN 201110077931A CN 102723917 A CN102723917 A CN 102723917A
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common
transistor
drain
source
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CN102723917B (en
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刘孝辉
龚夺
杨云
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BYD Semiconductor Co Ltd
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BYD Co Ltd
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Abstract

一种功率放大器,包括:共源晶体管、共栅晶体管以及电容,所述共源晶体管的源极连接地信号,所述共源晶体管的栅极用以连接第一偏置电压;所述共栅晶体管的源极与共源晶体管的漏极连接,所述共栅晶体管的栅极用以连接第二偏置电压,所述共栅晶体管的漏极耦合一直流电压源,所述电容连接所述共栅晶体管的栅极和漏极。由于共栅晶体管的栅极和漏极之间连接有一电容,在该栅极和漏极之间形成一高通通路,使该栅极和漏极的压差减小,这样能够使漏极具有一个更大信号摆幅而不会达到栅极和漏极的击穿电压。

Figure 201110077931

A power amplifier, comprising: a common-source transistor, a common-gate transistor and a capacitor, the source of the common-source transistor is connected to a ground signal, and the gate of the common-source transistor is used to connect to a first bias voltage; the common-gate The source of the transistor is connected to the drain of the common-source transistor, the gate of the common-gate transistor is used to connect to the second bias voltage, the drain of the common-gate transistor is coupled to a DC voltage source, and the capacitor is connected to the common The gate and drain of a gate transistor. Since a capacitance is connected between the gate and the drain of the common-gate transistor, a high-pass path is formed between the gate and the drain, so that the voltage difference between the gate and the drain is reduced, so that the drain has a Larger signal swings without reaching gate and drain breakdown voltages.

Figure 201110077931

Description

一种功率放大器a power amplifier

技术领域 technical field

本发明涉及功率器件领域,具体涉及一种功率放大器。 The invention relates to the field of power devices, in particular to a power amplifier.

背景技术 Background technique

在现有技术的MOS功率放大器中,漏极-栅极电压经常高于电源电压的三倍,为防止漏极-栅极击穿,限制了可以使用在此类放大器中的最大电源电压。一种改进此问题的方法是在功率放大器中使用共源共栅结构,该结构一般采用两个晶体管:一个共源管、一个共栅管。但在该常用共源共栅结构中,共栅管的漏极-栅极电压也常高于电源电压的两倍,在电源电压较高时,共栅管的漏极-栅极电压一般也会超出该管的耐压范围。 In prior art MOS power amplifiers, the drain-gate voltage is often three times higher than the supply voltage, which limits the maximum supply voltage that can be used in such amplifiers to prevent drain-gate breakdown. One way to improve this problem is to use a cascode structure in the power amplifier, which generally uses two transistors: a common source transistor and a common gate transistor. However, in this commonly used cascode structure, the drain-gate voltage of the common-gate transistor is often twice as high as the power supply voltage. When the power supply voltage is high, the drain-gate voltage of the common-gate transistor is generally also higher than Will exceed the pressure range of the tube.

图1表示出了两个晶体管的标准共源共栅结构,晶体管M1是共源管,晶体管M2是共栅管,晶体管M1的漏极和晶体管M2的源极连接在一起。为了方便说明,在下文中用字母D、G、S指代一个给定晶体管的漏极、栅极、源极,例如G1指的是晶体管M1的栅极、D2指的是晶体管M2的漏极等等。图2表示了一个常规的共源共栅结构的功率放大器,晶体管M1为共源管,晶体管M2为共栅管。直流电压Vgg1通过一个电阻Rg1供给栅极G1为晶体管M1提供直流偏置,该直流偏置可以根据实际需要选取任意值;直流电压Vgg2通过电阻Rg2供给栅极G2为晶体管M2提供直流偏置,该值也可以根据实际需要选取任意值;射频输入信号RFin通过电容Cin被耦合到G1,G2通过电阻Rg2连接到射频地,但本身并不是射频地,因此G2处的电压可以具有射频摆幅,只要D2处射频信号具有全摆幅,功率放大器就可以提供高的输出功率;如果在源电压较高时,共栅管的漏极-栅极电压一般也会超出该管的耐压范围。 FIG. 1 shows a standard cascode structure of two transistors, the transistor M1 is a common source transistor, the transistor M2 is a common gate transistor, and the drain of the transistor M1 and the source of the transistor M2 are connected together. For the convenience of description, the letters D, G, and S are used hereinafter to refer to the drain, gate, and source of a given transistor, for example, G1 refers to the gate of transistor M1, D2 refers to the drain of transistor M2, etc. wait. FIG. 2 shows a conventional power amplifier with a cascode structure, the transistor M1 is a cascode transistor, and the transistor M2 is a cascode transistor. The DC voltage Vgg1 is supplied to the gate G1 through a resistor Rg1 to provide a DC bias for the transistor M1, and the DC bias can be selected according to actual needs; the DC voltage Vgg2 is supplied to the gate G2 through a resistor Rg2 to provide a DC bias for the transistor M2. The value can also be selected according to actual needs; RF input signal RFin is coupled to G1 through capacitor Cin, G2 is connected to RF ground through resistor Rg2, but it is not RF ground itself, so the voltage at G2 can have RF swing, as long as The RF signal at D2 has a full swing, and the power amplifier can provide high output power; if the source voltage is high, the drain-gate voltage of the common-gate tube will generally exceed the withstand voltage range of the tube.

发明内容 Contents of the invention

本发明为解决现有技术功率放大器中共栅管的漏极-栅极电压会超出该管耐压范围的问题。 The invention aims to solve the problem that the drain-gate voltage of the common grid tube of the power amplifier in the prior art will exceed the withstand voltage range of the tube.

为解决上述技术问题,本发明提供如下技术方案: In order to solve the above technical problems, the present invention provides the following technical solutions:

一种功率放大器,包括:共源晶体管、共栅晶体管以及电容,所述共源晶体管的源极连接地信号,所述共源晶体管的栅极用以连接第一偏置电压;所述共栅晶体管的源极与共源晶体管的漏极连接,所述共栅晶体管的栅极用以连接第二偏置电压,所述共栅晶体管的漏极用以连接一直流电压源,所述电容连接所述共栅晶体管的栅极和漏极。 A power amplifier, comprising: a common-source transistor, a common-gate transistor and a capacitor, the source of the common-source transistor is connected to a ground signal, and the gate of the common-source transistor is used to connect to a first bias voltage; the common-gate The source of the transistor is connected to the drain of the common-source transistor, the gate of the common-gate transistor is used for connecting the second bias voltage, the drain of the common-gate transistor is used for connecting a DC voltage source, and the capacitor is connected to the The gate and drain of the common gate transistor.

与现有技术相比,本发明具有如下有益效果:本发明提供的一种功率放大器,由于共栅晶体管的栅极和漏极之间连接有一电容,在该栅极和漏极之间形成一高通通路,使该栅极和漏极的压差减小,这样能够使漏极具有一个更大信号摆幅而不会达到栅极和漏极的击穿电压。 Compared with the prior art, the present invention has the following beneficial effects: in a power amplifier provided by the present invention, since a capacitance is connected between the gate and the drain of the common-gate transistor, a capacitor is formed between the gate and the drain. The high-pass path reduces the voltage difference between the gate and the drain, which enables the drain to have a larger signal swing without reaching the breakdown voltage of the gate and drain.

附图说明 Description of drawings

图1是两个晶体管的共源共栅结构示意图。 FIG. 1 is a schematic diagram of a cascode structure of two transistors.

图2是现有技术共源共栅结构的功率放大器。 Fig. 2 is a power amplifier with cascode structure in the prior art.

图3是本发明实施例两个晶体管的共源共栅结构示意图。 FIG. 3 is a schematic diagram of a cascode structure of two transistors according to an embodiment of the present invention.

图4是本发明第一实施例共源共栅结构的功率放大器。 FIG. 4 is a power amplifier with cascode structure according to the first embodiment of the present invention.

图5是本发明第二实施例共源共栅结构的功率放大器。 FIG. 5 is a power amplifier with cascode structure according to the second embodiment of the present invention.

具体实施方式 Detailed ways

为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 In order to make the technical problems, technical solutions and beneficial effects solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

图3是本发明实施例两个晶体管的共源共栅结构示意图;该共源共栅结构包括共源晶体管M1、共栅晶体管M2以及电容Cb,所述共栅晶体管M2的源极S2与共源晶体管M1的漏极D1连接,所述电容Cb连接所述共栅晶体管M2的栅极G2和漏极D2;由于共栅晶体管M2的栅极G2和漏极D2之间连接有一电容,在该栅极G2和漏极D2之间形成一高通通路,使该栅极G2和漏极D2的压差减小,这样能够使漏极具有一个更大信号摆幅而不会达到栅极和漏极的击穿电压。 3 is a schematic diagram of a cascode structure of two transistors in an embodiment of the present invention; the cascode structure includes a common source transistor M1, a common gate transistor M2, and a capacitor Cb, and the source S2 of the common gate transistor M2 is connected to the common source The drain D1 of the transistor M1 is connected, and the capacitor Cb is connected to the gate G2 and the drain D2 of the common-gate transistor M2; since a capacitor is connected between the gate G2 and the drain D2 of the common-gate transistor M2, the gate A high-pass path is formed between the gate G2 and the drain D2, so that the voltage difference between the gate G2 and the drain D2 is reduced, so that the drain has a larger signal swing without reaching the gap between the gate and the drain. breakdown voltage.

图4是本发明第一实施例共源共栅结构的功率放大器;在图3共源共栅结构的基础上,所述共源晶体管M1的栅极G1设置有第一偏置电压Vgg1;所述共栅晶体管M2的栅极G2设置有第二偏置电压Vgg2,所述共栅晶体管M2的漏极D2耦合一直流电压源VDD,所述电容Cb连接所述共栅晶体管M2的栅极G2和漏极D2;所述共源晶体管M1的源极S1连接地信号。由于共栅晶体管M2的栅极G2和漏极D2之间连接有一电容Cb,在该栅极G2和漏极D2之间形成一高通通路,使该栅极G2和漏极D2的压差减小,这样能够使在漏极具有一个更大信号摆幅而不会达到栅极和漏极的击穿电压。 FIG. 4 is a power amplifier with a cascode structure according to the first embodiment of the present invention; on the basis of the cascode structure in FIG. 3 , the gate G1 of the common source transistor M1 is provided with a first bias voltage Vgg1; The gate G2 of the common-gate transistor M2 is provided with a second bias voltage Vgg2, the drain D2 of the common-gate transistor M2 is coupled to a DC voltage source VDD, and the capacitor Cb is connected to the gate G2 of the common-gate transistor M2 and the drain D2; the source S1 of the common source transistor M1 is connected to the ground signal. Since a capacitance Cb is connected between the gate G2 and the drain D2 of the common-gate transistor M2, a high-pass path is formed between the gate G2 and the drain D2, so that the voltage difference between the gate G2 and the drain D2 is reduced , which enables a larger signal swing at the drain without reaching the breakdown voltage of the gate and drain.

本实施例中,共源晶体管M1和共栅M2晶体管均是NMOS管,其他实施例中也可以是其他晶体管,此处不再赘述。该实施例中,共源晶体管M1的栅极G1电极通过一耦合电容Cin被耦合到射频信号输入端RFin;共源晶体管M1的栅极G1通过第一偏置电阻Rg1连接第一偏置电压Vgg1;共栅晶体管M2的漏极D2通过一漏极电感Ldc连接直流电压源VDD;共栅晶体管M2的栅极G2通过第二偏置电阻Rb连接第二偏置电压Vgg2。 In this embodiment, both the common-source transistor M1 and the common-gate M2 transistor are NMOS transistors, and may be other transistors in other embodiments, which will not be repeated here. In this embodiment, the gate G1 electrode of the common source transistor M1 is coupled to the radio frequency signal input terminal RFin through a coupling capacitor Cin; the gate G1 of the common source transistor M1 is connected to the first bias voltage Vgg1 through the first bias resistor Rg1 The drain D2 of the common-gate transistor M2 is connected to the DC voltage source VDD through a drain inductance Ldc; the gate G2 of the common-gate transistor M2 is connected to the second bias voltage Vgg2 through the second bias resistor Rb.

以下详述其工作原理,由于第一偏置电压Vgg1和第二偏置电压Vgg2是直流偏压,故相对输入的射频信号也是射频地。由于共栅晶体管M2的栅极G2-漏极D2之间接的是电容Cb;所以对直流而言,共栅晶体管M2的栅极G2的直流偏压Vgg2是通过外部引脚独立外加的任意值,共栅晶体管M2的漏极D2的直流电压为VDD,两者之间没有联系。对射频而言,在共栅晶体管M2的漏极D2处的射频摆幅被Cb-Rb串联连接的高通特性消弱,根据需要可以合理选择Cb与Rb的值,便可以在共栅晶体管M2的栅极G2端得到一个射频摆幅,从而使共栅晶体管M2的栅极G2-漏极D2的压差减小,这样能够使在共栅晶体管M2的漏极D2处具有一个更大信号摆幅,而不会达到共栅晶体管M2的栅极G2-漏极D2的击穿电压。随着共栅晶体管M2的漏极D2处电压的增加,该晶体管的栅极G2的电压也增加,增加的量由电容Cb与第二偏置电阻Rb的值决定;并且共栅晶体管M2的源极S2的电压也增加,这样,在共源晶体管M1和共栅晶体管M2的每个栅极-漏极上的电压降的量可以被平衡。当合理选择第二偏置电压Vgg2、电容Cb与第二偏置电阻Rb的值,可以使在共源晶体管M1与共栅晶体管M2的栅极-漏极电压差相等时,获得最佳性能和最大信号摆幅。由于电阻电容的值几乎不会随加在其两端的电压变化而变化,所以无论射频信号的摆幅是多少,功率放大器的输出阻抗不会变化。 The working principle will be described in detail below. Since the first bias voltage Vgg1 and the second bias voltage Vgg2 are DC bias voltages, the corresponding input RF signal is also RF ground. Since the gate G2-drain D2 of the common-gate transistor M2 is connected to the capacitor Cb; so for DC, the DC bias voltage Vgg2 of the gate G2 of the common-gate transistor M2 is an arbitrary value independently applied through an external pin, The DC voltage of the drain D2 of the common-gate transistor M2 is VDD, and there is no connection between the two. For the radio frequency, the radio frequency swing at the drain D2 of the common gate transistor M2 is weakened by the high-pass characteristic of the Cb-Rb series connection, and the values of Cb and Rb can be reasonably selected according to the needs, so that the common gate transistor M2 A radio frequency swing is obtained at the gate G2 terminal, so that the voltage difference between the gate G2-drain D2 of the common-gate transistor M2 is reduced, which enables a larger signal swing at the drain D2 of the common-gate transistor M2 , without reaching the breakdown voltage of the gate G2-drain D2 of the common-gate transistor M2. As the voltage at the drain D2 of the common-gate transistor M2 increases, the voltage at the gate G2 of the transistor also increases by an amount determined by the values of the capacitor Cb and the second bias resistor Rb; and the source of the common-gate transistor M2 The voltage at terminal S2 is also increased so that the amount of voltage drop across each gate-drain of common-source transistor M1 and common-gate transistor M2 can be balanced. When the values of the second bias voltage Vgg2, the capacitor Cb and the second bias resistor Rb are selected reasonably, the gate-drain voltage difference between the common-source transistor M1 and the common-gate transistor M2 can be equal, and the best performance and the maximum signal swing. Since the value of the resistor and capacitor hardly changes with the voltage applied across it, the output impedance of the power amplifier will not change no matter how much the swing of the radio frequency signal is.

图5是本发明第二实施例共源共栅结构的功率放大器;第一偏置电压Vgg1与第二偏置电压Vgg2是直流偏压,故也是射频地,但在实际中提供直流电压的电源或电路的输出阻抗不为零,所以该两处并不是理想的射频地,故可以加强该两处的射频地能力。为了加强共源晶体管M1栅极G1处的射频地,在图4的基础上还包括第一电感L1和第一电容C1,所述第一偏置电阻Rg1、第一电感L1和第一电容C1串联后连接到地信号。为了加强共栅晶体管M2栅极G2处的射频地,在图4的基础上还包括第二电感L2和第二电容C2,所述第二偏置电阻Rb、第二电感L2和第二电容C2串联后连接到地信号。本实施例中共源晶体管M1栅极G1和共栅晶体管M2栅极G2处的射频地均有加强,并使第一电感L1、第一电容C1和第二电感L2、第二电容C2都谐振在射频信号的频率下。 Fig. 5 is a power amplifier with a cascode structure in the second embodiment of the present invention; the first bias voltage Vgg1 and the second bias voltage Vgg2 are DC bias voltages, so they are also radio frequency grounds, but in practice, they are power supplies that provide DC voltages Or the output impedance of the circuit is not zero, so the two places are not ideal radio frequency grounds, so the radio frequency ground capabilities of the two places can be enhanced. In order to strengthen the RF ground at the gate G1 of the common source transistor M1, a first inductor L1 and a first capacitor C1 are also included on the basis of FIG. 4 , the first bias resistor Rg1, the first inductor L1 and the first capacitor C1 Connect to the ground signal after series connection. In order to strengthen the RF ground at the gate G2 of the common-gate transistor M2, a second inductor L2 and a second capacitor C2 are also included on the basis of FIG. Connect to the ground signal after series connection. In this embodiment, the radio frequency grounds at the gate G1 of the common source transistor M1 and the gate G2 of the common gate transistor M2 are strengthened, and the first inductor L1, the first capacitor C1, the second inductor L2, and the second capacitor C2 are all resonated at at the frequency of the radio frequency signal.

本实施例中,放大器输出通过一个匹配网络100耦合到一个负载RL,匹配网络100可以将负载RL的阻抗变换到放大器输出阻抗的共轭阻抗上,以达到功率的最大输出。本发明实施例通过在共栅极晶体管的栅极-漏极之间耦合射频摆幅的方式解决了功率放大器(尤其是E类功放)所面临的漏极-栅极耐压问题。在本发明实施例中,最佳情况是当两个晶体管承受相同的最大漏极-栅极电压时,这意味着可以使用一个更大的电源电压,从而产生更高的输出功率。 In this embodiment, the output of the amplifier is coupled to a load RL through a matching network 100, and the matching network 100 can transform the impedance of the load RL to the conjugate impedance of the output impedance of the amplifier to achieve the maximum power output. The embodiment of the present invention solves the problem of drain-gate withstand voltage faced by power amplifiers (especially class E power amplifiers) by coupling the radio frequency swing between the gate and the drain of the common-gate transistor. In an embodiment of the present invention, the optimum situation is when both transistors experience the same maximum drain-gate voltage, which means that a larger supply voltage can be used, resulting in higher output power.

以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。 The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention should be included in the protection of the present invention. within range.

Claims (8)

1.一种功率放大器,其特征在于,包括:共源晶体管、共栅晶体管以及电容,所述共源晶体管的源极连接地信号,所述共源晶体管的栅极用以连接第一偏置电压;所述共栅晶体管的源极与共源晶体管的漏极连接,所述共栅晶体管的栅极用以连接第二偏置电压,所述共栅晶体管的漏极用以连接一直流电压源,所述电容连接所述共栅晶体管的栅极和漏极。 1. A power amplifier, characterized in that it comprises: a common source transistor, a common gate transistor and a capacitor, the source of the common source transistor is connected to the ground signal, and the gate of the common source transistor is used to connect the first bias Voltage; the source of the common gate transistor is connected to the drain of the common source transistor, the gate of the common gate transistor is used to connect the second bias voltage, and the drain of the common gate transistor is used to connect a DC voltage source , the capacitor is connected to the gate and the drain of the common-gate transistor. 2.根据权利要求1所述的功率放大器,其特征在于,所述共源晶体管和共栅晶体管均是NMOS管。 2. The power amplifier according to claim 1, wherein the common-source transistor and the common-gate transistor are both NMOS transistors. 3.根据权利要求1所述的功率放大器,其特征在于,所述共源晶体管的栅极电极通过一耦合电容被耦合到射频信号输入端。 3. The power amplifier according to claim 1, wherein the gate electrode of the common source transistor is coupled to the radio frequency signal input terminal through a coupling capacitor. 4.根据权利要求1所述的功率放大器,其特征在于,所述共源晶体管的栅极通过第一偏置电阻连接第一偏置电压。 4. The power amplifier according to claim 1, wherein the gate of the common source transistor is connected to a first bias voltage through a first bias resistor. 5.根据权利要求4所述的功率放大器,其特征在于,还包括第一电感和第一电容,所述第一偏置电阻、第一电感和第一电容串联后连接到地信号。 5. The power amplifier according to claim 4, further comprising a first inductor and a first capacitor, the first bias resistor, the first inductor and the first capacitor are connected in series to the ground signal. 6.根据权利要求1所述的功率放大器,其特征在于,所述共栅晶体管的漏极通过一漏极电感连接所述直流电压源。 6. The power amplifier according to claim 1, wherein the drain of the common-gate transistor is connected to the DC voltage source through a drain inductance. 7.根据权利要求1所述的功率放大器,其特征在于,所述共栅晶体管的栅极通过第二偏置电阻连接第二偏置电压。 7. The power amplifier according to claim 1, wherein the gate of the common-gate transistor is connected to the second bias voltage through a second bias resistor. 8.根据权利要求7所述的功率放大器,其特征在于,还包括第二电感和第二电容,所述第二偏置电阻、第二电感和第二电容串联后连接到地信号。 8. The power amplifier according to claim 7, further comprising a second inductor and a second capacitor, the second bias resistor, the second inductor and the second capacitor are connected in series to the ground signal.
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CN107404291A (en) * 2017-01-13 2017-11-28 上海韦玏微电子有限公司 Biasing circuit and low-noise amplifier
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CN106330109A (en) * 2016-08-31 2017-01-11 中国科学院微电子研究所 Cascode amplifying circuit and power amplifier
CN106330109B (en) * 2016-08-31 2019-02-12 中国科学院微电子研究所 Cascode amplifying circuit and power amplifier
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CN108155880A (en) * 2018-02-22 2018-06-12 北京遥感设备研究所 A kind of novel programmable millimeter wave digital power amplifier
CN113792512A (en) * 2021-08-24 2021-12-14 天津大学 Composite discrete semiconductor transistor
CN113792512B (en) * 2021-08-24 2024-04-05 天津大学 Composite discrete semiconductor transistor
CN114844478A (en) * 2022-05-25 2022-08-02 上海集成电路研发中心有限公司 power amplifier circuit

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