CN102723333B - Non-volatile memory with P+ floating gate electrode and preparation method thereof - Google Patents

Abstract

The invention relates to a non-volatile memory with a P+ floating gate electrode and a preparation method thereof. The upper part of the semiconductor substrate is provided with a memory cell; the memory cell includes a PMOS access transistor, a control capacitor and a programming capacitor; The upper part of the upper part is provided with a number of isolation trenches, and an isolation medium is provided in the isolation trenches to form a domain dielectric area; the PMOS access transistor, control capacitor and programming capacitor in the memory cell are isolated from each other through the domain dielectric area; the first main body of the semiconductor substrate A gate dielectric layer is deposited on the surface, and the gate dielectric layer covers the notch of the isolation trench and covers the first main surface of the semiconductor substrate; the PMOS access transistor and the top corner of the isolation trench on both sides of the control capacitor are provided with P+ The floating gate electrode, the P+ floating gate electrode is located on the gate dielectric layer and corresponds to the top angle of the corresponding isolation trench. The invention is compatible with CMOS logic technology, improves data retention time and improves the use reliability of non-volatile memory.

Description

A kind of non-volatile memory with P+ floating gate electrode and preparation method thereof

technical field

The present invention relates to a kind of non-volatile memory and its preparation method, especially a kind of non-volatile memory with P+ floating gate electrode and its preparation method, specifically a kind of non-volatile memory which can improve data retention time A memory and a preparation method thereof belong to the technical field of integrated circuits.

Background technique

For system-on-chip (SoC) applications, it is the integration of many functional blocks into an integrated circuit. The most commonly used SoCs include a microprocessor or microcontroller, static random access memory (SRAM) modules, nonvolatile memory, and logic blocks for various special functions. However, conventional non-volatile memory processes, which typically use stacked-gate or split-gate memory cells, are not compatible with conventional logic processes.

The non-volatile memory (NVM) process is different from the traditional logic process. The combination of non-volatile memory (NVM) process and traditional logic process will make the process a more complex and expensive combination; since the typical use of non-volatile memory for SoC applications is in relation to the whole The chip size is small, so this approach is not advisable. At the same time, due to the working principle of the existing non-volatile memory, the written data is easily lost, which affects the reliability of use.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a non-volatile memory with P+ floating gate electrodes and a preparation method thereof, which is compact in structure, compatible with CMOS logic technology, improves data retention time, reduces Use cost, improve the use reliability of non-volatile memory.

According to the technical solution provided by the present invention, the non-volatile memory with P+ floating gate electrodes includes a semiconductor substrate, and the upper part of the semiconductor substrate is provided with several memory cells for storage; the memory cells include PMOS access transistors, control capacitors and programming capacitors; the upper part of the semiconductor substrate is provided with a number of isolation trenches, and isolation dielectrics are provided in the isolation trenches to form domain dielectric regions; the PMOS access transistors, control The capacitor and the programming capacitor are isolated from each other by the domain dielectric region; a gate dielectric layer is deposited on the first main surface of the semiconductor substrate, and the gate dielectric layer covers the notch of the isolation trench and covers the first main surface of the semiconductor substrate; PMOS access P+ floating gate electrodes are arranged directly above the top corners of the isolation trenches on both sides of the transistor and the control capacitor, and the P+ floating gate electrodes are located on the gate dielectric layer and correspond to the top corners of the corresponding isolation trenches.

The P+ floating gate electrode is conductive polysilicon of P conductivity type.

A P+ floating gate electrode is arranged directly above the corners of the isolation trenches on both sides of the programming capacitor, and the P+ floating gate electrode corresponds to the corners of the isolation trenches on both sides of the programming capacitor.

The material of the semiconductor substrate includes silicon, and the semiconductor substrate is a P conductivity type substrate or an N conductivity type substrate; when the semiconductor substrate is a P conductivity type substrate, the PMOS access transistor, control capacitor and programming capacitor pass through the P type conductivity type substrate The second N-type region inside and the third N-type region above the second N-type region are isolated from the P-type conductivity type substrate.

A floating gate electrode is provided on the gate dielectric layer, and the floating gate electrode covers and penetrates the corresponding gate dielectric layer above the PMOS access transistor, the control capacitor and the programming capacitor, and side protection layers are deposited on both sides of the floating gate electrode. The protection layer covers the sidewall of the floating gate electrode; the PMOS access transistor includes a first N-type region and a P-type source region and a P-type drain region located on the upper part of the first N-type region, and the control capacitor includes a P-type region A and the P-type doped region C and the P-type doped region D located in the upper part of the P-type region A; the programming capacitor includes the P-type region B and the P-type doped region E and D located in the upper part of the P-type region B. P-type doped region F; P-type doped region C, P-type doped region D, P-type doped region E, P-type doped region F, P-type source region and P-type drain region and the floating above The gate electrodes correspond to and are in contact with corresponding gate dielectric layers and domain dielectric regions respectively.

The material of the gate dielectric layer includes silicon dioxide; the side protection layer is silicon nitride or silicon dioxide.

The material of the floating gate electrode includes conductive polysilicon of N conductivity type.

A kind of non-volatile memory preparation method with P+ floating gate electrode, the preparation method of described non-volatile memory comprises the steps:

a, providing a semiconductor substrate, the semiconductor substrate comprising a first main surface and a second main surface;

b. Perform the required barrier layer deposition, barrier layer etching and self-aligned ion implantation on the first main surface of the semiconductor substrate to form the required first N-type region and the third N-type region in the semiconductor substrate. region, P-type region A and P-type region B, the first N-type region is located between the P-type region A and the P-type region B, and the third N-type region is located outside the P-type region A and the P-type region B;

c. Perform trench etching in the above-mentioned semiconductor substrate to form a required isolation trench in the semiconductor substrate, and set an isolation medium in the isolation trench to form a domain dielectric region in the semiconductor substrate, the domain dielectric The regions extend downward from the first main surface, and isolate the upper parts of the third N-type region, the P-type region A, the first N-type region, and the P-type region B from each other;

d. Depositing a gate dielectric layer on the corresponding first main surface of the semiconductor substrate, the gate dielectric layer covering the first main surface of the semiconductor substrate;

e. Deposit a floating gate electrode on the first main surface of the above-mentioned semiconductor substrate, the floating gate electrode covers the gate dielectric layer and runs through the corresponding gate above the P-type region A, the first N-type region and the P-type region B on the medium layer;

f. Deposit a fourth barrier layer on the gate dielectric layer, and selectively mask and etch the fourth barrier layer to remove the first N-type region, the P-type region A and the P-type region B above the corresponding covering floating gate a fourth barrier layer of the electrode;

g. Self-aligned implantation of P-type impurity ions above the fourth barrier layer to obtain a first P-type lightly doped region and a second P-type lightly doped region in the upper part of the P-type region A. In the first N-type The upper part of the region obtains the third P-type lightly doped region and the fourth P-type lightly doped region, and the upper part of the P-type region B obtains the fifth P-type lightly doped region and the sixth P-type lightly doped region ;

h, removing the above-mentioned fourth barrier layer, and depositing a side protection material on the first main surface to form a side protection layer on both sides of the floating gate electrode;

i. Deposit a fifth barrier layer on the above-mentioned first main surface, and selectively mask and etch the fifth barrier layer to remove the corresponding deposition on the P-type region A, the first N-type region and the P-type region B Covered fifth barrier layer;

j. Self-aligned implantation of P-type impurity ions again above the above-mentioned fifth barrier layer to obtain a first P-type heavily doped region and a second P-type heavily doped region in the upper part of the P-type region A. In the first N A third P-type heavily doped region and a fourth P-type heavily doped region are obtained in the upper part of the P-type heavily doped region, and a fifth P-type heavily doped region and a sixth P-type heavily doped region are obtained in the upper part of the third P-type heavily doped region. type heavily doped region;

k, removing the fifth barrier layer on the first main surface;

1. Deposit the P+ floating gate electrode material on the first main surface of the semiconductor substrate, and selectively mask and etch the P+ floating gate electrode material, so that the apex angles of the isolation trenches on both sides of the PMOS access transistor and the control capacitor are positive P+ floating gate electrodes are formed above.

When in the step a, the semiconductor substrate is a P conductivity type substrate, the step b includes

b1. Depositing a first barrier layer on the first main surface of the P conductivity type substrate, selectively masking and etching the first barrier layer, and self-aligning implanting N-type impurity ions above the first barrier layer, to obtain a second N-type region in the semiconductor substrate;

b2. removing the first barrier layer on the corresponding first main surface of the P conductivity type substrate, and depositing a second barrier layer on the first main surface;

b3. Selectively mask and etch the second barrier layer, and self-align implant N-type impurity ions above the second barrier layer to form a first N-type region and a third N-type region in the semiconductor substrate, the first Both the N-type region and the third N-type region are located above the second N-type region;

b4, removing the second barrier layer on the corresponding first main surface of the P conductivity type substrate, and depositing a third barrier layer on the first main surface;

b5. Selectively mask and etch the third barrier layer, and self-align implant P-type impurity ions above the third barrier layer to form a P-type region A and a P-type region B above the second N-type region, P The type region A and the P-type region B are separated by the first N-type region.

When in the step a, the semiconductor substrate is an N conductivity type substrate, the step b includes

s1, depositing a second barrier layer on the first main surface, and selectively masking and etching the second barrier layer;

s2. Self-alignment implanting N-type impurity ions above the second barrier layer to obtain the required first N-type region and second N-type region in the upper part of the N-conductivity type substrate;

s3, removing the second barrier layer on the first main surface, and depositing a third barrier layer on the first main surface;

s4. Selectively mask and etch the third barrier layer, and self-align implant P-type impurity ions on the third barrier layer, so as to obtain P-type region A and P-type region B in the N conductivity type substrate.

Advantages of the present invention: the upper part of the semiconductor substrate is provided with several isolation trenches, and the isolation medium is provided in the isolation trenches to form a domain medium area, and the PMOS access transistors, control capacitors and programming capacitors in the memory cells pass through the domain medium The regions are isolated from each other; a P+ floating gate electrode is provided directly above the apex of the isolation trench, and the P+ floating gate electrode is located on the gate dielectric layer and distributed correspondingly to the apex of the isolation trench. The width of the P+ floating gate electrode can be Completely cover the thinner oxide layer at the top corner, the P+ floating gate electrode is conductive polysilicon of P conductivity type, and the electrons on the P+ floating gate electrode are minority carriers, so when the non-volatile memory stores electrons, due to the P+ floating gate electrode Existence, it is difficult for electrons to leak through the oxide layer at the top corner, thereby improving the data storage time of the non-volatile memory, compact structure, compatible with CMOS logic process, reducing the cost of use, and improving the use of non-volatile memory reliability.

Description of drawings

Fig. 1 is a schematic structural diagram of Embodiment 1 of the present invention.

Fig. 2 is a schematic structural diagram of Embodiment 2 of the present invention.

3 to 14 are cross-sectional views of the specific implementation process of Embodiment 1 of the present invention, wherein:

FIG. 3 is a cross-sectional view of a substrate of P conductivity type used in the present invention.

FIG. 4 is a cross-sectional view of the second N-type region obtained in the present invention.

FIG. 5 is a cross-sectional view of the first N-type region and the third N-type region obtained in the present invention.

FIG. 6 is a cross-sectional view of P-type region A and P-type region B obtained in the present invention.

Fig. 7 is a cross-sectional view of the present invention after the domain medium region is obtained.

FIG. 8 is a cross-sectional view of the gate dielectric layer obtained in the present invention.

FIG. 9 is a cross-sectional view of the floating gate electrode obtained in the present invention.

FIG. 10 is a cross-sectional view of lightly doped regions obtained by self-alignment implantation of P impurity ions according to the present invention.

Fig. 11 is a cross-sectional view of the side protective layer obtained in the present invention.

FIG. 12 is a cross-sectional view of the present invention after self-alignment implantation of P impurity ions to obtain a heavily doped region.

FIG. 13 is a cross-sectional view of the present invention after removing the fifth barrier layer.

FIG. 14 is a cross-sectional view of the P+ floating gate electrode obtained in the present invention.

Figures 15 to 25 are cross-sectional views of the specific implementation process of Embodiment 2 of the present invention, wherein:

Fig. 15 is a cross-sectional view of an N conductive type substrate used in the present invention.

FIG. 16 is a cross-sectional view of the first N-type region and the second N-type region obtained in the present invention.

FIG. 17 is a cross-sectional view of P-type region A and P-type region B obtained in the present invention.

Fig. 18 is a cross-sectional view of the present invention after the domain medium region is obtained.

FIG. 19 is a cross-sectional view of the gate dielectric layer obtained in the present invention.

Fig. 20 is a cross-sectional view of the floating gate electrode obtained in the present invention.

FIG. 21 is a cross-sectional view of lightly doped regions obtained by self-alignment implantation of P impurity ions according to the present invention.

Fig. 22 is a cross-sectional view of the present invention after the side protective layer is obtained.

FIG. 23 is a cross-sectional view of the present invention after self-alignment implantation of P impurity ions to obtain a heavily doped region.

Fig. 24 is a cross-sectional view of the present invention after removing the fifth barrier layer.

Fig. 25 is a cross-sectional view after obtaining a P+ floating gate electrode according to the present invention.

Explanation of reference numerals: 1-P conductivity type substrate, 2-first N-type region, 3-second N-type region, 4-third N-type region, 5-P-type region A, 6-P-type doped region C, 7-first P-type heavily doped region, 8-first P-type lightly doped region, 9-P-type doped region D, 10-isolation trench, 11-second P-type lightly doped region, 12-Second P-type heavily doped region, 13-P-type source region, 14-Field dielectric region, 15-Gate dielectric layer, 16-Floating gate electrode, 17-Side protection layer, 18-Third P-type light Doped region, 19-third P-type heavily doped region, 20-P+ floating gate electrode, 21-P-type drain region, 22-fourth P-type lightly doped region, 23-fourth P-type heavily doped region Region, 24-P-type doped region E, 25-fifth P-type heavily doped region, 26-fifth P-type lightly doped region, 27-P-type doped region F, 28-sixth P-type lightly doped region Impurity region, 29-sixth P-type heavily doped region, 30-vertex, 31-P-type region B, 32-first main surface, 33-second main surface, 34-first barrier layer, 35-the first Second barrier layer, 36-third barrier layer, 37-fourth barrier layer, 38-fifth barrier layer, 39-N conductivity type substrate, 100-memory cell, 110-PMOS access transistor, 120-control capacitor and 130 - programming capacitor.

Detailed ways

The present invention will be further described below in conjunction with specific drawings and embodiments.

Generally, a non-volatile memory includes a semiconductor substrate, and a plurality of memory cells 100 for storage are arranged on the upper part of the semiconductor substrate, and the memory cells 100 include a PMOS access transistor 110, a control capacitor 120 and a programming capacitor 130 , the PMOS access transistor 110 , the control capacitor 120 and the programming capacitor 130 are isolated 14 through the domain dielectric region on the upper part of the semiconductor substrate. In the CMOS logic process, in order to reduce the size of the non-volatile memory, when the domain dielectric region 14 is formed, trench etching is generally performed first, and then an oxide layer is grown in the trench. When the groove is formed by etching, the groove has an apex 30 , and the apex 30 is located at the edge of the notch of the groove from the cross-section of the non-volatile memory, and the apex 30 generally has a certain slope. When growing an oxide layer in the trench, due to the existence of the corner 30, the thickness of the oxide layer at the top corner 30 of the trench is thinner than the oxide layer at other positions of the trench; During storage, due to the thinner oxide layer at the top corner 30, the electrons in the non-volatile memory can pass through the thinner oxide layer for leakage, that is, the data retention time of the non-volatile memory cannot meet the required requirements , reducing the reliability of non-volatile memory storage data. In order to improve the retention time of data stored in the non-volatile memory, the present invention will be described below through Embodiment 1 and Embodiment 2.

Example 1

As shown in Figure 1 and Figure 13: In order to make the non-volatile memory compatible with the CMOS logic process and enable the non-volatile memory to store for a longer period of time, the non-volatile memory includes a P conductivity type substrate 1 , the material of the P conductivity type substrate 1 is silicon. At least one memory cell 100 is provided on the upper part of the P conductivity type substrate 1, and the memory cell 100 includes a PMOS access transistor 110, a control capacitor 120 and a programming capacitor 130, and a gate electrode is deposited on the surface of the P conductivity type substrate 1. The dielectric layer 15 , the gate dielectric layer 15 covers the surface corresponding to the memory cell 100 , and the PMOS access transistor 110 , the control capacitor 120 and the programming capacitor 130 are isolated from each other by the domain dielectric region 14 in the P conductivity type substrate 1 . The domain dielectric region 14 is located in the isolation trench 10 of the P conductivity type substrate 1, the isolation trench 10 is located on the upper part of the P conductivity type substrate 1, extends downward from the first main surface 32 of the P conductivity type substrate 1, and passes through the A gate oxide layer is grown in the isolation trench 10 to obtain a domain dielectric region 14, and the material of the domain dielectric region 14 is generally silicon dioxide. It can be seen from the above analysis that the thickness of the oxide layer at the top corner 30 of the isolation trench 10 is thinner than that at other positions of the isolation trench 10 .

In order to improve the data retention time of the non-volatile memory in the present invention, a P+ floating gate electrode 20 is set directly above the top corner 30 of the isolation trench 10 on both sides of the PMOS access transistor 110 and the control capacitor 120, and the P+ floating gate The electrode 20 is located on the gate dielectric layer 15 , and the width of the P+ floating gate electrode 20 is distributed corresponding to the corner 30 , specifically, the width of the P+ floating gate electrode 20 can completely cover the thinner oxide layer at the corner 30 . The P+ floating gate electrode 20 is conductive polysilicon of P conductivity type, and the electrons on the P+ floating gate electrode 20 are minority carriers, so when the non-volatile memory stores electrons, due to the existence of the P+ floating gate electrode 20, it is difficult for the electrons to pass through the top again. The oxide layer at the corner 30 leaks electricity, thereby improving the data storage time of the non-volatile memory.

In the embodiment of the present invention, in order to further improve the data storage time of the non-volatile memory, P+ floating gate electrodes 20 are arranged directly above the corners 30 of the isolation trenches 10 on both sides of the programming capacitor 130, and the P+ floating gate electrodes 20 The electrodes 20 correspond to the top corners 30 of the isolation trenches 10 on both sides of the programming capacitor 130 to cover the corresponding top corners 30 . In the embodiment of the present invention, viewed from the cross-section of the non-volatile memory of the present invention, the apex 30 of the isolation trench 10 on both sides of the PMOS access transistor 110, the control capacitor 120, and the programming capacitor 130 refers to the two sides of the floating gate electrode 16. 30 area of the top corner of the side. At the same time, on the cross-section of the non-volatile memory of the present invention, the P+ floating gate electrode 20 can also be arranged directly above the corner 30 of the isolation groove 10 outside the memory cell 100. In the drawings of the embodiment of the present invention, the memory The P+ floating gate electrodes 20 on the outside of the cell 100 refer to the P+ floating gate electrodes 20 at the left and right ends; after the above-mentioned settings, the P+ floating gate electrodes 20 are arranged directly above the corners 30 of each isolation trench 20, which can Further improve the data retention time of non-volatile memory.

A floating gate electrode 16 is deposited on the gate dielectric layer 15, and the floating gate electrode 16 covers the gate dielectric layer 15 and penetrates through the gate dielectric layer 15 corresponding to the PMOS access transistor 110, the control capacitor 120 and the programming capacitor 130, thereby The PMOS access transistor 110 , the control capacitor 120 and the programming capacitor 130 are connected and cooperated with each other. Both sides of the floating gate electrode 16 are covered with a side protection layer 17 , and the side protection layer 17 covers the corresponding outer wall surface of the floating gate electrode 16 . Seen from the top view plane of the non-volatile memory in the embodiment of the present invention, the P+ floating gate electrode 20 is in contact with the floating gate electrode 16 .

The PMOS access transistor 110, the control capacitor 120 and the programming capacitor 130 are isolated from the P conductivity type region in the P conductivity type substrate 1 through the third N type region 4 on the outside and the second N type region 3 below, and the P conductivity type substrate The P-conductive region within 1 forms the first P-type region. The material of the floating gate electrode 16 includes conductive polysilicon, the gate dielectric layer 15 is silicon dioxide, the side protection layer 17 is silicon dioxide or silicon nitride; the field dielectric region 14 is silicon dioxide.

The PMOS access transistor 110 includes a first N-type region 2, and a symmetrically distributed P-type source region 13 and a P-type drain region 21 are arranged on the upper part of the first N-type region 2, and the P-type source region The region 13 and the P-type drain region 21 are in contact with the corresponding domain dielectric region 14 and the upper gate dielectric layer 15 . The P-type source region 13 includes a third P-type lightly doped region 18 and a third P-type heavily doped region 19, and the doping concentration of the third P-type heavily doped region 19 is greater than that of the third P-type lightly doped region. The doping concentration of region 18. The P-type drain region 21 includes a fourth P-type lightly doped region 22 and a fourth P-type heavily doped region 23, and the doping concentration of the fourth P-type heavily doped region 23 is greater than that of the fourth P-type lightly doped region. The doping concentration of region 22. The third P-type lightly doped region 18 and the fourth P-type lightly doped region 22 are in the same manufacturing layer, and the third P-type heavily doped region 19 and the fourth P-type heavily doped region 23 are in the same manufacturing layer. The third P-type lightly doped region 18 is in contact with the third P-type heavily doped region 19, and is in contact with the domain dielectric region 14 through the third P-type heavily doped region 19. The third P-type lightly doped region 18 The width extending in the first N-type region 2 is consistent with the thickness of the side protection layer 17 ; meanwhile, the distribution of the fourth P-type lightly doped region 22 is the same as that of the third P-type lightly doped region 18 .

The control capacitor 120 includes a P-type region A5, and the upper part of the P-type region A5 is provided with a P-type doped region C6 and a P-type doped region D9; the P-type doped region C6 is symmetrical to the P-type doped region D9 Distributed in the P-type area A5. The P-type doped region C6 and the P-type doped region D9 are in contact with the corresponding field dielectric region 14 and the gate dielectric layer 15 . The P-type doped region C6 includes a first P-type lightly doped region 8 and a first P-type heavily doped region 7, and the first P-type lightly doped region 8 passes through the first P-type heavily doped region 7 and the domain dielectric region. 14 , the extension distance of the first P-type lightly doped region 8 in the P-type region A5 is consistent with the thickness of the side protection layer 17 . The P-type doped region D9 includes a second P-type lightly doped region 11 and a second P-type heavily doped region 12, and the second P-type lightly doped region 11 communicates with the second P-type heavily doped region 12. The dielectric region 14 is in contact with each other, and the distribution of the second P-type lightly doped region 11 is consistent with that of the first P-type lightly doped region 8 . A capacitor structure, namely a control capacitor 120 , is formed between the floating gate electrode 16 and the gate dielectric layer 15 and the P-type region A5 below the gate dielectric layer 15 . Similarly, a capacitor structure, ie, a programming capacitor 130 , is also formed between the floating gate electrode 16 and the gate dielectric layer 15 and the P-type region B31 below the gate dielectric layer 15 .

The programming capacitor 130 includes a P-type region B31, the upper part of the P-type region B31 is provided with a P-type doped region E24 and a P-type doped region F27, and the P-type doped region E24 is symmetrical to the P-type doped region F27 distributed in the P-type region B31. The P-type doped region E24 includes a fifth P-type lightly doped region 26 and a fifth P-type heavily doped region 25, and the fifth P-type heavily doped region 25 has a higher doping concentration than the fifth P-type lightly doped region 26. The doping concentration of the fifth P-type lightly doped region 26 is in contact with the domain dielectric region 14 through the fifth P-type heavily doped region 25, and the extension distance of the fifth P-type lightly doped region 26 in the P-type region B31 It is consistent with the thickness of the side protection layer 17 . The P-type doped region F27 includes a sixth P-type lightly doped region 28 and a sixth P-type heavily doped region 29, and the sixth P-type lightly doped region 28 passes through the fourth N-type lightly doped region 29 and the domain dielectric region. 14 , the distribution of the sixth P-type lightly doped region 28 is consistent with that of the fifth P-type lightly doped region 26 . The fifth P-type lightly doped region 26 and the sixth P-type lightly doped region 28 are in the same manufacturing layer, and the fifth P-type heavily doped region 25 and the sixth P-type heavily doped region 29 are in the same manufacturing layer.

Data can be written into the memory cell 100 through the programming capacitor 130, or the data in the memory cell 100 can be erased; the stored data state in the memory cell 100 can be read through the PMOS access transistor 110, and the stored data state in the memory cell 100 can be read through the control capacitor 120 The voltage value can be transmitted to the floating gate electrode 16 to realize the voltage value between the floating gate electrode 16 and the programming capacitor 130 , and data writing, erasing and reading operations can be realized according to the corresponding voltage value.

As shown in Figure 3 to Figure 13: the non-volatile memory with the above structure can be realized through the following process steps, specifically:

a. Provide a P conductivity type substrate 1, the P conductivity type substrate 1 includes a first main surface 32 and a second main surface 33; as shown in Figure 3: the P conductivity type substrate 1 is compatible with conventional CMOS process preparation requirements Consistently, the material of the P conductivity type substrate 1 can be commonly used silicon, and the first main surface 32 corresponds to the second main surface 33;

b. Perform required barrier layer deposition, barrier layer etching and self-aligned ion implantation on the first main surface 32 of the P conductivity type substrate 1 to form the required first N Type region 2, the third N-type region 4, P-type region A5 and P-type region B31, the first N-type region 2 is located between the P-type region A5 and the P-type region B31, and the third N-type region 4 is located in the P-type region A5 and the outside of the P-type area B31;

As shown in Figures 4 to 6, the specific formation process is as follows:

b1. Deposit a first barrier layer 34 on the first main surface 32 of the P conductivity type substrate 1, and selectively mask and etch the first barrier layer 34, and perform self-aligned implantation on the first barrier layer 34 N-type impurity ions to obtain a second N-type region 3 in the P conductivity type substrate 1; as shown in Figure 4, the first barrier layer 34 is silicon dioxide or silicon nitride; when the first main surface 32 After depositing the first barrier layer 34, by etching the first barrier layer 34 in the central region, after implanting N-type impurity ions in self-alignment, a second N-type region 3 can be obtained in the P conductivity type substrate 1; N-type impurity ions are impurity ions commonly used in semiconductor technology, and the required second N-type region 3 can be formed by controlling the dose and energy of N-type impurity ion implantation;

b2, removing the first barrier layer 34 corresponding to the first main surface 32 of the above-mentioned P conductivity type substrate 1, and depositing a second barrier layer 35 on the first main surface 32;

b3. Selectively mask and etch the second barrier layer 35, and self-align implant N-type impurity ions above the second barrier layer 35 to form the first N-type region 2 and the third N-type region 2 in the semiconductor substrate 1 Region 4, the first N-type region 2 and the third N-type region 4 are all located above the second N-type region 3; as shown in Figure 5: After selectively masking and etching the second barrier layer 35, it will be necessary to form The corresponding second barrier layer 35 above the first N-type region 2 and the third N-type region 4 is etched away, and after implanting N-type impurity ions, the first N-type region 2 and the third N-type region 4 can be formed. outside of the third N-type region 4 and the first N-type region 2;

b4, removing the second barrier layer 35 corresponding to the first main surface 32 of the above-mentioned P conductivity type substrate 1, and depositing a third barrier layer 36 on the first main surface 32;

b5. Selectively mask and etch the third barrier layer 36, and self-align implant P-type impurity ions above the third barrier layer 36 to form a P-type region A5 and a P-type region above the second N-type region 3 B31, the P-type region A5 is isolated from the P-type region B31 by the first N-type region 2;

As shown in Figure 6: when etching the third barrier layer 36, the corresponding third barrier layer 36 above the P-type region A5 and the P-type region B31 is removed, and after self-alignment implantation of P-type impurity ions, a P-type impurity ion can be formed Area A5 and P-type area B31;

c. Perform trench etching in the above-mentioned semiconductor substrate to form the required isolation trench 10 in the semiconductor substrate, and set an isolation medium in the isolation trench 10 to form a field dielectric region 14 in the semiconductor substrate, so The dielectric region 14 extends downward from the first main surface 32, and isolates the upper parts of the third N-type region 4, the P-type region A5, the first N-type region 2, and the P-type region B31 from each other;

As shown in FIG. 7 : the domain dielectric region 14 is silicon dioxide, which can be obtained by conventional thermal oxidation growth in the isolation trench 10 ;

d. Deposit a gate dielectric layer 15 on the first main surface 32 corresponding to the above-mentioned P conductivity type substrate 1, and the gate dielectric layer 15 covers the first main surface 32 of the semiconductor substrate 1; as shown in FIG. 8: the gate The dielectric layer 15 is silicon dioxide, and the gate dielectric layer 15 covers the corresponding surface of the domain dielectric region 14 and the semiconductor substrate 1;

e. Deposit a floating gate electrode 16 on the first main surface 32 of the above-mentioned P conductivity type substrate 1, the floating gate electrode 16 covers the gate dielectric layer 15 and penetrates the P-type region A5, the first N-type region 2 and On the corresponding gate dielectric layer 15 above the P-type region B31; as shown in FIG. Connected to one another; here, in order to be able to show the structure of the present invention, the sectional view of the present invention is obtained by adopting the spaced sectional method; the floating gate electrode 16 is T-shaped on the gate dielectric layer 15;

f. Deposit the fourth barrier layer 37 on the above gate dielectric layer 15, and selectively mask and etch the fourth barrier layer 37 to remove the first N-type region 2, the P-type region A5 and the corresponding upper part of the P-type region B31 a fourth barrier layer 37 covering the floating gate electrode 16;

g. Self-aligned implantation of P-type impurity ions above the fourth barrier layer 37 to obtain a first P-type lightly doped region 8 and a second P-type lightly doped region 11 in the upper part of the P-type region A5. A third P-type lightly doped region 18 and a fourth P-type lightly doped region 22 are obtained in the upper part of the N-type region 2, and a fifth P-type lightly doped region 26 and a fourth P-type lightly doped region 22 are obtained in the upper part of the P-type region B31. Six P-type lightly doped regions 28; as shown in Figure 10: the fourth barrier layer 37 is silicon dioxide or silicon nitride; after selectively masking and etching the fourth barrier layer 37, except for the P-type region A5 1. Both the first N-type region 2 and the corresponding regions outside the P-type region B31 can block the implantation of P-type impurity ions into the P-type conductivity type substrate 1; the conventional self-aligned implantation of P-type impurity ions can simultaneously obtain the required P-type lightly doped region;

h. Remove the above-mentioned fourth barrier layer 37, and deposit a side protection material on the first main surface 32 to form a side protection layer 17 on both sides of the floating gate electrode 16; as shown in FIG. 11 : the side protection layer The material of 17 is silicon oxide or silicon dioxide, and the required heavily doped region can be formed through the side protection layer 17, and at the same time, the corresponding lightly doped region can be correspondingly consistent with the side protection layer 17;

i. Deposit the fifth barrier layer 38 on the first main surface 32, and selectively mask and etch the fifth barrier layer 38 to remove the P-type region A5, the first N-type region 2 and the P-type region B31 The fifth barrier layer 38 is correspondingly deposited and covered on the top; the fifth barrier layer 38 is deposited and selectively masked and etched, mainly to avoid ion implantation into the P-type conductivity type substrate 1 when forming a heavily doped region. In the area; the fifth barrier layer 38 is silicon dioxide or silicon nitride;

j. Self-aligned implantation of P-type impurity ions again above the fifth barrier layer 38 to obtain a first P-type heavily doped region 7 and a second P-type heavily doped region 12 in the upper part of the P-type region A5. The upper part of the first N-type region 2 obtains the third P-type heavily doped region 19 and the fourth P-type heavily doped region 23, and the upper part of the third P-type heavily doped region 31 obtains the fifth P-type heavily doped region. Doped region 25 and the sixth P-type heavily doped region 29; as shown in Figure 12: the concentration of the self-aligned implanted P-type impurity ions is greater than the ion concentration of step g, due to the fifth barrier layer 38 and side protection The barrier of the layer 17 can make a heavily doped region be formed at the position corresponding to the lightly doped region, and the remaining lightly doped region can be consistent with the side protection layer 17, thereby obtaining the required single polycrystalline structure;

k. Removing the fifth barrier layer 38 on the first main surface 32 . As shown in FIG. 13 : the fifth barrier layer 38 is removed to obtain the required non-volatile memory.

1. Deposit the P+ floating gate electrode material on the above-mentioned gate dielectric layer 15, and selectively mask and etch the P+ floating gate electrode material, so as to isolate the top corner of the trench 10 on both sides of the PMOS access transistor 110 and the control capacitor 120 30 are formed directly above the P+ floating gate electrodes 20 as shown in FIG. 14 .

Example 2

As shown in Fig. 2 and Fig. 25: in this embodiment, the semiconductor substrate is an N-conductivity type substrate 39. After the N-conductivity type substrate 39 is adopted, there is no need to form a second N-type region 3 in the N-conductivity type substrate 39, that is, a P-type region. The region A5 and the P-type region B31 are in direct contact with the N-type conductive type substrate 39 , and meanwhile, the first N-type region 2 and the third N-type region 4 are also in direct contact with the N-type conductive type substrate 39 . After adopting the N conductive type substrate 39 , the rest of the structure is the same as that of Embodiment 1.

As shown in Figure 15 to Figure 25: the non-volatile memory with the above structure can be realized through the following process steps, specifically:

a. Provide an N conductive type substrate 39, the N conductive type substrate 39 includes a first main surface 32 and a second main surface 33; as shown in FIG. 15 , the material of the N conductive type substrate 39 can be silicon;

b. Perform required barrier layer deposition, barrier layer etching and self-aligned ion implantation on the first main surface 32 of the semiconductor substrate to form the required first N-type region 2, the third N-type region 4, P-type region A5 and P-type region B31, the first N-type region 2 is located between P-type region A5 and P-type region B31, and the third N-type region 4 is located between P-type region A5 and P-type region B31 outside;

The forming process of step b can be divided into:

s1, depositing a second barrier layer 35 on the first main surface 32, and selectively masking and etching the second barrier layer 35;

S2. Self-aligned implantation of N-type impurity ions above the second barrier layer 35 to obtain the required first N-type region 2 and second N-type region 4 in the upper part of the N-conductivity type substrate 39, as shown in FIG. 16 shown;

s3, removing the second barrier layer 35 on the first main surface 32, and depositing a third barrier layer 36 on the first main surface 32;

s4, selectively masking and etching the third barrier layer 36, and implanting P-type impurity ions on the third barrier layer 36 by self-alignment, so as to obtain the P-type region A5 and the P-type region B31 in the N-conductivity type substrate 39 , as shown in Figure 17;

c. Perform trench etching in the above-mentioned semiconductor substrate to form the required isolation trench 10 in the semiconductor substrate, and set an isolation medium in the isolation trench 10 to form a field dielectric region 14 in the semiconductor substrate, so The dielectric region 14 extends downward from the first main surface 32, and isolates the upper parts of the third N-type region 4, the P-type region A5, the first N-type region 2 and the P-type region B31 from each other; as shown in FIG. 18 ;

d. Depositing a gate dielectric layer 15 on the corresponding first main surface 32 of the semiconductor substrate, the gate dielectric layer 15 covering the first main surface 32 of the semiconductor substrate 1, as shown in FIG. 19 ;

e. Deposit a floating gate electrode 16 on the first main surface 32 of the semiconductor substrate, the floating gate electrode 16 covers the gate dielectric layer 15 and penetrates the P-type region A5, the first N-type region 2 and the P-type region on the corresponding gate dielectric layer 15 above B31, as shown in FIG. 20;

f. Deposit the fourth barrier layer 37 on the above-mentioned gate dielectric layer 15, and selectively mask and etch the fourth barrier layer 37 to remove the first N-type region 2, corresponding to the top of the P-type region A5 and the P-type region B31 a fourth barrier layer 37 covering the floating gate electrode 16;

g. Self-aligned implantation of P-type impurity ions above the fourth barrier layer 37 to obtain a first P-type lightly doped region 8 and a second P-type lightly doped region 11 in the upper part of the P-type region A5. A third P-type lightly doped region 18 and a fourth P-type lightly doped region 22 are obtained in the upper part of the N-type region 2, and a fifth P-type lightly doped region 26 and a fourth P-type lightly doped region 22 are obtained in the upper part of the P-type region B31. Six P-type lightly doped regions 28, as shown in FIG. 21;

h. Remove the above-mentioned fourth barrier layer 37, and deposit a side protection material on the first main surface 32 to form a side protection layer 17 on both sides of the floating gate electrode 16, as shown in FIG. 22 ;

i. Deposit the fifth barrier layer 38 on the first main surface 32, and selectively mask and etch the fifth barrier layer 38 to remove the P-type region A5, the first N-type region 2 and the P-type region B31 The fifth barrier layer 38 is correspondingly deposited and covered above;

j. Self-aligned implantation of P-type impurity ions again above the fifth barrier layer 38 to obtain a first P-type heavily doped region 7 and a second P-type heavily doped region 12 in the upper part of the P-type region A5. The upper part of the first N-type region 2 obtains the third P-type heavily doped region 19 and the fourth P-type heavily doped region 23, and the upper part of the third P-type heavily doped region 31 obtains the fifth P-type heavily doped region. The doped region 25 and the sixth P-type heavily doped region 29, as shown in FIG. 23;

k. Removing the fifth barrier layer 38 on the first main surface 32 , as shown in FIG. 24 .

1. Deposit the P+ floating gate electrode material on the above-mentioned gate dielectric layer 15, and selectively mask and etch the P+ floating gate electrode material, so as to isolate the top corner of the trench 10 on both sides of the PMOS access transistor 110 and the control capacitor 120 P+ floating gate electrodes 20 are formed directly above 30, as shown in FIG. 25 .

In the above description, the embodiments of the present invention assume that the memory cell 100 includes a PMOS access transistor 110, a control capacitor 120, and a programming capacitor 130. , those skilled in the art know that when the domain dielectric region 14 is formed in the isolation trench 10 during the process of preparing the memory cell 100, the P+ floating gate electrode 20 can be arranged at the corner 30 of the isolation trench 10, namely Except for the structure of the memory cell 100 described in the present invention, the memory cell 100 of other structures can also use the method of the present invention to arrange the P+ floating gate electrode 20 to improve the data retention time. The structures of the memory cells 100 of other structures are well known to those skilled in the art, and the structures of the memory cells 100 of the other structures are formed by setting the P+ floating gate electrode 20 of the present invention and will not be listed and described here.

At the same time, when describing the non-volatile memory above, the complete preparation process is described with the structure of the memory cell 100 including the PMOS access transistor 110 , the control capacitor 120 and the programming capacitor 130 . When the memory cell 100 of the non-volatile memory adopts other structures, the implementation steps compatible with the CMOS logic process can be adopted, as long as the isolation trench 10 is formed in the process of preparing the memory cell on the semiconductor substrate, and the isolation trench The isolation medium is grown in 10 to form the domain medium region 14, and the transistors and capacitors in the memory cell 100 can be isolated through the domain medium region 14, and the preparation process of the memory cell 100 with other structures will not be described in detail here.

As shown in FIG. 1 and FIG. 14 : for a single memory cell 100 , it can realize writing, reading and erasing of a single binary data. The working mechanism of the non-volatile memory of the present invention will be described below through the process of writing, reading and erasing a single memory cell 100 . When it is necessary to write input data, the voltage of the P-type region in the P-conductivity type substrate 1 is always set to 0 potential, and the first N-type region 2, the second N-type region 3 and the third N-type region 4 are all set to 5 potential , the P-type region A5 is also set at 0 potential, the voltage of the P-type region B31 is -5V, the voltages of the P-type doped region E24 and the P-type doped region F27 of the programming capacitor 130 are both set at -5V, and the voltage of the control capacitor 120 Both the P-type doped region C6 and the P-type doped region D9 are set at 5V; due to the transfer effect of the control capacitor 120, the voltage value of 5V can be transferred to the floating gate electrode 16, and a voltage of 4-5V is generated on the floating gate electrode 16. At this time, the voltage value between the floating gate electrode 16 and the P-type region B31 is 9-10V, and the electric field required by the field emission characteristic, also known as FN (Fowler-Nordheim) tunneling effect, will be reached, and the electrons will pass through the gate The dielectric layer 15 reaches into the floating gate electrode 16 to implement data writing. Since the bottom of the floating gate electrode 16 is isolated by the gate dielectric layer 15 and the side is isolated by the side protection layer 17 , electrons can remain in the floating gate electrode 16 for a long time.

When it is necessary to erase the data in the memory cell 100, the voltage of the P-type area in the P-conductive type substrate 1 is always set to 0 potential, the first N-type area 2, the second N-type area 3 and the third N-type area 4 The voltage of the P-type region A5 is set to 5V, the voltage of the P-type region A5 is set to -5V, the voltages of the P-type doped region C6 and the P-type doped region D9 are set to -5V, and the voltage of the P-type region B31 is set to 5V. Both the P-type doped region E24 and the P-type doped region F27 are set at a voltage of 5V. Under the action of the control capacitor 120, a voltage of -4V～-5V can be generated in the floating gate electrode 16. At this time, the floating gate electrode 16 and the P The voltage value between the P-type region B31 is -9～-10V, which will reach the electric field required by the field emission characteristic, also known as FN (Fowler-Nordheim) tunneling effect, and electrons will enter the P-type region B31 through the gate dielectric layer 15, In this way, data in the floating gate electrode 16 can be erased.

When it is necessary to read the data in the memory cell 100, the voltage of the P-type area in the P-conductive type substrate 1 is always set to 0 potential, the first N-type area 2, the second N-type area 3 and the third N-type area 4 The voltage of the P-type region A5 is set to -1V, the P-type doped region C6 and the P-type doped region D9 are both set to -1V, and the PMOS access transistor source region 13 and the PMOS access transistor drain region 21 are both set to 0.5V, the P-type region B31 is set to a voltage of 5V, and the P-type doped region E24 and the P-type doped region F27 are both set to a voltage of 5V. After the above-mentioned voltage value is loaded, when data is written in the memory cell 100, there are a large amount of electrons in the floating gate electrode 16, and when the data in the memory cell 100 is erased, the electrons flow out from the floating gate electrode 16; When there are electrons in the gate electrode 16, the current for accessing the source region 13 of the transistor through the PMOS is relatively large, and when electrons flow out from the floating gate electrode 16, the current for accessing the source region 13 of the transistor through the PMOS is relatively small. size, it can be known whether the memory cell 100 is in the state of writing data or in the state of erasing data.

Since the P-type doped region C6, the P-type doped region D9, the P-type source region 13, the P-type drain region 21, the P-type doped region E24, and the P-type doped region F27 can move in the corresponding P+ region Negative ions (electrons) have a small number of particles, so that when the inhaled data is stored for a longer period of time, it is safer and more reliable when stored and used.

Simultaneously, the P+ floating gate electrode 20 is set directly above the vertex 30 of the isolation trench 10, the P+ floating gate electrode 20 is conductive polysilicon of P conductivity type, and the electrons on the P+ floating gate electrode 20 are minority carriers. When the memory stores electrons, due to the existence of the P+ floating gate electrode 20 , it is difficult for electrons to leak through the oxide layer at the top corner 30 , thereby further improving the data storage time of the non-volatile memory.

As shown in Figure 2 and Figure 23: the non-volatile memory with a single polycrystalline structure formed by using the N conductivity type substrate 39 requires a corresponding loading voltage when writing, erasing and reading. To achieve the corresponding write, erase and read operations. Specifically, the corresponding writing, erasing and reading voltages are consistent with the operation voltage of the non-volatile memory with a single polycrystalline structure corresponding to the P conductivity type substrate 1 , which will not be described in detail here.

The upper part of the semiconductor substrate of the present invention is provided with a plurality of isolation trenches 10, and isolation dielectrics are arranged in the isolation trenches 10 to form domain dielectric regions 14, PMOS access transistors 110, control capacitors 120 and programming capacitors in memory cells 100 130 are isolated from each other by the field dielectric region 14; a P+ floating gate electrode 20 is provided directly above the apex 30 of the isolation trench 10, and the P+ floating gate electrode 20 is located on the gate dielectric layer 15 and connected to the apex of the isolation trench 10 30 corresponds to the distribution, the width of the P+ floating gate electrode 20 can completely cover the thinner oxide layer at the top corner 30, the P+ floating gate electrode 20 is conductive polysilicon of P conductivity type, and the electrons on the P+ floating gate electrode 20 are minority electrons, so When the non-volatile memory stores electrons, due to the existence of the P+ floating gate electrode 20, it is difficult for the electrons to leak through the oxide layer at the top corner 30, thereby improving the data storage time of the non-volatile memory.

Claims (8)

1. a non-volatility memory with P+ floating gate electrode, comprises semiconductor substrate, and the top in described semiconductor substrate is provided with some memory body cells (100) for storing; Described memory body cell (100) comprises PMOS access transistor (110), control capacitance (120) and programming electric capacity (130); It is characterized in that: the top in described semiconductor substrate is provided with some isolated grooves (10), in described isolated groove (10), be provided with spacer medium to form field areas of dielectric (14); PMOS access transistor (110), control capacitance (120) and programming electric capacity (130) in memory body cell (100) are isolated mutually by field areas of dielectric (14); On first interarea (32) of semiconductor substrate, be deposited with gate dielectric layer (15), described gate dielectric layer (15) covers the notch of isolated groove (10) and covers first interarea (32) of semiconductor substrate; Directly over the drift angle (30) of PMOS access transistor (110), control capacitance (120) both sides isolated grooves (10), P+ floating gate electrode (20) is all set, it is upper that described P+ floating gate electrode (20) is positioned at gate dielectric layer (15), and corresponding with the drift angle (30) of corresponding isolated groove (10);

The material of described semiconductor substrate comprises silicon, and semiconductor substrate is P conduction type substrate (1) or N conduction type substrate (39); When described semiconductor substrate is P conduction type substrate (1), described PMOS access transistor (110), control capacitance (120) and programming electric capacity (130) are isolated with P-type conduction type of substrate (1) by the 3rd N-type region (4) of the second N-type region (3) in P-type conduction type of substrate (1) and top, the second N-type region (3);

Described gate dielectric layer (15) is provided with floating gate electrode (16), described floating gate electrode (16) covers and runs through the gate dielectric layer (15) of PMOS access transistor (110), control capacitance (120) and programming electric capacity (130) top correspondence, the both sides of floating gate electrode (16) are deposited with lateral protection layer (17), and lateral protection layer (17) covers the sidewall of floating gate electrode (16); The P type source area (13) that PMOS access transistor (110) comprises the first N-type region (2) and is positioned at described the first N-type region (2) internal upper part and P type drain region (21), control capacitance (120) comprises territory, p type island region A(5) and be positioned at described p type island region territory A(5) the P type doped region C(6 of internal upper part) with P type doped region D(9); Programming electric capacity (130) comprises territory, p type island region B(31) and be positioned at described p type island region territory B(31) the P type doped region E(24 of internal upper part) with P type doped region F(27); P type doped region C(6), P type doped region D(9), P type doped region E(24), P type doped region F(27), P type source area (13) and P type drain region (21) corresponding with the floating gate electrode (16) of top, and contact with corresponding gate dielectric layer (15) and field areas of dielectric (14) respectively.

2. a kind of non-volatility memory with P+ floating gate electrode according to claim 1, is characterized in that: the conductive polycrystalline silicon that described P+ floating gate electrode (20) is P conduction type.

3. a kind of non-volatility memory with P+ floating gate electrode according to claim 1, it is characterized in that: directly over the drift angle (30) of described programming electric capacity (130) both sides isolated grooves (10), P+ floating gate electrode (20) is set, described P+ floating gate electrode (20) is corresponding with the drift angle (30) of programming electric capacity (130) both sides isolated grooves (10).

4. a kind of non-volatility memory with P+ floating gate electrode according to claim 1, is characterized in that: the material of described gate dielectric layer (15) comprises silicon dioxide; Described lateral protection layer (17) is silicon nitride or silicon dioxide.

5. a kind of non-volatility memory with P+ floating gate electrode according to claim 1, is characterized in that: the material of described floating gate electrode (16) comprises the conductive polycrystalline silicon of N conduction type.

6. a non-volatility memory preparation method with P+ floating gate electrode, is characterized in that, the preparation method of described non-volatility memory comprises the steps:

(a), provide semiconductor substrate, described semiconductor substrate to comprise the first interarea (32) and the second interarea (33);

(b), on first interarea (32) of semiconductor substrate, carry out required barrier layer deposition, barrier etch and autoregistration Implantation, to form the first required N-type region (2), the 3rd N-type region (4), territory, p type island region A(5 in semiconductor substrate) and territory, p type island region B(31), the first N-type region (2) is positioned at territory, p type island region A(5) and territory, p type island region B(31) between, the 3rd N-type region (4) is positioned at territory, p type island region A(5) and territory, p type island region B(31) outside;

(c), in above-mentioned semiconductor substrate, carry out etching groove, to form required isolated groove (10) in semiconductor substrate, and in isolated groove (10), spacer medium is set, to form field areas of dielectric (14) in semiconductor substrate, described field areas of dielectric (14) is from the first interarea (32) to downward-extension, and makes the 3rd N-type region (4), territory, p type island region A(5), the first N-type region (2) and territory, p type island region B(31) top mutually isolate;

(d), at the upper deposit gate dielectric layer (15) of the first interarea (32) corresponding to above-mentioned semiconductor substrate, first interarea (32) of described gate dielectric layer (15) covering semiconductor substrate;

(e), at the upper deposit floating gate electrode (16) of first interarea (32) of above-mentioned semiconductor substrate, described floating gate electrode (16) is covered in gate dielectric layer (15) and go up and runs through territory, p type island region A(5), the first N-type region (2) and territory, p type island region B(31) on the gate dielectric layer (15) of top correspondence;

(f), on the upper deposit of above-mentioned gate dielectric layer (15) the 4th barrier layer (37), and optionally shelter and etching the 4th barrier layer (37), to remove the first N-type region (2), territory, p type island region A(5) and territory, p type island region B(31) corresponding the 4th barrier layer (37) that covers floating gate electrode (16), top;

(g), inject p type impurity ion in above-mentioned the 4th barrier layer (37) top autoregistration, at territory, p type island region A(5) in top obtain a P type lightly doped region (8) and the 2nd P type lightly doped region (11), top in the first N-type region (2) obtains the 3rd P type lightly doped region (18) and the 4th P type lightly doped region (22), and at territory, p type island region B(31) in top obtain the 5th P type lightly doped region (26) and the 6th P type lightly doped region (28);

(h), remove above-mentioned the 4th barrier layer (37), and at the upper deposit lateral protection material of the first interarea (32), form lateral protection layers (17) with the both sides at floating gate electrode (16);

(i), on the upper deposit of above-mentioned the first interarea (32) the 5th barrier layer (38), and optionally shelter and etching the 5th barrier layer (38), to remove territory, p type island region A(5), the first N-type region (2) and territory, p type island region B(31) the 5th barrier layer (38) that covers of the corresponding deposit in top;

(j), in above-mentioned the 5th top, barrier layer (38), p type impurity ion is injected in autoregistration again, at territory, p type island region A(5) in top obtain a P type heavily doped region (7) and the 2nd P type heavily doped region (12), top in the first N-type region (2) obtains the 3rd P type heavily doped region (19) and the 4th P type heavily doped region (23), and at territory, p type island region B(31) in top obtain the 5th P type heavily doped region (25) and the 6th P type heavily doped region (29);

(k), remove the 5th barrier layer (38) on the first interarea (32);

(l), deposit P+ floating gate electrode material above the first interarea of semiconductor substrate, and optionally shelter the floating gate electrode material with etching P+, all to form P+ floating gate electrode (20) directly over the drift angle (30) at PMOS access transistor (110), control capacitance (120) both sides isolated grooves (10).

7. a kind of non-volatility memory preparation method with P+ floating gate electrode according to claim 6, is characterized in that: when in described step (a), when semiconductor substrate is P conduction type substrate (1), described step (b) comprises

(b1), deposit the first barrier layer (34) on first interarea (32) of P conduction type substrate (1), and optionally shelter and the first barrier layer (34) described in etching, in the first barrier layer (34), N-type foreign ion is injected in top autoregistration, to obtain the second N-type region (3) in P conduction type substrate (1);

(b2), remove the first barrier layer (34) on corresponding the first interarea of above-mentioned P conduction type substrate (1) (32), and on upper deposit the second barrier layer (35) of the first interarea (32);

(b3), optionally shelter and etching the second barrier layer (35), and inject N-type foreign ion in the second barrier layer (35) top autoregistration, to form the first N-type region (2) and the 3rd N-type region (4) in P conduction type substrate (1), the first N-type region (2) and the 3rd N-type region (4) are all positioned at the top in the second N-type region (3);

(b4), remove the second barrier layer (35) on corresponding the first interarea of above-mentioned P conduction type substrate (1) (32), and on the upper deposit of the first interarea (32) the 3rd barrier layer (36);

(b5), optionally shelter and etching the 3rd barrier layer (36), and inject p type impurity ion in the 3rd barrier layer (36) top autoregistration, to form territory, p type island region A(5 in the second N-type region (3) top) and territory, p type island region B(31), territory, p type island region A(5) with territory, p type island region B(31) between isolate by the first N-type region (2).

8. a kind of non-volatility memory preparation method with P+ floating gate electrode according to claim 6, is characterized in that: when in described step (a), when semiconductor substrate is N conduction type substrate (39), described step (b) comprises

(s1), on upper deposit the second barrier layer (35) of the first interarea (32), and optionally shelter and etching the second barrier layer (35);

(s2), inject N-type foreign ion in the autoregistration of the top on above-mentioned the second barrier layer (35), obtain the first required N-type region (2) and the second N-type region (4) with the top N conduction type substrate (39) in;

(s3), remove the second barrier layer (35) on the first interarea (32), and on the upper deposit of the first interarea (32) the 3rd barrier layer (36);

(s4), optionally shelter and etching the 3rd barrier layer (36), and inject p type impurity ion in the 3rd barrier layer (36) top autoregistration, to obtain territory, p type island region A(5 in N conduction type substrate (39)) and territory, p type island region B(31).