CN102723281A - Flip chip double-faced three-dimensional circuit manufacture method by encapsulation prior to etching and flip chip double-faced three-dimensional circuit encapsulation structure - Google Patents
Flip chip double-faced three-dimensional circuit manufacture method by encapsulation prior to etching and flip chip double-faced three-dimensional circuit encapsulation structure Download PDFInfo
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- CN102723281A CN102723281A CN2012101886078A CN201210188607A CN102723281A CN 102723281 A CN102723281 A CN 102723281A CN 2012101886078 A CN2012101886078 A CN 2012101886078A CN 201210188607 A CN201210188607 A CN 201210188607A CN 102723281 A CN102723281 A CN 102723281A
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- metal substrate
- green lacquer
- metal
- back side
- pin
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000005530 etching Methods 0.000 title abstract description 8
- 238000005538 encapsulation Methods 0.000 title abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 334
- 239000002184 metal Substances 0.000 claims abstract description 334
- 239000000758 substrate Substances 0.000 claims abstract description 201
- 238000000576 coating method Methods 0.000 claims abstract description 68
- 239000011248 coating agent Substances 0.000 claims abstract description 64
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 44
- 229910052802 copper Inorganic materials 0.000 claims abstract description 32
- 239000010949 copper Substances 0.000 claims abstract description 32
- 238000007747 plating Methods 0.000 claims abstract description 30
- 238000002203 pretreatment Methods 0.000 claims abstract description 29
- 238000003486 chemical etching Methods 0.000 claims abstract description 19
- 238000005520 cutting process Methods 0.000 claims abstract description 14
- 238000004140 cleaning Methods 0.000 claims abstract description 5
- 239000004922 lacquer Substances 0.000 claims description 122
- 239000000463 material Substances 0.000 claims description 55
- 238000003384 imaging method Methods 0.000 claims description 25
- 238000001465 metallisation Methods 0.000 claims description 21
- 238000013459 approach Methods 0.000 claims description 13
- 239000005022 packaging material Substances 0.000 claims description 13
- 239000004033 plastic Substances 0.000 claims description 13
- 230000003628 erosive effect Effects 0.000 claims description 8
- 239000000047 product Substances 0.000 claims description 8
- 239000003822 epoxy resin Substances 0.000 claims description 6
- 229920000647 polyepoxide Polymers 0.000 claims description 6
- 238000010079 rubber tapping Methods 0.000 claims description 6
- 150000002739 metals Chemical class 0.000 claims description 4
- 239000011265 semifinished product Substances 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 238000009713 electroplating Methods 0.000 abstract description 14
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 238000013461 design Methods 0.000 abstract description 3
- 238000003912 environmental pollution Methods 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000003973 paint Substances 0.000 abstract 8
- 239000003365 glass fiber Substances 0.000 description 14
- 239000011889 copper foil Substances 0.000 description 12
- 238000007772 electroless plating Methods 0.000 description 12
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 10
- 239000004411 aluminium Substances 0.000 description 10
- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 10
- 229910052709 silver Inorganic materials 0.000 description 10
- 239000004332 silver Substances 0.000 description 10
- 239000011521 glass Substances 0.000 description 8
- 238000011112 process operation Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 238000007639 printing Methods 0.000 description 6
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000007654 immersion Methods 0.000 description 4
- 239000003112 inhibitor Substances 0.000 description 4
- 238000012856 packing Methods 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 229910000863 Ferronickel Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- ZBTDWLVGWJNPQM-UHFFFAOYSA-N [Ni].[Cu].[Au] Chemical compound [Ni].[Cu].[Au] ZBTDWLVGWJNPQM-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 238000000149 argon plasma sintering Methods 0.000 description 2
- UIFOTCALDQIDTI-UHFFFAOYSA-N arsanylidynenickel Chemical compound [As]#[Ni] UIFOTCALDQIDTI-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 230000007812 deficiency Effects 0.000 description 2
- 230000029087 digestion Effects 0.000 description 2
- 239000003814 drug Substances 0.000 description 2
- 239000011152 fibreglass Substances 0.000 description 2
- 238000005187 foaming Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052742 iron Inorganic materials 0.000 description 2
- FBAFATDZDUQKNH-UHFFFAOYSA-M iron chloride Chemical compound [Cl-].[Fe] FBAFATDZDUQKNH-UHFFFAOYSA-M 0.000 description 2
- KFZAUHNPPZCSCR-UHFFFAOYSA-N iron zinc Chemical compound [Fe].[Zn] KFZAUHNPPZCSCR-UHFFFAOYSA-N 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- -1 porpezite Chemical compound 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 238000007704 wet chemistry method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000005496 eutectics Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
本发明涉及一种芯片倒装双面三维线路先封后蚀制造方法，它包括以下工艺步骤：取金属基板；金属基板表面预镀铜材；绿漆披覆；金属基板正面去除部分绿漆；电镀惰性金属线路层；电镀金属线路层；绿漆披覆；金属基板正面去除部分绿漆；电镀金属线路层；绿漆披覆；金属基板正面去除部分绿漆；覆上线路网板；金属化前处理；移除线路网板；电镀金属线路层；装片及芯片底部填充包封；金属基板背面去除部分绿漆；化学蚀刻；电镀金属线路层；电镀金属线路层；绿漆披覆；绿漆表面开孔；清洗；植球；切割成品。本发明的有益效果是：降低了制造成本，提高了封装体的安全性和可靠性，减少了环境污染，能够真正做到高密度线路的设计和制造。
The invention relates to a method for manufacturing flip-chip double-sided three-dimensional circuits by first sealing and then etching, which comprises the following process steps: taking a metal substrate; pre-plating copper on the surface of the metal substrate; coating with green paint; removing part of the green paint from the front of the metal substrate; Electroplating inert metal circuit layer; electroplating metal circuit layer; green paint coating; removing part of the green paint on the front of the metal substrate; electroplating metal circuit layer; green paint coating; removing part of the green paint on the front of the metal substrate; Pre-treatment; removal of circuit board; electroplating metal circuit layer; chip loading and chip underfill encapsulation; removal of part of the green paint on the back of the metal substrate; chemical etching; electroplating metal circuit layer; electroplating metal circuit layer; green paint coating; green Opening holes on the painted surface; cleaning; planting balls; cutting finished products. The beneficial effects of the invention are: the manufacturing cost is reduced, the safety and reliability of the packaging body are improved, the environmental pollution is reduced, and the design and manufacture of high-density circuits can be truly achieved.
Description
Technical field
The present invention relates to the two-sided three-dimensional circuit of a kind of flip-chip be honored as a queen earlier erosion manufacturing approach and encapsulating structure thereof, belong to the semiconductor packaging field.
Background technology
The manufacturing process flow of traditional high-density base board encapsulating structure is as follows:
Step 4, referring to Figure 74, insert conductive materials in the position of glass fiber substrate punching,
Step 8, referring to Figure 78, the part that completion is windowed is carried out etching,
Above-mentioned traditional high-density base board encapsulating structure exists following deficiency and defective:
1, many glass fiber materials of one deck, same also many costs of layer of glass;
2, because must use glass fiber, so with regard to many thickness space of about 100 ~ 150 μ m of layer of glass thickness;
3, glass fiber itself is exactly a kind of foaming substance, so easily because time of placing and environment suck moisture and moisture, directly have influence on the security capabilities of reliability or the grade of reliability;
4, the fiberglass surfacing Copper Foil metal layer thickness of about 50 ~ 100 μ m of one deck that has been covered; And the etching of metal level circuit and circuit distance also because the etched gap that the characteristic of etching factor can only be accomplished 50 ~ 100 μ m (referring to Figure 83; Best making ability is that etched gap is equal to the thickness that is etched object approximately), so the design of accomplishing high-density line and manufacturing that can't be real;
5, because must use the Copper Foil metal level, and the Copper Foil metal level is the mode that the employing high pressure is pasted, so the thickness of Copper Foil is difficult to be lower than the thickness of 50 μ m, otherwise just is difficult to operation like out-of-flatness or Copper Foil breakage or Copper Foil extension displacement or the like;
6, also because the whole base plate material is to adopt glass fiber material, thus significantly increased thickness 100 ~ 150 μ m of glass layer, can't be real accomplish ultra-thin encapsulation;
7, the traditional glass fiber stick on Copper Foil technology because material property difference very big (coefficient of expansion) causes stress deformation easily in the operation of adverse circumstances, directly have influence on precision and element and substrate adherence and reliability that element loads.
Summary of the invention
The objective of the invention is to overcome above-mentioned deficiency, provide the two-sided three-dimensional circuit of a kind of flip-chip to be honored as a queen earlier and lose manufacturing approach and encapsulating structure thereof, its technology is simple; Need not use glass layer; Reduce manufacturing cost, improved the fail safe and the reliability of packaging body, reduced the environmental pollution that glass fiber material brings; And the metal substrate line layer adopts is electro-plating method, can really accomplish the design and the manufacturing of high-density line.
The objective of the invention is to realize like this: the two-sided three-dimensional circuit of a kind of flip-chip erosion manufacturing approach of being honored as a queen earlier, it comprises following processing step:
Electroplate one deck copper material film in metallic substrate surfaces,
Accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer,
Step 4, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 3 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
The graphics field of windowing has been accomplished in step 4 metal substrate front has electroplated upward inert metal line layer,
Inert metal line layer surface metal plated line layer in step 5,
Accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more,
Step 8, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 7 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
The graphics field of windowing has been accomplished in step 8 metal substrate front has electroplated upward metallic circuit layer,
Accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more,
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 10 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone,
The metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front,
The circuit web plate that metal substrate front in the step 12 is covered with removes,
The positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate electroplated goes up the metallic circuit layer, after said metallic circuit layer is electroplated and is accomplished promptly on the positive top that forms pin or Ji Dao and pin relatively of metal substrate,
Chip and chip bottom filling epoxy resin in the relative pin that forms of step 15 or Ji Dao and the upside-down mounting of pin top front face,
The plastic packaging material operation is sealed in metal substrate front after step 10 six completion flip-chip and the chip bottom filling,
The green lacquer of part is removed at step 10 eight, the metal substrate back side
Utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, exposing the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching,
The graphics field of windowing is accomplished at the metal substrate back side in the step 10 eight carries out chemical etching,
Accomplish the inert metal line layer surface of exposing after the chemical etching in step 10 nine and carry out the plating of metallic circuit layer, step 2 11, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 ten is accomplished the plated metal line layer,
The green lacquer of part is removed at step 2 12, the metal substrate back side
Utilize exposure imaging equipment to carry out graph exposure, develop and window at the metal substrate back side that step 2 11 is accomplished green lacquer coating, exposing the graphics field that the follow-up needs in the metal substrate back side are electroplated,
The graphics field of windowing has been accomplished at the step 2 12 metal substrate back sides has electroplated upward metallic circuit layer,
The lining of green lacquer is carried out at the metal substrate back side in that step 2 13 is accomplished the plated metal line layer once more,
The green lacquer of part is removed at step 2 15, the metal substrate back side
Utilize exposure imaging equipment to carry out graph exposure, develop and window at the metal substrate back side that step 2 14 is accomplished green lacquer coating, exposing the graphics field that the follow-up needs in the metal substrate back side are electroplated,
Be covered with the circuit web plate at the metal substrate back side,
The circuit web plate that the metal substrate back side in the step 2 16 is covered with removes,
The zone that the pre-treatment of plated metal line layer is accomplished at the step 2 17 metal substrate back sides is electroplated and is gone up the metallic circuit layer, after said metallic circuit layer is electroplated and is accomplished promptly in the positive bottom that forms pin or Ji Dao and pin relatively of metal substrate,
The lining of green lacquer is carried out at the metal substrate back side in that step 2 19 is accomplished the plated metal line layer once more,
The follow-up perforate operation that will plant the metal ball zone is carried out on green lacquer surface in step 3 ten metal substrate back side coatings,
The green lacquer tapping in the step 3 11 metal substrate back sides is cleaned
Be implanted into metal ball in step 3 12 through the aperture that cleans,
The two-sided three-dimensional circuit of a kind of flip-chip is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach; It comprises Ji Dao, pin and chip; Said flip-chip is positive in Ji Dao and pin; Be provided with underfill between said chip bottom and Ji Dao and the pin front, the zone between zone, pin and the pin between zone, Ji Dao and the pin of periphery, said basic island and the zone of Ji Dao and pin bottom are encapsulated with green lacquer, and the zone and the chip on said Ji Dao and pin top are encapsulated with plastic packaging material outward; Offer aperture on the green lacquer surface of said pin bottom; Said aperture is connected with the pin back side, is provided with metal ball in the said aperture, and said metal ball contacts with the pin back side.
The green lacquer tapping in 12 pairs of metal substrate back sides of said step 3 cleans and carries out the coat of metal lining simultaneously.
Said encapsulating structure comprises Ji Dao, and this moment, flip-chip Ji Dao and pin were positive, were provided with underfill between said chip bottom and front, basic island and the pin front.
Said Ji Dao has single or a plurality of.
Compared with prior art, the present invention has following beneficial effect:
1, the present invention need not use glass layer, so can reduce the cost that glass layer brings;
2, the present invention does not use the foaming substance of glass layer, so the grade of reliability can improve again, the fail safe to packaging body will improve relatively;
3, the present invention need not use the glass layer material, so just can reduce the environmental pollution that glass fiber material brings;
What 4,3-dimensional metal substrate circuit layer of the present invention was adopted is electro-plating method; And the gross thickness of electrodeposited coating is about 10 ~ 15 μ m; And the gap between circuit and the circuit can reach the gap below the 25 μ m easily, so can accomplish the technical capability of pin circuit tiling in the high density veritably;
5,3-dimensional metal substrate of the present invention is the metal level galvanoplastic because of what adopt; So the technology than glass fiber high pressure Copper Foil metal level is come simply, and do not have metal level because high pressure produces bad or puzzled that metal level out-of-flatness, metal level breakage and metal level extend and be shifted;
6,3-dimensional metal substrate circuit layer of the present invention is to carry out metal plating on the surface of metal base; So the material characteristic is basic identical; So the internal stress of coating circuit and metal base is basic identical, can carries out the back engineering (like the surface mount work of high temperature eutectic load, high temperature tin material scolder load and high temperature passive device) of adverse circumstances easily and be not easy to produce stress deformation.
Description of drawings
Fig. 1 ~ Figure 34 is honored as a queen earlier for the two-sided three-dimensional circuit of flip-chip of the present invention and loses each operation sketch map of manufacturing approach embodiment one.
Figure 35 is honored as a queen earlier for the two-sided three-dimensional circuit of flip-chip of the present invention and loses the structural representation of encapsulating structure embodiment one.
Figure 36 ~ Figure 69 is honored as a queen earlier for the two-sided three-dimensional circuit of flip-chip of the present invention and loses each operation sketch map of manufacturing approach embodiment two.
Figure 70 is honored as a queen earlier for the two-sided three-dimensional circuit of flip-chip of the present invention and loses the structural representation of encapsulating structure embodiment two.
Figure 71 ~ Figure 82 is each operation sketch map of the manufacturing process flow of traditional high-density base board encapsulating structure.
Figure 83 is the etching situation sketch map of fiberglass surfacing Copper Foil metal level.
Wherein:
Inert metal line layer 4
Chip 8
Coat of metal 12
Embodiment
The two-sided three-dimensional circuit of flip-chip of the present invention be honored as a queen earlier the erosion manufacturing approach comprise following processing step:
Embodiment one, no Ji Dao
Referring to Fig. 1, get the suitable metal substrate of a slice thickness, the material of said metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper material, iron material, ferronickel material or zinc-iron material etc.;
Referring to Fig. 2, electroplate one deck copper material film in metallic substrate surfaces, purpose is to do the basis for follow-up plating, the mode of said plating can adopt chemical plating or metallide;
Referring to Fig. 3, accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer, to protect follow-up electroplated metal layer process operation;
Step 4, the positive green lacquer of part of removing of metal substrate
Referring to Fig. 4, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Referring to Fig. 5; The graphics field of windowing has been accomplished in step 4 metal substrate front electroplated upward inert metal line layer; As the barrier layer of subsequent etch operation, said inert metal wiring material layer adopts nickel, titanium or copper etc., and said plating mode adopts chemical plating or metallide mode;
Referring to Fig. 6; Inert metal line layer surface metal plated line layer in step 5; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Fig. 7, accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 8, the positive green lacquer of part of removing of metal substrate
Referring to Fig. 8, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 7 is accomplished green lacquer coating;
Referring to Fig. 9; The graphics field of windowing has been accomplished in step 8 metal substrate front electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 10, accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Referring to Figure 11, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 10 is accomplished green lacquer coating;
Referring to Figure 12, be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone;
Referring to Figure 13, the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Referring to Figure 14, the circuit web plate that metal substrate front in the step 12 is covered with removes;
Referring to Figure 15; Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 16, chip and chip bottom filling epoxy resin in the pin top front face upside-down mounting that step 15 forms relatively;
Referring to Figure 17; The plastic packaging material operation is sealed in metal substrate front after step 10 six completion flip-chip and the chip bottom filling; The mode of sealing of plastic packaging material can adopt mould encapsulating mode, spraying method or brush coating mode, and said plastic packaging material can adopt packing material or not have the epoxy resin of packing material;
The green lacquer of part is removed at step 10 eight, the metal substrate back side
Referring to Figure 18, utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, to expose the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching;
Referring to Figure 19, the graphics field of windowing to be accomplished at the metal substrate back side in the step 10 eight carry out chemical etching, chemical etching is till the position of inert metal line layer, and etching liquid medicine can adopt copper chloride or iron chloride;
Referring to Figure 20; Accomplish the inert metal line layer surface of exposing after the chemical etching in step 10 nine and carry out the plating of metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and said electro-plating method can be electroless plating or metallide;
Referring to Figure 21, carry out the lining of green lacquer at the metal substrate back side that step 2 ten is accomplished the plated metal line layer;
The green lacquer of part is removed at step 2 12, the metal substrate back side
Referring to Figure 22, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the follow-up needs in the metal substrate back side are electroplated at the metal substrate back side that step 2 11 is accomplished green lacquer coating;
Referring to Figure 23; The graphics field of windowing has been accomplished at the step 2 12 metal substrate back sides electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 24, carry out the lining of green lacquer once more at the metal substrate back side that step 2 13 is accomplished the plated metal line layer, to protect follow-up electroplated metal layer process operation;
The green lacquer of part is removed at step 2 15, the metal substrate back side
Referring to Figure 25, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the follow-up needs in the metal substrate back side are electroplated at the metal substrate back side that step 2 14 is accomplished green lacquer coating;
Referring to Figure 26, be covered with the circuit web plate at the metal substrate back side, the covering of circuit web plate is follow-up need not carry out metallized zone;
Referring to Figure 27, step 2 ten five metals are belonged to substrate back accomplished the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Referring to Figure 28, the circuit web plate that the metal substrate back side in the step 2 16 is covered with removes;
Referring to Figure 29; The step 2 17 metal substrate back sides are accomplished the zone of plated metal line layer pre-treatment and electroplate upward metallic circuit layer; After electroplating and accomplish, said metallic circuit layer promptly forms the bottom of pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 30, carry out the lining of green lacquer once more at the metal substrate back side that step 2 19 is accomplished the plated metal line layer;
Referring to Figure 31, carry out the follow-up perforate operation that will plant the metal ball zone on the green lacquer surface of step 3 ten metal substrate back side coatings, said perforate mode can adopt dry laser sintering or wet chemistry corroding method;
Referring to Figure 32, the green lacquer tapping in the step 3 11 metal substrate back sides is cleaned to remove oxidation material or organic substance etc., can carry out the lining of coat of metal simultaneously, coat of metal adopts oxidation inhibitor;
Referring to Figure 33; Be implanted into metal ball in step 3 12 through the aperture that cleans; Metal ball contacts with the back side of pin; The said ball mode of planting can adopt conventional ball attachment machine or adopt the paste printing after high-temperature digestion, can form orbicule again, and the material of metal ball can be pure tin or ashbury metal;
Referring to Figure 34; Step 3 13 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the two-sided three-dimensional circuit of chip formal dress and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The encapsulating structure of embodiment one is following:
Referring to Figure 35, the two-sided three-dimensional circuit of the flip-chip of the present invention erosion encapsulating structure of being honored as a queen earlier, it comprises pin 14 and chip 8; Said chip 8 upside-down mountings are in pin 14 fronts; Be provided with underfill 9 between said chip 8 bottoms and pin 14 fronts, the zone between zone, pin 14 and the pin 14 of said pin 14 peripheries and the zone of pin 14 bottoms are encapsulated with green lacquer 3, and the zone and the chip 8 on said pin 14 tops are encapsulated with plastic packaging material 10; Offer aperture 11 on green lacquer 3 surfaces of said pin 14 bottoms; Said aperture 11 is connected with pin 14 back sides, is provided with metal ball 13 in the said aperture 11, and said metal ball 13 contacts with pin 14 back sides; Be provided with coat of metal 12 between the said metal ball 13 and pin 14 back sides, said coat of metal 12 is an oxidation inhibitor.
Embodiment two, Ji Dao is arranged
Referring to Figure 36, get the suitable metal substrate of a slice thickness, the material of said metal substrate can be carried out conversion according to the function and the characteristic of chip, for example: copper material, iron material, ferronickel material or zinc-iron material etc.;
Referring to Figure 37, electroplate one deck copper material film in metallic substrate surfaces, purpose is to do the basis for follow-up plating, the mode of said plating can adopt chemical plating or metallide;
Referring to Figure 38, accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer, to protect follow-up electroplated metal layer process operation;
Step 4, the positive green lacquer of part of removing of metal substrate
Referring to Figure 39, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 3 is accomplished green lacquer coating;
Referring to Figure 40; The graphics field of windowing has been accomplished in step 4 metal substrate front electroplated upward inert metal line layer; As the barrier layer of subsequent etch operation, said inert metal wiring material layer adopts nickel, titanium or copper etc., and said plating mode adopts chemical plating or metallide mode;
Referring to Figure 41; Inert metal line layer surface metal plated line layer in step 5; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 42, accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Step 8, the positive green lacquer of part of removing of metal substrate
Referring to Figure 43, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 7 is accomplished green lacquer coating;
Referring to Figure 44; The graphics field of windowing has been accomplished in step 8 metal substrate front electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 45, accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more, to protect follow-up electroplated metal layer process operation;
Referring to Figure 46, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the positive follow-up needs of metal substrate are electroplated in the metal substrate front that step 10 is accomplished green lacquer coating;
Referring to Figure 47, be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone;
Referring to Figure 48, the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Referring to Figure 49, the circuit web plate that metal substrate front in the step 12 is covered with removes;
Referring to Figure 50; Upward metallic circuit layer is electroplated in the positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate; After electroplating and accomplish, said metallic circuit layer promptly forms the top of Ji Dao and pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 51, chip and chip bottom filling epoxy resin in relative Ji Dao that forms of step 15 and the upside-down mounting of pin top front face;
Referring to Figure 52; The plastic packaging material operation is sealed in metal substrate front after step 10 six completion flip-chip and the chip bottom filling; The mode of sealing of plastic packaging material can adopt mould encapsulating mode, spraying method or brush coating mode, and said plastic packaging material can adopt packing material or not have the epoxy resin of packing material;
The green lacquer of part is removed at step 10 eight, the metal substrate back side
Referring to Figure 53, utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, to expose the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching;
Referring to Figure 54, the graphics field of windowing to be accomplished at the metal substrate back side in the step 10 eight carry out chemical etching, chemical etching is till the position of inert metal line layer, and etching liquid medicine can adopt copper chloride or iron chloride;
Referring to Figure 55; Accomplish the inert metal line layer surface of exposing after the chemical etching in step 10 nine and carry out the plating of metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts copper nickel gold, copper nickeline, porpezite, gold or copper etc., and said electro-plating method can be electroless plating or metallide;
Referring to Figure 56, carry out the lining of green lacquer at the metal substrate back side that step 2 ten is accomplished the plated metal line layer;
The green lacquer of part is removed at step 2 12, the metal substrate back side
Referring to Figure 57, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the follow-up needs in the metal substrate back side are electroplated at the metal substrate back side that step 2 11 is accomplished green lacquer coating;
Referring to Figure 58; The graphics field of windowing has been accomplished at the step 2 12 metal substrate back sides electroplated upward metallic circuit layer; Said metallic circuit layer can be a single or multiple lift; Said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 59, carry out the lining of green lacquer once more at the metal substrate back side that step 2 13 is accomplished the plated metal line layer, to protect follow-up electroplated metal layer process operation;
The green lacquer of part is removed at step 2 15, the metal substrate back side
Referring to Figure 60, utilize exposure imaging equipment to carry out graph exposure, develop and window, to expose the graphics field that the follow-up needs in the metal substrate back side are electroplated at the metal substrate back side that step 2 14 is accomplished green lacquer coating;
Referring to Figure 61, be covered with the circuit web plate at the metal substrate back side, the covering of circuit web plate is follow-up need not carry out metallized zone;
Referring to Figure 62, step 2 ten five metals are belonged to substrate back accomplished the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing, said metallization pre-treatment mode can adopt modes such as coating, sprinkling, printing, showering or immersion;
Referring to Figure 63, the circuit web plate that the metal substrate back side in the step 2 16 is covered with removes;
Referring to Figure 64; The step 2 17 metal substrate back sides are accomplished the zone of plated metal line layer pre-treatment and electroplate upward metallic circuit layer; After electroplating and accomplish, said metallic circuit layer promptly forms the bottom of Ji Dao and pin relatively in the metal substrate front; Said metallic circuit layer can be a single or multiple lift, and said metallic circuit layer material adopts silver, aluminium, copper, nickel gold or NiPdAu etc., and said plating mode can be that electroless plating also can be the mode of metallide;
Referring to Figure 30, carry out the lining of green lacquer once more at the metal substrate back side that step 2 19 is accomplished the plated metal line layer;
Referring to Figure 31, carry out the follow-up perforate operation that will plant the metal ball zone on the green lacquer surface of step 3 ten metal substrate back side coatings, said perforate mode can adopt dry laser sintering or wet chemistry corroding method;
Referring to Figure 32, the green lacquer tapping in the step 3 11 metal substrate back sides is cleaned to remove oxidation material or organic substance etc., can carry out the lining of coat of metal simultaneously, coat of metal adopts oxidation inhibitor;
Referring to Figure 33; Be implanted into metal ball in step 3 12 through the aperture that cleans; Metal ball contacts with the back side of pin; The said ball mode of planting can adopt conventional ball attachment machine or adopt the paste printing after high-temperature digestion, can form orbicule again, and the material of metal ball can be pure tin or ashbury metal;
Referring to Figure 34; Step 3 13 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the two-sided three-dimensional circuit of chip formal dress and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
The encapsulating structure of embodiment two is following:
Referring to Figure 70; The two-sided three-dimensional circuit of the flip-chip of the present invention erosion encapsulating structure of being honored as a queen earlier; It comprises basic island 15, pin 14 and chip 8, and said chip 8 upside-down mountings are provided with underfill 9 in basic island 15 and pin 14 fronts between said chip 8 bottoms and basic island 15 and pin 14 fronts; The zone between zone, pin 14 and the pin 14 between zone, basic island 15 and the pin 14 of 15 peripheries, said basic island and the zones of basic island 15 and pin 14 bottoms are encapsulated with green lacquer 3; Be encapsulated with plastic packaging material 10 outside the zone on said basic island 15 and pin 14 tops and the chip 8, offer aperture 11 on green lacquer 3 surfaces of said pin 14 bottoms, said aperture 11 is connected with pin 14 back sides; Be provided with metal ball 13 in the said aperture 11; Said metal ball 13 contacts with pin 14 back sides, is provided with coat of metal 12 between the said metal ball 13 and pin 14 back sides, and said coat of metal 12 is an oxidation inhibitor.
Claims (5)
1. the two-sided three-dimensional circuit of flip-chip erosion manufacturing approach of being honored as a queen earlier is characterized in that said method comprises following processing step:
Step 1, get metal substrate
Step 2, metallic substrate surfaces preplating copper material
Electroplate one deck copper material film in metallic substrate surfaces,
Step 3, green lacquer coating
Accomplish the metal substrate front and the back side of preplating copper material film in step 2 and carry out the lining of green lacquer,
Step 4, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 3 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 5, plating inert metal line layer
The graphics field of windowing has been accomplished in step 4 metal substrate front has electroplated upward inert metal line layer,
Step 6, plated metal line layer
Inert metal line layer surface metal plated line layer in step 5,
Step 7, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 6 and carry out the lining of green lacquer once more,
Step 8, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 7 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 9, plated metal line layer
The graphics field of windowing has been accomplished in step 8 metal substrate front has electroplated upward metallic circuit layer,
Step 10, green lacquer coating
Accomplish the metal substrate front of plated metal line layer in step 9 and carry out the lining of green lacquer once more,
Step 11, the positive green lacquer of part of removing of metal substrate
Utilize exposure imaging equipment to carry out graph exposure, develop and window in the metal substrate front that step 10 is accomplished green lacquer coating, exposing the graphics field that the positive follow-up needs of metal substrate are electroplated,
Step 12, be covered with the circuit web plate
Be covered with the circuit web plate in the metal substrate front, the covering of circuit web plate is follow-up need not carry out metallized zone,
Step 13, metallization pre-treatment
The metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing has been accomplished in step 11 metal substrate front,
Step 14, remove the circuit web plate
The circuit web plate that metal substrate front in the step 12 is covered with removes,
Step 15, plated metal line layer
The positive zone of accomplishing the pre-treatment of plated metal line layer of step 13 metal substrate electroplated goes up the metallic circuit layer, after said metallic circuit layer is electroplated and is accomplished promptly on the positive top that forms pin or Ji Dao and pin relatively of metal substrate,
Step 10 six, load and chip bottom are filled
Chip and chip bottom filling epoxy resin in the relative pin that forms of step 15 or Ji Dao and the upside-down mounting of pin top front face,
Step 10 seven, seal
The plastic packaging material operation is sealed in metal substrate front after step 10 six completion flip-chip and the chip bottom filling,
The green lacquer of part is removed at step 10 eight, the metal substrate back side
Utilize exposure imaging equipment that the green lacquer of metal substrate back side coating is carried out graph exposure, develops and windows, exposing the graphics field that the follow-up needs in the metal substrate back side carry out chemical etching,
Step 10 nine, chemical etching
The graphics field of windowing is accomplished at the metal substrate back side in the step 10 eight carries out chemical etching,
Step 2 ten, plated metal line layer
Accomplish the inert metal line layer surface of exposing after the chemical etching in step 10 nine and carry out the plating of metallic circuit layer, step 2 11, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 ten is accomplished the plated metal line layer,
The green lacquer of part is removed at step 2 12, the metal substrate back side
Utilize exposure imaging equipment to carry out graph exposure, develop and window at the metal substrate back side that step 2 11 is accomplished green lacquer coating, exposing the graphics field that the follow-up needs in the metal substrate back side are electroplated,
Step 2 13, plated metal line layer
The graphics field of windowing has been accomplished at the step 2 12 metal substrate back sides has electroplated upward metallic circuit layer,
Step 2 14, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 13 is accomplished the plated metal line layer once more,
The green lacquer of part is removed at step 2 15, the metal substrate back side
Utilize exposure imaging equipment to carry out graph exposure, develop and window at the metal substrate back side that step 2 14 is accomplished green lacquer coating, exposing the graphics field that the follow-up needs in the metal substrate back side are electroplated,
Step 2 16, be covered with the circuit web plate
Be covered with the circuit web plate at the metal substrate back side,
Step 2 17, metallization pre-treatment
Step 2 ten five metals are belonged to substrate back have accomplished the metallization pre-treatment that the plated metal line layer is carried out in the graphics field of windowing,
Step 2 18, remove the circuit web plate
The circuit web plate that the metal substrate back side in the step 2 16 is covered with removes,
Step 2 19, plated metal line layer
The zone that the pre-treatment of plated metal line layer is accomplished at the step 2 17 metal substrate back sides is electroplated and is gone up the metallic circuit layer, after said metallic circuit layer is electroplated and is accomplished promptly in the positive bottom that forms pin or Ji Dao and pin relatively of metal substrate,
Step 3 ten, green lacquer coating
The lining of green lacquer is carried out at the metal substrate back side in that step 2 19 is accomplished the plated metal line layer once more,
Step 3 11, the surperficial perforate of green lacquer
The follow-up perforate operation that will plant the metal ball zone is carried out on green lacquer surface in step 3 ten metal substrate back side coatings,
Step 3 12, cleaning
The green lacquer tapping in the step 3 11 metal substrate back sides is cleaned
Step 3 13, plant ball
Be implanted into metal ball in step 3 12 through the aperture that cleans,
Step 3 14, cutting finished product
Step 3 13 is accomplished the semi-finished product of planting ball carry out cutting operation; Make originally to integrate and to contain more than cuttings of plastic-sealed body module of chip independent, make the two-sided three-dimensional circuit of chip formal dress and be honored as a queen earlier and lose the encapsulating structure finished product with array aggregate mode.
One kind according to claim 1 the two-sided three-dimensional circuit of flip-chip be honored as a queen earlier the erosion manufacturing approach encapsulating structure; It is characterized in that: it comprises Ji Dao (15), pin (14) and chip (8); Said chip (8) upside-down mounting is in Ji Dao (15) and pin (14) front; Be provided with underfill (9) between said chip (8) bottom and Ji Dao (15) and pin (14) front; The zone between zone, pin (14) and the pin (14) between zone, Ji Dao (15) and the pin (14) of said Ji Dao (15) periphery and the zone of Ji Dao (15) and pin (14) bottom are encapsulated with green lacquer (3); The outer plastic packaging material (10) that is encapsulated with of the zone on said Ji Dao (15) and pin (14) top and chip (8); Offer aperture (11) on green lacquer (3) surface of said pin (14) bottom; Said aperture (11) is connected with pin (14) back side, is provided with metal ball (13) in the said aperture (11), and said metal ball (13) contacts with pin (14) back side.
3. the two-sided three-dimensional circuit of a kind of flip-chip according to claim 1 erosion manufacturing approach of being honored as a queen earlier is characterized in that: the green lacquer tapping in 12 pairs of metal substrate back sides of said step 3 cleans and carries out the coat of metal lining simultaneously.
4. the two-sided three-dimensional circuit of a kind of flip-chip according to claim 2 is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach; It is characterized in that: said encapsulating structure comprises Ji Dao (15); This moment, chip (8) upside-down mounting Ji Dao (15) and pin (14) front were provided with underfill (9) between said chip (8) bottom and Ji Dao (15) front and pin (14) front.
5. the two-sided three-dimensional circuit of a kind of flip-chip according to claim 4 is honored as a queen earlier and is lost the encapsulating structure of manufacturing approach, and it is characterized in that: said Ji Dao (15) has single or a plurality of.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210188607.8A CN102723281B (en) | 2012-06-09 | 2012-06-09 | Flip chip double-faced three-dimensional circuit manufacture method by encapsulation prior to etching and flip chip double-faced three-dimensional circuit encapsulation structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210188607.8A CN102723281B (en) | 2012-06-09 | 2012-06-09 | Flip chip double-faced three-dimensional circuit manufacture method by encapsulation prior to etching and flip chip double-faced three-dimensional circuit encapsulation structure |
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| Publication Number | Publication Date |
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| CN102723281A true CN102723281A (en) | 2012-10-10 |
| CN102723281B CN102723281B (en) | 2014-08-20 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004327903A (en) * | 2003-04-28 | 2004-11-18 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and its manufacturing method |
| CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技（深圳）有限公司 | Flip ball grid array packaging base plate and making technique thereof |
| CN102005432A (en) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | Packaging structure with four pin-less sides and packaging method thereof |
-
2012
- 2012-06-09 CN CN201210188607.8A patent/CN102723281B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004327903A (en) * | 2003-04-28 | 2004-11-18 | Dainippon Printing Co Ltd | Resin sealed semiconductor device and its manufacturing method |
| CN1691314A (en) * | 2004-04-21 | 2005-11-02 | 美龙翔微电子科技（深圳）有限公司 | Flip ball grid array packaging base plate and making technique thereof |
| CN102005432A (en) * | 2010-09-30 | 2011-04-06 | 江苏长电科技股份有限公司 | Packaging structure with four pin-less sides and packaging method thereof |
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