CN102710289A - Multi-user time hopping-pulse position modulation ultra-wideband receiver demodulator - Google Patents

Abstract

The invention discloses a multi-user time-hopping pulse position modulation ultra-wideband receiver demodulator. The local encryption module generates the encrypted signal required in the demodulator. The multi-user module receives the signal of the local encryption module and provides the local template signal output by the multi-user. The clock tree receives the system clock signal from the clock and data recovery circuit and distributes it to the clock terminals of each sub-module of the demodulator. The template generating and comparing module receives the PPM signal from the radio frequency front end, and compares it with the local template signal. The synchronous counting out-of-synchronization reset module receives the comparison result generated by the template and the comparison module, performs signal synchronization judgment, and completes the out-of-synchronization reset operation. The judgment output module receives the data from the template generation and comparison module and the enable signal from the synchronous count out-of-step reset, and sends out the decoded data signal. The invention realizes the TH-UWB multi-user decoding function while saving the entire chip area through simple template comparison and synchronous control.

Description

Multi-user Time Hopping Pulse Position Modulation UWB Receiver Demodulator

technical field

The invention relates to the technical field of wireless communication, in particular to a multi-user time-hopping pulse position modulation ultra-wideband receiver demodulator.

Background technique

Ultra-wideband (UWB) is a very competitive communication method in high-speed wireless communication. It can realize carrier-based or carrier-less communication, and it is an ultra-high-speed short-distance wireless access technology. Ultra-wideband can transmit extremely low-power signals on a wide spectrum, and can achieve a data transmission rate of hundreds of megabits per second within a range of about 10m. It has strong anti-interference performance, high transmission rate, extremely wide bandwidth, and low consumption Small power, good confidentiality, low transmission power and many other advantages. Because the frequency spectrum of UWB signal is determined by modulation mode and signal waveform; therefore, the choice of UWB waveform and modulation technology is very important in the design of UWB system. In practical applications, it is necessary to comprehensively consider the use occasions and technical requirements of the system to select the appropriate waveform and modulation method. In a multi-user system, the UWB modulation method is a combination of multiple access modulation and information modulation, such as time-hopping pulses that can avoid interference between different users in time by assigning different time-hopping sequences to different users Position Modulation Ultra Wideband (TH - Pulse Position Modulation - UWB).

Ultra-wideband signal transmission is affected by factors such as large-scale path loss, shadowing effect, and small-scale multipath fading; therefore, the signal reaching the receiver is severely distorted, and the signal may also be affected by multiple access interference, narrowband interference, and background noise. Influence. In general, an ultra-wideband receiver is mainly composed of a demodulator and a detector. The function of the demodulator is to transform the received waveform into an N-dimensional vector r, where N is the dimension of the transmitted waveform. The function of the detector is to judge which waveform is sent according to r. As a key component of the UWB receiver, the demodulator often adopts the following two implementation methods at present, one is based on the application of signal correlation, but based on the application of matched filter. However, the demodulators implemented by the above two methods all have the characteristics of complex circuit structures.

Contents of the invention

The technical problem to be solved by the present invention is to provide a multi-user time-hopping pulse position modulation ultra-wideband receiver demodulator, the demodulator can be realized by standard digital CMOS technology, the circuit structure is simple, and the power consumption of the circuit can not be increased at the same time The multi-user function is realized under the premise of complexity and complexity.

In order to solve the above problems, the present invention is achieved through the following schemes:

The multi-user time-hopping pulse position modulation ultra-wideband receiver demodulator is characterized in that it is mainly composed of a clock tree module, a multi-user module, a local encryption module, two template generation and comparison modules, a synchronous counting out-of-step reset module, and a judgment output modules. The system clock input terminal of the clock tree module accepts the system clock sent by the receiver clock and data recovery circuit, and decomposes it into multiple outputs of the first clock, the second clock, the third clock and the fourth clock; the clock tree module The first clock output terminal of the first and second template is connected to the first clock input terminal of the first and second template generation and comparison module, the first clock input terminal of the judgment output module, the first clock input terminal of the synchronous counting out-of-sync reset module, and the local The first clock input of the encryption module; the second clock output of the clock tree module is connected to the second clock input of the first and second template generation and comparison modules; the third clock output of the clock tree module is connected to the decision output The third clock input terminal of the module; the fourth clock output terminal of the clock tree module is connected to the fourth clock input terminal of the decision output template. The first input end and the second input end of the multi-user module are respectively connected to the external numerical control multi-user selection end; the local pseudo-random code input end of the multi-user module receives the encrypted output signal from the local encryption module; the multi-user module of the multi-user module The output is connected to the multi-user input of the first and second template generating and comparing modules. The compared data input terminal of the local encryption module is connected to the compared data output terminal of the synchronous counting out-of-synchronization reset module. The system pulse position modulation input terminal of the first template generation and comparison module receives the external pulse position modulation input signal; the mode control input terminal of the first template generation and comparison module is connected to the power supply; the first template generation and comparison template Q this signal The output end is connected to the Q signal input end of the judgment output module; the Q external signal output end of the first template generation and comparison template is connected to the Q external signal input end of the judgment output module; The second pulse position modulation output terminal is connected to the compared second pulse position modulation input terminal of the synchronous counting out-of-step reset module. The system pulse position modulation input terminal of the second template generation and comparison module receives the external pulse position modulation input signal; the mode control input terminal of the second template generation and comparison module is connected to the ground; A pulse position modulation output terminal is connected to the compared first pulse position modulation input terminal of the synchronous counting out-of-step reset module. The enable output of the synchronous counting out-of-step reset module is connected to the enable input of the first and second template generation and comparison modules, and the enable input of the judgment output module; the external reset signal is connected to the synchronous count out-of-step reset module the reset input. The data output end of the decision output template is the data output end after the final decision of the demodulator; the data clock output end of the decision output template is the data clock output end after the final decision of the demodulator.

In the present invention, the multi-user module comprises the first AND gate circuit and the first OR gate circuit; the local pseudo-random code and the first multi-user selection terminal from the local encryption module are sent into the first AND gate circuit, and the first AND The output of the gate circuit and the second multi-user selection terminal are sent to the first OR gate circuit, and the output of the first OR gate circuit is the multi-user output terminal.

In the present invention, the local encryption module includes a second AND gate circuit, an 8-frequency division circuit and a local pseudo-random code generation circuit; the compared data signal from the synchronous counting out-of-sync reset module and the first clock tree module output The clock signal is sent to the second AND gate circuit, and the output of the second AND gate circuit is sent to the local pseudo-random code generation circuit through an 8-frequency division circuit, and finally the output of the local pseudo-random code generation circuit is an encrypted output terminal.

In the present invention, the first template generation and comparison module and the second template generation and comparison module each include a half adder circuit, a pulse position modulation generation circuit, a first D flip-flop circuit, two serial-to-parallel conversion circuits, a second A buffer circuit and a comparator circuit; the multi-user input signal and the mode control signal are sent to the half adder circuit, and the output of the half adder circuit is sent to the pulse position modulation generation circuit; the clock of the pulse position modulation generation circuit comes from the output of the clock tree module The first clock of the pulse position modulation generation circuit is sent to the first D flip-flop circuit, and the clock of the first D flip-flop circuit comes from the second clock output by the clock tree module; the output of the first D flip-flop circuit is sent to The first serial-to-parallel conversion circuit, the clock of the first serial-to-parallel conversion circuit comes from the first clock output by the clock tree module; the system pulse position modulation input signal is sent to the second serial-to-parallel conversion circuit, and the clock of the second serial-to-parallel conversion circuit comes from the clock The output of the tree module is the first clock; the respective 4 outputs of the first and second serial-to-parallel conversion circuits are sent to the first buffer circuit, and the enable signal of the first buffer circuit comes from the enable of the synchronous counting out-of-step reset module The two 4-way outputs of the first buffer circuit are sent to the comparator circuit, and the clock of the comparator circuit comes from the first clock output by the clock tree module; the output of the comparator circuit is the first or second pulse position modulation output after comparison One of the 4 outputs of the first serial-to-parallel conversion circuit is the Q output terminal, and one of the 4 outputs of the second serial-to-parallel conversion circuit is the Q external output terminal.

In the present invention, the synchronous counting out-of-step reset module includes a second OR gate circuit, a counter circuit and a third AND gate circuit; the first and second templates produce the first and second pulse positions compared with the output of the comparison module The modulated signal is sent into the second OR gate circuit together; the compared data signal output by the second OR gate circuit is provided to the local encryption module and sent into the counter circuit at the same time; the clock of the counter circuit comes from the first clock output by the clock tree module, The output of the counter circuit is sent to the input of the third AND gate circuit, the third AND gate circuit has a reset terminal, and the output of the third AND gate circuit is an enabling output terminal.

In the present invention, the decision output template includes 3 D flip-flop circuits, an NOR gate circuit, a fourth AND gate circuit, an integrating circuit and a second buffer circuit; the clocks of the second and the third D flip-flop circuits are all From the third clock signal output by the clock tree module, the data of the second D flip-flop circuit comes from the Q external signal of the first template generation and comparison module, and the data of the third D flip-flop circuit comes from the Q signal of the first template generation and comparison module. This signal; the outputs of the second and third D flip-flop circuits are sent to the same-OR gate circuit, the clock of the same-OR gate circuit comes from the first clock signal output by the clock tree module, and the output of the same-OR gate circuit is sent to the fourth AND Gate circuit; another signal of the fourth AND gate circuit is the enable of the synchronous counting out-of-step reset module, and the output of the fourth AND gate circuit is sent to the fourth D flip-flop circuit after being integrated by the integrator circuit; the fourth D flip-flop Both the clocks of the circuit and the second buffer circuit come from the fourth clock output by the clock tree module, the output of the fourth D flip-flop circuit is the data output end, and the output of the second buffer circuit is the data clock output end.

Compared with prior art, the present invention has following characteristics:

1. A new multi-user time-hopping pulse position modulation ultra-wideband (TH-PPM-UWB) digital receiver demodulation circuit structure is proposed. This circuit can be realized by standard digital CMOS technology. The circuit structure is simple and does not require additional circuits. The multi-user function is realized under the premise of power consumption and complexity;

2. Realize the data decoding function of multi-user UWB system, and the system is simple, saving the area of the entire circuit;

3. It has the functions of synchronous search and out-of-synchronization protection, which improves the stability of the demodulator and the reliability of the decoded data;

4. Capable of decoding encrypted UWB system signals;

5. Suitable for short-distance wireless high-speed data transmission system.

Description of drawings

Figure 1 is a schematic structural diagram of a TH-PPM-UWB receiver demodulator.

Fig. 2 is a schematic diagram of the multi-user selection module of the demodulator.

Fig. 3 is a schematic diagram of the local encryption module of the demodulator.

Fig. 4 is a schematic diagram of the template generation and comparison module of the demodulator.

Fig. 5 is a schematic diagram of the synchronous counting and out-of-synchronization reset module of the demodulator.

Fig. 6 is a schematic diagram of the decision output module of the demodulator.

FIG. 7 is a schematic diagram of the timing sequence of the input and output signals of the demodulator.

Detailed ways

Referring to Fig. 1, a multi-user time-hopping pulse position modulation ultra-wideband receiver demodulator is mainly composed of a clock tree module, a multi-user module, a local encryption module, two template generation and comparison modules, a synchronous counting out-of-step reset module, and a decision output module. The local encryption module is used to generate the encrypted signal required in the TH-PPM-UWB receiver demodulator, the multi-user module receives the signal from the local encryption module, and provides the local template signal output by the multi-user. The clock tree receives the system clock signal from the clock and data recovery circuit and distributes it to the clock terminals of each sub-module of the demodulator. The template generating and comparing module receives the PPM signal from the radio frequency front end, and compares it with the local template signal. The synchronous counting out-of-synchronization reset module receives the comparison result generated by the template and the comparison module, performs signal synchronization judgment, and completes the out-of-synchronization reset operation. The judgment output module receives the data from the template generation and comparison module and the enable signal from the synchronous count out-of-step reset, and sends out the decoded data signal. The invention realizes the TH-UWB multi-user decoding function while saving the entire chip area through simple template comparison and synchronous control.

The system clock input terminal sysclk of the clock tree module receives the system clock sent by the receiver clock and data recovery circuit, and decomposes it into multiple channels of the first clock clk0, the second clock clk1, the third clock clk2 and the fourth clock clk500 Output; the first clock output terminal clk0 of the clock tree module is connected to the first clock input terminal clk0 of the first and second template generation and comparison modules, the first clock input terminal clk0 of the judgment output module, and the synchronous counting out-of-step reset module The first clock input terminal clk0 and the first clock input terminal clk0 of the local encryption module; the second clock output terminal clk1 of the clock tree module is connected to the second clock input terminal clk1 of the first and second template generation and comparison modules; the clock The third clock output terminal clk2 of the tree module is connected to the third clock input terminal clk2 of the decision output module; the fourth clock output terminal clk500 of the clock tree module is connected to the fourth clock input terminal clk500 of the decision output module. The first input terminal A and the second input terminal B of the multi-user module are respectively connected to the external numerical control multi-user selection terminal; the local pseudo-random code local PN code input terminal of the multi-user module receives the encrypted output signal from the local encryption module; The multi-user output of the user module is connected to the multi-user input of the first and second template generation and comparison modules. The compared data input terminal Dcomp of the local encryption module is connected to the compared data output terminal Dcomp of the synchronization counting out-of-synchronization reset module. The system pulse position modulation input terminal PPMin of the first template generation and comparison module receives the external pulse position modulation input signal; the mode control input modctrl of the first template generation and comparison module is connected to the power supply Vdd; the first template generation and comparison template The Q signal output end is connected to the Q signal input end of the judgment output module; the Q external signal output end of the first template generation and comparison template is connected to the Q external signal input end of the judgment output module; the first template generation and comparison template The compared second pulse position modulation output port and the compared post PPM1 are connected to the compared second pulse position modulation input port of the synchronous counting out-of-step reset module. The system pulse position modulation input terminal PPMin of the second template generation and comparison module receives the external pulse position modulation input signal; the mode control input modctrl of the second template generation and comparison module is connected to ground Vss; the second template generation and comparison template The first pulse position modulation output terminal after comparison PPM0 after comparison is connected to the first pulse position modulation input terminal after comparison of synchronous counting out-of-step reset module PPM0 after comparison. The enable output end en of the synchronous counting out-of-step reset module is connected to the enable input end en of the first and second template generation and comparison modules, and the enable input end en of the judgment output module; the external reset signal Reset is connected to the synchronous counting The reset input terminal Reset of the out-of-synchronization reset module. The data output terminal Dataout of the decision output template is the data output terminal after the final decision of the demodulator; the data clock output terminal clkout of the decision output template is the data clock output terminal after the final decision of the demodulator.

In order to realize the present invention by adopting standard digital CMOS process, the concrete circuit of each module of the present invention constitutes as follows:

In the present invention, the multi-user module comprises the first AND gate circuit and the first OR gate circuit; the local pseudo-random code and the first multi-user selection terminal from the local encryption module are sent into the first AND gate circuit, and the first AND The output of the gate circuit and the second multi-user selection terminal are sent to the first OR gate circuit, and the output of the first OR gate circuit is the multi-user output terminal.

In the present invention, the local encryption module includes a second AND gate circuit, an 8-frequency division circuit and a local pseudo-random code generation circuit; the compared data signal from the synchronous counting out-of-sync reset module and the first clock tree module output The clock signal is sent to the second AND gate circuit, and the output of the second AND gate circuit is sent to the local pseudo-random code generation circuit through an 8-frequency division circuit, and finally the output of the local pseudo-random code generation circuit is an encrypted output terminal.

In the present invention, the first template generation and comparison module and the second template generation and comparison module each include a half adder circuit, a pulse position modulation generation circuit, a first D flip-flop circuit, two serial-to-parallel conversion circuits, a second A buffer circuit and a comparator circuit; the multi-user input signal and the mode control signal are sent to the half adder circuit, and the output of the half adder circuit is sent to the pulse position modulation generation circuit; the clock of the pulse position modulation generation circuit comes from the output of the clock tree module The first clock of the pulse position modulation generation circuit is sent to the first D flip-flop circuit, and the clock of the first D flip-flop circuit comes from the second clock output by the clock tree module; the output of the first D flip-flop circuit is sent to The first serial-to-parallel conversion circuit, the clock of the first serial-to-parallel conversion circuit comes from the first clock output by the clock tree module; the system pulse position modulation input signal is sent to the second serial-to-parallel conversion circuit, and the clock of the second serial-to-parallel conversion circuit comes from the clock The output of the tree module is the first clock; the respective 4 outputs of the first and second serial-to-parallel conversion circuits are sent to the first buffer circuit, and the enable signal of the first buffer circuit comes from the enable of the synchronous counting out-of-step reset module The two 4-way outputs of the first buffer circuit are sent to the comparator circuit, and the clock of the comparator circuit comes from the first clock output by the clock tree module; the output of the comparator circuit is the first or second pulse position modulation output after comparison One of the 4 outputs of the first serial-to-parallel conversion circuit is the Q output terminal, and one of the 4 outputs of the second serial-to-parallel conversion circuit is the Q external output terminal.

In the present invention, the synchronous counting out-of-step reset module includes a second OR gate circuit, a counter circuit and a third AND gate circuit; the first and second templates produce the first and second pulse positions compared with the output of the comparison module The modulated signal is sent into the second OR gate circuit together; the compared data signal output by the second OR gate circuit is provided to the local encryption module and sent into the counter circuit at the same time; the clock of the counter circuit comes from the first clock output by the clock tree module, The output of the counter circuit is sent to the input of the third AND gate circuit, the third AND gate circuit has a reset terminal, and the output of the third AND gate circuit is an enabling output terminal.

In the present invention, the decision output template includes 3 D flip-flop circuits, an NOR gate circuit, a fourth AND gate circuit, an integrating circuit and a second buffer circuit; the clocks of the second and the third D flip-flop circuits are all From the third clock signal output by the clock tree module, the data of the second D flip-flop circuit comes from the Q external signal of the first template generation and comparison module, and the data of the third D flip-flop circuit comes from the Q signal of the first template generation and comparison module. This signal; the outputs of the second and third D flip-flop circuits are sent to the same-OR gate circuit, the clock of the same-OR gate circuit comes from the first clock signal output by the clock tree module, and the output of the same-OR gate circuit is sent to the fourth AND Gate circuit; another signal of the fourth AND gate circuit is the enable of the synchronous counting out-of-step reset module, and the output of the fourth AND gate circuit is sent to the fourth D flip-flop circuit after being integrated by the integrator circuit; the fourth D flip-flop Both the clocks of the circuit and the second buffer circuit come from the fourth clock output by the clock tree module, the output of the fourth D flip-flop circuit is the data output end, and the output of the second buffer circuit is the data clock output end.

The multi-user input terminal is the input position pulse modulation signal, which is respectively sent to the first and second module generation and comparison modules. The first and second module generation and comparison modules are respectively local PPM template signals. The first module generates and The mode control terminal of the comparison module is connected to the power supply (high level Vdd), and the second module generates and the mode control terminal of the comparison module is grounded (low level Vss), so that one channel can be used to generate a PPM signal whose template is "1". The other way is used to generate the PPM signal whose template is "0". When the information data is "0" code, the PPM template signal circuit outputs a TH-PPM baseband signal containing information code "0"; when the information data is "1" code, the PPM template signal circuit outputs a TH-PPM baseband signal containing information code "1" for TH-PPM baseband signal. The multi-user module realizes the multi-user selection function by connecting A and B terminals with high level, low level, and different combinations of PN pseudo-random sequences. The output ends of the generating and comparing modules of the first and second modules are sent to the synchronous counting out-of-synchronization reset module. The main function of the synchronous counting out-of-synchronization reset module is to provide synchronization search and out-of-synchronization protection functions for the receiver. Under normal circumstances, it is used to realize the system's re-synchronization search and out-of-synchronization protection functions. The template generation and comparison module shifts and compares the received TH-PPM signal with the PPM template signal of the hidden information code "0" or "1", and then sends the parallel comparison result to the synchronous counting and out-of-synchronization reset module. When the output signal voltage values of the two template generation and comparison modules are both low level, the output signal of the OR gate is low level, and the control counter circuit starts counting. When the count value reaches the set value, the counter circuit outputs high level. The enabling end of the control related detector circuit is turned on, and the two template generating and comparing modules start working again. After the system is synchronized, the judgment is made through the judgment output module, and the information signal is recovered. The clock tree module provides the system clock for each module of the receiver. The output signal of the judgment output module is high level, which means the recovery information code "1"; when the output of the integrator is low level, the output signal of the decision device is low level, which means the recovery information code "0". The function of the D flip-flop circuit is to shape the output signal of the integrator.

Since the digital circuit has certain requirements for the setup time and the hold time, the present invention realizes the requirements for the setup time and the hold time through the application of the D flip-flop and the inverter. If the signal changes at the edge of the clock, it may cause instability. At this time, invert the clock to move the edge of the clock to the middle of the signal level, which can improve the stability of the circuit and have a great effect on the jitter of the clock. Good noise immunity. However, after the clock is inverted, we must pay attention to the change of the desired signal to avoid errors. The function of the D flip-flop is to shape the signal to prolong the hold time of the signal. Since the D flip-flop is a sequential circuit, the signal shaped by it has a synchronous nature and is transmitted completely according to the clock. Combining an inverter and a D flip-flop makes the circuit more stable.

Finally, it should be noted that any modification or equivalent replacement of the technical solution of the present invention without departing from the spirit and scope of the technical solution of the present invention shall be covered by the claims of the present invention.

Claims (6)

1. pulse position modulation ultra wideband receiver demodulator when the multi-user jumps is characterized in that: mainly by clock trees module, multi-user's module, local encryption module, 2 template generations and comparison modules, count the step-out reseting module synchronously and the judgement output module is formed;

The system clock input (sysclk) of clock trees module is accepted the system clock that receiver clock and data recovery circuit are sent here, and it is decomposed into first clock (clk0), second clock (clk1), this multichannel output of the 3rd clock (clk2) and the 4th clock (clk500); First output terminal of clock (clk0) of clock trees module is connected to first and second templates and produces with first input end of clock (clk0) of first input end of clock (clk0) of comparison module, judgement output module, counts first input end of clock (clk0) of step-out reseting module and first input end of clock (clk0) of local encryption module synchronously; The second clock output (clk1) of clock trees module is connected to the second clock input (clk1) of generation of first and second templates and comparison module; The 3rd output terminal of clock (clk2) of clock trees module is connected to the 3rd input end of clock (clk2) of judgement output module; The 4th output terminal of clock (clk500) of clock trees module is connected to the 4th input end of clock (clk500) of judgement output template;

The first input end of multi-user's module (A) is connected outside next selecting side, numerical control multipurpose family respectively with second input (B); The local pseudo noise code of multi-user's module (local PN sign indicating number) input receives the encryption output signal from local encryption module; Multi-user's output of multi-user's module is connected to multi-user's input of generation of first and second templates and comparison module;

Data input pin after the comparison of local encryption module (Dcomp) is connected to the data output end (Dcomp) after the comparison of synchronous counting step-out reseting module;

First template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input (PPMin) of comparison module; First template produces and the pattern control input end (modctrl) of comparison module is connected to power supply (Vdd); First template produces this signal input part of Q that is connected to the judgement output module with this signal output part of Q that compares template; First template produces the Q external signal input that is connected to the judgement output module with the Q external signal output that compares template; First template produces the second pulse position modulation output (relatively back PPM1) after the comparison with template relatively and is connected to the second pulse position modulation input (relatively back PPM1) after the comparison of synchronous counting step-out reseting module;

Second template produces the pulse position modulation input signal that receives the outside with system's pulse position modulation input (PPMin) of comparison module; Second template produces and the pattern control input end (modctrl) of comparison module is connected to ground (Vss); Second template produces the first pulse position modulation output (relatively back PPM0) after the comparison with template relatively and is connected to the first pulse position modulation input (relatively back PPM0) after the comparison of synchronous counting step-out reseting module;

Synchronously counting step-out reseting module enable output (en) be connected to first and second templates produce with comparison module enable input (en) and judgement output module enable input (en); External reset signal (Reset) is connected to the RESET input (Reset) of synchronous counting step-out reseting module;

The data output end (Dataout) of judgement output template is the later data output end of demodulator conclusive judgement; The data clock output (clkout) of judgement output template is the later data clock output of demodulator conclusive judgement.

2. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps, it is characterized in that: said multi-user's module comprises first AND circuit and first OR circuit;

First AND circuit is sent in the local pseudo noise code and the first multi-user selecting side from local encryption module, and the output of first AND circuit and the second multi-user selecting side are sent into first OR circuit together, and the output of first OR circuit is multi-user's output.

3. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said local encryption module comprises second AND circuit, 8 frequency dividing circuits and local pseudo noise code and produces circuit;

First clock signal from data-signal after the comparison of synchronous counting step-out reseting module and the output of clock trees module is sent into second AND circuit; The output of second AND circuit is through 8 frequency dividing circuits; Deliver to local pseudo noise code again and produce circuit, the output that last local pseudo noise code produces circuit is to encrypt output.

4. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said first template generation and comparison module and second template produce with each self-contained half adder circuit of comparison module, pulse position modulation and produce circuit, the first d type flip flop circuit, 2 serial-parallel conversion circuits, first buffer circuits and comparator circuits;

Multi-user's input signal is sent into half adder circuit with mode control signal, and half adder circuit output is delivered to pulse position modulation and produced circuit; Pulse position modulation produces first clock of the clock of circuit from the output of clock trees module; Pulse position modulation produces the signal of circuit output and delivers to the first d type flip flop circuit, and the clock of the first d type flip flop circuit is from the second clock of clock trees module output; First serial-parallel conversion circuit is sent in the output of the first d type flip flop circuit, and the clock of first serial-parallel conversion circuit is from first clock of clock trees module output; System's pulse position modulation input signal is sent into second serial-parallel conversion circuit, and the clock of second serial-parallel conversion circuit is from output first clock of clock trees module; First buffer circuits is all delivered in 4 tunnel outputs separately of first and second serial-parallel conversion circuits, and the enable signal of first buffer circuits is from the Enable Pin of synchronous counting step-out reseting module; Comparator circuit is delivered in 24 tunnel outputs of first buffer circuits, and the clock of comparator circuit is from first clock of clock trees module output; Comparator circuit is output as the first or second pulse position modulation output after the comparison, and a road in 4 tunnel outputs of first serial-parallel conversion circuit are this output of Q, and a road in 4 tunnel outputs of second serial-parallel conversion circuit are the outer output of Q.

5. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps is characterized in that: said synchronous counting step-out reseting module comprises second OR circuit, counter circuit and the 3rd AND circuit; First and second pulse position modulation signals were sent into second OR circuit after first and second templates produced the comparison of exporting with comparison module; Data-signal after the comparison of second OR circuit output offers local encryption module, and sends into counter circuit simultaneously; The clock of counter circuit is from first clock of clock trees module output, and the input of the 3rd AND circuit is delivered in the output of counter circuit, has reset terminal on the 3rd AND circuit, and the 3rd AND circuit is output as and enables output.

6. pulse position modulation ultra wideband receiver demodulator when multi-user according to claim 1 jumps, it is characterized in that: said judgement output template comprises 3 d type flip flop circuit, same OR circuit, the 4th AND circuit, integrating circuit and second buffer circuits;

Second and the clock of 3d flip-flop circuit all from the 3rd clock signal of clock trees module output; The data of the second d type flip flop circuit are from the Q external signal of first template generation with comparison module, and the data of 3d flip-flop circuit are from first template generation this signal of Q with comparison module; Second and the output of 3d flip-flop circuit send into same OR circuit together, with the clock of OR circuit first clock signal, send into the 4th AND circuit with the output of OR circuit from the output of clock trees module; Another signal of the 4th AND circuit is from the enabling of synchronous counting step-out reseting module, and the output of the 4th AND circuit is sent into the four d flip-flop circuit after through the integrator circuit integration; All from the 4th clock of clock trees module output, the four d flip-flop circuit is output as data output end to the clock of the four d flip-flop circuit and second buffer circuits, and second buffer circuits is output as the data clock output.

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