CN102708788B - Pixel circuit - Google Patents

Abstract

The invention provides a pixel circuit, which relates to the technical field of the display device. The pixel circuit is invented in order to solve the technical problem that the pixel circuit in the prior art has difficulty in realizing high-quality display. The pixel circuit comprises a driving unit, a switch unit, an energy storage unit and an organic light emitting diode (OLED), wherein the first input end of the driving unit is connected with a voltage drain drain (VDD); the second input end of the driving unit is connected with the output end of the switch unit; the output end of the driving unit is connected with the first end of the OLED; the driving unit consists of polysilicon transistors; the first input end of the switch unit inputs a line scanning signal (SCAN); the second input end of the switch unit inputs data voltage (Vdata); the switch unit consists of polysilicon transistors; two ends of the energy storage unit are connected with the driving unit for storing voltage; and the second end of the OLED is earthed. According to the pixel circuit disclosed by the invention, the display quality of the pixel circuit can be improved.

Description

pixel circuit

technical field

The present invention relates to the technical field of display devices, in particular to a pixel circuit.

Background technique

OLED (Organic Light-Emitting Diode, Organic Light-Emitting Diode) organic electroluminescent display is an emerging flat-panel display device. It has the advantages of low power consumption, easy matching with integrated circuit driver, high luminous brightness, wide range of working temperature adaptability, light and thin volume and easy realization of flexible display, etc., and has broad application prospects.

According to different driving methods, OLED can be divided into two types: Passive Matrix Organic Light Emission Display (PMOLED) and Active Matrix Organic Light Emission Display (AMOLED). Although the passive matrix driver has a simple process and low cost, it cannot meet the needs of high-resolution and large-size displays due to shortcomings such as crosstalk, high power consumption, and low lifespan. In contrast, the active matrix drive adds thin film transistors (Thin Film Transistor, TFT) to the panel, so that the pixel unit can emit light within a frame time, so it requires a small drive current and low power consumption. It has a longer lifespan and can meet the needs of large-size displays with high resolution and multiple grayscales.

At present, there are mainly two solutions for the driving circuit of the AMOLED display. One is to use amorphous silicon (a-Si, Amorphous-Silicon) TFT technology; the other is to use polysilicon (p-Si, poly-Silicon) TFT technology.

Although a-Si TFT technology is simple in process and low in cost, its carrier mobility is very small (typically less than 1cm ² /Vs), which cannot provide sufficient driving current; at the same time, amorphous silicon TFT can only provide N type devices, and their stability under long-term stress is also problematic. The polysilicon TFT, because of its high carrier mobility (typically greater than 50cm ² /Vs), has a fast response speed and is easy to realize large-area dynamic video display. At the same time, the high carrier mobility can use polysilicon TFT to integrate the peripheral driving circuit on the display backplane, which greatly reduces the external leads and reduces the complexity of the peripheral driving circuit. At present, polysilicon TFTs are commonly used in the research and development of AMOLED backplanes in the world.

The channel region of a polysilicon TFT is prepared by forming an amorphous silicon layer on a substrate, recrystallizing the amorphous silicon layer to form a polysilicon layer. The method of recrystallization can include, for example: excimer laser annealing (Excimer Laser Annealing, ELA) method, sequential lateral crystallization (Sequential Lateral Solidification, SLS) method, metal induced crystallization (Metal Induced Crystallization, MIC) method, or metal induced lateral Crystallization (Metal Induced Lateral Crystallization, MILC) method.

Among these methods, compared with ELA and SLS technologies, MILC technology has better uniformity of TFT devices, and it is easier to realize the needs of large-size AMOLED display. At the same time, the cost of using MILC technology is also lower. Moreover, compared with the MIC technology, the MILC technology can effectively reduce the pollution of residual metal in the channel region.

At present, the main bottleneck of the AMOLED backplane using MILC technology is that the leakage current of the TFT cannot be reduced. In order to ensure the normal display of each pixel in one frame time, it is necessary to ensure that the leakage current passing through the switching transistor when it is turned off will not make the The voltage value on the storage capacitor drops by more than 1 gray level. However, since there is still a small amount of metal residue in the polysilicon TFT obtained by the MILC method, the leakage current of the TFT is too high, which restricts the realization of high gray scale and high quality display.

Contents of the invention

The technical problem to be solved by the present invention is to provide a pixel circuit, which can reduce the leakage current of the switch transistor and improve the display quality of the pixel circuit.

In order to solve the problems of the technologies described above, the present invention provides technical solutions as follows:

A pixel circuit, comprising: a drive unit, a switch unit, an energy storage unit, and an organic light emitting diode;

The first input end of the drive unit is connected to the power supply voltage, the second input end of the drive unit is connected to the output end of the switch unit, the output end of the drive unit is connected to the first end of the organic light emitting diode, Used to output a current signal for driving the organic light emitting diode to emit light; the driving unit is composed of a polysilicon transistor;

The first input terminal of the switch unit inputs a row scan signal, and the second input terminal of the switch unit inputs a data voltage; the switch unit is composed of an amorphous silicon transistor;

Both ends of the energy storage unit are connected to the drive unit for storing voltage; and

The second end of the OLED is grounded.

The drive unit includes: a polysilicon transistor;

The first input end of the driving unit is the first pole of the polysilicon transistor, the second input end of the driving unit is the gate of the polysilicon transistor, and the output end of the driving unit is the gate of the polysilicon transistor. second pole.

The switch unit includes: an amorphous silicon transistor;

The first input terminal of the switch unit is the gate of the amorphous silicon transistor; the second input terminal of the switch unit is the first pole of the amorphous silicon transistor, and the output terminal of the switch unit is the gate of the amorphous silicon transistor. The second pole of the amorphous silicon transistor.

The first pole of the polysilicon transistor is the drain, and the second pole of the polysilicon transistor is the source; or, the second pole of the polysilicon transistor is the drain, and the first pole of the polysilicon transistor is the source;

The second pole of the amorphous silicon transistor is the drain, and the first pole of the amorphous silicon transistor is the source; or, the first pole of the amorphous silicon transistor is the drain, and the second pole of the amorphous silicon transistor is Very source.

The switch unit includes: a first amorphous silicon transistor, a second amorphous silicon transistor, and a third amorphous silicon transistor;

The first input terminal of the switch unit includes a first sub-input terminal and a second sub-input terminal;

The first sub-input terminal of the switch unit is the gate of the first amorphous silicon transistor and the gate of the second amorphous silicon transistor, respectively connected to the first row scanning signal;

The second sub-input terminal of the switch unit is the gate of the third amorphous silicon transistor, connected to the second row scanning signal;

The second input terminals of the switch unit are respectively the first pole of the first amorphous silicon transistor and the first pole of the third amorphous silicon transistor;

The output end of the switch unit is the second pole of the first amorphous silicon transistor;

The second pole of the third amorphous silicon transistor is connected to the first pole of the second amorphous silicon transistor, and the second pole of the second amorphous silicon transistor is connected to the output terminal of the driving unit.

The first pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the source; or, the second pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the drain. a first electrode of an amorphous silicon transistor;

The first pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the source; or, the second pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the drain. The first pole of the two amorphous silicon transistors is the source;

The first pole of the third amorphous silicon transistor is the drain, and the second pole of the third amorphous silicon transistor is the source; or, the second pole of the third amorphous silicon transistor is the drain, and the second pole of the third amorphous silicon transistor is the drain. The first pole of the three amorphous silicon transistors is the source.

The driving unit includes: a first polysilicon transistor and a second polysilicon transistor;

The switch unit includes: a first amorphous silicon transistor, a second amorphous silicon transistor;

The first input terminal of the driving unit is the first pole of the second polysilicon transistor; the second input terminal of the driving unit is the gate of the second polysilicon transistor; The output terminal is the second pole of the second polysilicon transistor;

The first input terminal of the switch unit is the gate of the first amorphous silicon transistor; the second input terminal of the switch unit is the first pole of the first amorphous silicon transistor;

The output terminal of the switch unit is the second pole of the second amorphous silicon transistor;

The first pole of the second amorphous silicon transistor is connected to the first pole of the first amorphous silicon transistor; the gate of the second amorphous silicon transistor is connected to the gate of the first amorphous silicon transistor connect;

The gate of the second polysilicon transistor is connected to the gate of the first polysilicon transistor, and the first pole of the second polysilicon transistor is connected to the first pole of the first polysilicon transistor. connect;

The second pole of the first amorphous silicon transistor is connected to the second pole of the first polysilicon transistor.

The first pole of the first polysilicon transistor is the drain, and the second pole of the first polysilicon transistor is the source; or, the second pole of the first polysilicon transistor is the drain, and the second pole of the first polysilicon transistor is the drain. a first pole source of a polysilicon transistor;

The first pole of the second polysilicon transistor is the drain, and the second pole of the second polysilicon transistor is the source; or, the second pole of the second polysilicon transistor is the drain, and the second pole of the second polysilicon transistor is the drain. The first pole of the polysilicon transistor is the source;

The first pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the source; or, the second pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the drain. a first electrode of an amorphous silicon transistor;

The first pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the source; or, the second pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the drain. The first pole of the two amorphous silicon transistors is the source.

The energy storage unit includes any combination of one or more of the following capacitors:

a first capacitor, the first end of the first capacitor is connected to a power supply voltage, and the second end of the first capacitor is connected to the second input end of the drive unit;

a second capacitor, the first end of the second capacitor is connected to a power supply voltage, and the second end of the second capacitor is connected to the output end of the drive unit;

A third capacitor, the first terminal of the third capacitor is connected to the second input terminal of the driving unit, and the second terminal of the third capacitor is connected to the output terminal of the driving unit.

The energy storage unit includes any combination of one or more of the following capacitors:

a first capacitor, the first end of the first capacitor is connected to the second input end of the drive unit; the second end of the first capacitor is connected to the second pole of the third amorphous silicon transistor;

A second capacitor, the first end of the second capacitor is connected to the power supply voltage; the second end of the second capacitor is connected to the second pole of the third amorphous silicon transistor.

The polysilicon transistor is formed by a metal-induced lateral crystallization MILC process.

The present invention has the following beneficial effects:

In the above solution, the pixel circuit includes: a drive unit, a switch unit, an energy storage unit, and an organic light emitting diode OLED; the first input terminal of the drive unit is connected to the power supply voltage VDD, and the second input terminal of the drive unit is connected to the switch The output end of the unit is connected, the output end of the driving unit is connected to the first end of the OLED, and is used to output the current signal for driving the OLED to emit light; the first input end of the switching unit inputs the row scanning signal SCAN, so The second input end of the switch unit inputs data voltage Vdata; the two ends of the energy storage unit are connected to the drive unit for storing voltage; the second end of the OLED is grounded. Since the driving unit is composed of polysilicon transistors; the switching unit is composed of amorphous silicon transistors; the leakage current of amorphous silicon transistors is usually less than 10 ^-13 A, thereby effectively reducing the leakage current of switching transistors, thereby improving the pixel The display quality of the circuit.

Description of drawings

FIG. 1 is a schematic connection diagram of a first embodiment of a pixel circuit according to the present invention;

FIG. 2 is a schematic connection diagram of a second embodiment of a pixel circuit according to the present invention;

FIG. 3 is a timing diagram of a second embodiment of a pixel circuit according to the present invention;

FIG. 4 is a schematic connection diagram of a third embodiment of a pixel circuit according to the present invention;

5 is a schematic connection diagram of a fourth embodiment of a pixel circuit according to the present invention;

6-13 are top views in the process flow corresponding to the second embodiment of a pixel circuit according to the present invention;

FIG. 14 is a corresponding cross-sectional view of the second embodiment of a pixel circuit according to the present invention.

Detailed ways

In order to make the technical problems, technical solutions and advantages to be solved by the embodiments of the present invention clearer, the following will describe in detail with reference to the drawings and specific embodiments.

As shown in FIG. 1 , it is a pixel circuit according to the present invention, including: a driving unit 10 , a switching unit 20 , an energy storage unit 30 and an organic light emitting diode OLED 40 .

The first input end of the drive unit 10 is connected to the power supply voltage VDD, the second input end of the drive unit 10 is connected to the output end of the switch unit 20, and the output end of the drive unit 10 is connected to the OLED 40. The first end is used to output a current signal for driving the OLED to emit light; the driving unit 10 is composed of polysilicon transistors.

The first input terminal of the switch unit 20 inputs the row scan signal SCAN, and the second input terminal of the switch unit 20 inputs the data voltage Vdata; the switch unit 20 is composed of an amorphous silicon transistor.

Both ends of the energy storage unit 30 are connected to the drive unit for storing voltage.

The second terminal of the OLED is grounded to GND.

A first embodiment of the present invention is described below.

As shown in FIG. 2, the driving unit 10 includes: a polysilicon transistor T1;

The first input terminal of the driving unit 10 is the first pole of the polysilicon transistor T1, the second input terminal of the driving unit 10 is the gate of the polysilicon transistor T1, and the output terminal of the driving unit 10 is The second pole of the polysilicon transistor T1.

The switch unit 20 includes an amorphous silicon transistor T2.

The first input terminal of the switch unit 20 is the gate of the amorphous silicon transistor T2; the second input terminal of the switch unit 20 is the first pole of the amorphous silicon transistor T2, and the switch unit 20 The output terminal of is the second pole of the amorphous silicon transistor T2.

Optionally, the first pole of the polysilicon transistor T1 is a drain, and the second pole of the polysilicon transistor T1 is a source; or, the second pole of the polysilicon transistor T1 is a drain, and the first pole of the polysilicon transistor T1 is a drain. Very source.

The second electrode of the amorphous silicon transistor T2 is the drain, and the first electrode of the amorphous silicon transistor T2 is the source; or, the first electrode of the amorphous silicon transistor T2 is the drain, and the amorphous silicon transistor The second pole of T2 is the source.

The energy storage unit includes any combination of one or more of the following capacitors:

A first capacitor C _S , the first end of the first capacitor C _S is connected to the power supply voltage VDD, and the second end of the first capacitor C _S is connected to the second input end of the driving unit;

A second capacitor C1 (not shown in FIG. 2 ), the first end of the second capacitor C1 is connected to the power supply voltage VDD, and the second end of the second capacitor C1 is connected to the output end of the driving unit;

A third capacitor C2 (not shown in FIG. 2 ), the first end of the third capacitor C2 is connected to the second input end of the drive unit, and the second end of the third capacitor C2 is connected to the output of the drive unit end.

In this embodiment, the polysilicon transistor T1 is used as a driving tube, and its function is to provide a current signal for driving the OLED to emit light; the amorphous silicon transistor T2 is used as a switching tube, and the row scanning signal is applied to the gate of the T2 tube to control the flow of the data voltage. ; The capacitor _CS stores the data voltage in the form of a voltage.

Wherein, the gate of the polysilicon TFT T1 is connected to the drain of the amorphous silicon TFT T2, the source of the polysilicon TFT T1 is connected to the first power supply with a certain potential, and the drain of the polysilicon TFT T1 is connected to the organic light emitting diode OLED The gate of the amorphous silicon TFT transistor T2 is connected to the row scanning signal line SCAN, the drain of the amorphous silicon TFT transistor T2 is connected to the gate of the polysilicon TFT transistor T1, and the source of the amorphous silicon TFT transistor T2 The pole is connected with the data signal line DATA; the first electrode of the organic light emitting diode OLED is connected with the drain of the polysilicon TFT tube T1, and the second electrode of the organic light emitting diode OLED is grounded; the first electrode of the storage capacitor _CS is connected with the polysilicon TFT tube T1 The gate is connected, and the second electrode of the storage capacitor _CS is connected to VDD.

FIG. 3 is a timing diagram of the pixel circuit shown in FIG. 2 . The pixel circuit works as follows:

In the gate phase, the SCAN signal turns on the switching transistor T2, and the voltage signal on the data voltage line DATA is applied to the gate of the driving transistor T1 through the transistor T2, and at the same time, the data voltage line DATA charges the storage capacitor _CS . In the stable stage, controlled by the data voltage Vdata, the current output from the transistor T1 to the OLED is equal to:

I _OLED = 1/2 u _n COX(W/L) _T1 (Vdata-V _TH ) ² ;

In the formula, I _OLED is the current value output by the transistor T1 to the OLED; u _n is the carrier mobility of the transistor T1; C _OX is the capacitance per unit area of the gate insulating layer of the transistor T1; W is the channel width of the transistor T1; L is the tube channel length of the crystal T1; V _TH is the threshold voltage of the transistor T1; VDD is the first power supply value of about 5V given by the external power supply.

In the holding phase, the SCAN signal turns off the switching transistor T2. At this time, due to the existence of the storage capacitor _CS , the gate signal of the driving transistor T1 is not affected by the turning off of T2, and is still Vdata, so as to ensure that it is in the whole off stage, there is current to continuously drive the OLED.

However, there is a leakage current I _leakage when the transistor T2 is turned off. Therefore, in the holding phase, as the charge leaks from the transistor T2, the gate potential of the transistor T2 gradually decreases, and the current driving the OLED also gradually decreases.

The drop value V of the gate potential can be calculated by the following formula:

V=Q/C _s =I _leakage *t/C _s .

Among them, Cs is the capacitance value of the storage capacitor; Q is the amount of charge lost due to charge leakage; t is the duration of the hold phase.

Usually the refresh rate of the screen is 60Hz, so t=1/60s=16.67ms. In order to achieve high-quality, high-gray-scale display, it is necessary to ensure that the brightness drop of the OLED is not higher than the recognizable range of the human eye (usually 10 gray-scale), and the leakage current of T2 is required to be greater than 10 ^-12 A. The leakage current of the amorphous silicon TFT used in the invention is less than 10 ^-13 A, and the turn-off characteristic is good, which meets the design requirement.

In addition, the present invention adopts the MILC method to prepare low-temperature polysilicon TFTs, which have high carrier mobility and are used as driving transistors for OLEDs. The present invention utilizes MILC technology to realize regional crystallization, combines the advantages of MILC low-temperature polysilicon TFTs and amorphous silicon TFTs, and uses MILC crystallization technology to make the drive tube T1 into a low-temperature polysilicon TFT, while the switch tube T2 is designed to be amorphous Silicon TFT, while ensuring that it can drive OLED, effectively reduces the leakage current and improves the stability of the circuit in the holding phase.

A second embodiment of the present invention is described below.

As shown in FIG. 4, the first input end of the driving unit 10 is the first pole of the polysilicon transistor A1, the second input end of the driving unit 10 is the gate of the polysilicon transistor T1, and the driving The output terminal of the unit 10 is the second pole of the polysilicon transistor T1.

The switch unit 20 includes: a first amorphous silicon transistor A2, a second amorphous silicon transistor A3, and a third amorphous silicon transistor A4;

The first input terminal of the switch unit 20 includes a first sub-input terminal and a second sub-input terminal;

The first sub-input terminal of the switch unit 20 is the gate of the first amorphous silicon transistor A2 and the gate of the second amorphous silicon transistor A3, respectively connected to the first row scanning signal SCAN1;

The second sub-input terminal of the switch unit 20 is the gate of the third amorphous silicon transistor A4, which is connected to the second row scanning signal SCAN2;

The second input terminals of the switch unit 20 are respectively the first pole of the first amorphous silicon transistor A2 and the first pole of the third amorphous silicon transistor A4;

The output end of the switch unit 20 is the second pole of the first amorphous silicon transistor A2;

The second pole of the third amorphous silicon transistor A4 is connected to the first pole of the second amorphous silicon transistor A3, and the second pole of the second amorphous silicon transistor A3 is connected to the output end of the driving unit.

The first pole of the first amorphous silicon transistor A2 is the drain, and the second pole of the first amorphous silicon transistor A2 is the source; or, the second pole of the first amorphous silicon transistor A2 is the drain, The first pole of the first amorphous silicon transistor A2 is the source;

The first electrode of the second amorphous silicon transistor A3 is a drain, the second electrode of the second amorphous silicon transistor A3 is a source; or, the second electrode of the second amorphous silicon transistor A3 is a drain, The first pole of the second amorphous silicon transistor A3 is the source;

The first pole of the third amorphous silicon transistor A4 is the drain, the second pole of the third amorphous silicon transistor A4 is the source; or, the second pole of the third amorphous silicon transistor A4 is the drain, The first pole of the third amorphous silicon transistor A4 is the source.

The energy storage unit includes any combination of one or more of the following capacitors:

A first capacitor _CS (not shown in FIG. 4 ), the first end of the first capacitor _CS is connected to the power supply voltage VDD, and the second end of the first capacitor _CS is connected to the second input end of the drive unit ;

A second capacitor C1 (not shown in FIG. 4 ), the first end of the second capacitor C1 is connected to the power supply voltage VDD, and the second end of the second capacitor C1 is connected to the output end of the driving unit;

A third capacitor C2 (not shown in FIG. 4 ), the first end of the third capacitor C2 is connected to the second input end of the drive unit, and the second end of the third capacitor C2 is connected to the output of the drive unit end.

Alternatively, the energy storage unit includes any combination of one or more of the following capacitors:

A first capacitor, the first end of the first capacitor C1 is connected to the second input end of the drive unit; the second end of the first capacitor is connected to the second pole of the third amorphous silicon transistor A4;

A second capacitor, the first end of the second capacitor C2 is connected to the power supply voltage; the second end of the second capacitor is connected to the second pole of the third amorphous silicon transistor A4.

In the above embodiment, the three TFTs A2, A3, and A4 form a switching unit, which may be composed of amorphous silicon TFTs; TFTA1 forms a driving unit, which may be composed of low-temperature polysilicon TFTs.

A third embodiment of the present invention is described below.

As shown in FIG. 5, the driving unit 10 includes: a first polysilicon transistor DR1, a second polysilicon transistor DR2;

The switch unit 20 includes: a first amorphous silicon transistor SW1, a second amorphous silicon transistor SW2;

The first input terminal of the driving unit 10 is the first pole of the second polysilicon transistor DR2; the second input terminal of the driving unit is the gate of the second polysilicon transistor DR2; the The output end of the driving unit is the second pole of the second polysilicon transistor DR2;

The first input terminal of the switch unit 20 is the gate of the first amorphous silicon transistor SW1; the second input terminal of the switch unit is the first pole of the first amorphous silicon transistor SW1;

The output terminal of the switch unit 20 is the second pole of the second amorphous silicon transistor SW2;

The first pole of the second amorphous silicon transistor SW2 is connected to the first pole of the first amorphous silicon transistor SW1; the gate of the second amorphous silicon transistor SW2 is connected to the first pole of the first amorphous silicon transistor SW2 Gate connection of SW1;

The gate of the second polysilicon transistor DR2 is connected to the gate of the first polysilicon transistor DR1, and the first pole of the second polysilicon transistor DR2 is connected to the first pole of the first polysilicon transistor DR1. The first pole connection;

The second pole of the first amorphous silicon transistor SW1 is connected to the second pole of the first polysilicon transistor DR1 .

Optionally, the first pole of the first polysilicon transistor DR1 is the drain, and the second pole of the first polysilicon transistor DR1 is the source; or, the second pole of the first polysilicon transistor DR1 is The pole is the drain, and the first pole of the first polysilicon transistor DR1 is the source;

The first pole of the second polysilicon transistor DR2 is the drain, and the second pole of the second polysilicon transistor DR2 is the source; or, the second pole of the second polysilicon transistor DR2 is the drain, The first pole of the second polysilicon transistor DR2 is the source;

The first pole of the first amorphous silicon transistor SW1 is the drain, and the second pole of the first amorphous silicon transistor SW1 is the source; or, the second pole of the first amorphous silicon transistor SW1 is the drain, The first pole of the first amorphous silicon transistor SW1 is the source;

The first pole of the second amorphous silicon transistor SW2 is the drain, the second pole of the second amorphous silicon transistor SW2 is the source; or, the second pole of the second amorphous silicon transistor SW2 is the drain, The first pole of the second amorphous silicon transistor SW2 is the source.

The energy storage unit includes any combination of one or more of the following capacitors:

The first capacitor _CS (not shown in FIG. 5 ), the first terminal of the first capacitor _CS is connected to the power supply voltage VDD, and the second terminal of the first capacitor _CS is connected to the second input terminal of the driving unit ;

A second capacitor C1, the first terminal of the second capacitor C1 is connected to the power supply voltage VDD, and the second terminal of the second capacitor C1 is connected to the output terminal of the driving unit;

The third capacitor C2, the first terminal of the third capacitor C2 is connected to the second input terminal of the driving unit, and the second terminal of the third capacitor C2 is connected to the output terminal of the driving unit.

In the above embodiment, the TFTs SW1 and SW2 form the switching unit, which may be composed of amorphous silicon TFTs; the TFTs DR1 and DR2 are the driving units, which are composed of low-temperature polysilicon TFTs.

Wherein, the polysilicon transistor described in the present invention is formed by a metal-induced lateral crystallization MILC process.

In each of the above embodiments, the control electrode of the transistor corresponds to the gate of the TFT, and the first current conduction electrode and the second current conduction electrode are reciprocal, that is, the first current conduction electrode can be the source or is the drain, and correspondingly, the second current conduction electrode may be the drain or the source.

The present invention proposes a pixel circuit of an organic electroluminescent display device, using MILC technology to prepare a TFT transistor with high consistency, and effectively reducing the leakage current of the TFT transistor through pixel design, thereby improving the image grayscale of the OLED display device level and display quality of the screen. On the basis of maintaining the advantages of high uniformity and low cost of MILC low-temperature polysilicon TFT, the present invention achieves the technical effect of reducing the leakage current of switching transistors by controlling the technical means of the crystallization area, thereby solving the problem that the AMOLED backplane prepared by MILC technology cannot Technical problems in realizing high gray scale display. The pixel circuit of the present invention can be prepared by using metal lateral induced crystallization (MILC) technology. Through the technical means of controlling the crystallization area, the technical effect of reducing the leakage current of the switching transistor is achieved, thereby solving the technical problem that the AMOLED backplane prepared by MILC technology cannot realize high grayscale display.

The pixel circuit described in the present invention can be prepared by using MILC technology. The method for preparing the pixel circuit described in the present invention will be introduced below in conjunction with the layout of the unit pixel circuit shown in FIGS. 6 to 13 and the circuit cross-sectional view shown in FIG. 14 .

6 to 13 are top views of the pixel circuit shown in FIG. 2 in the process flow. The manufacturing process includes the following steps:

First, as shown in Figure 6, a buffer layer 1 is grown on a glass substrate; an active layer (a-Si thin film) is grown; the active layer is etched to form an active trench made of an amorphous silicon thin film Road District 2-1.

Then, as shown in Figure 7, photolithography and deposition of the induced precursor metal layer 3, in this implementation, Ni is preferred as the precursor metal; the induced precursor metal layer 3 formed by MILC technology can be metals such as Ni, Cu, etc. crystallization temperature.

Then, as shown in FIG. 8, the active region is crystallized using MILC technology to form an active channel region 2-2 made of low-temperature polysilicon; grow a gate insulating layer; deposit the first metal layer; etch the first The metal layer and the gate insulating layer form the gate insulating layer of the transistor T1, the gate insulating layer of the transistor T2, the gate electrode 5-1 of the transistor T1, the gate electrode 5-2 of the transistor T2, and the first electrode 5 of the storage capacitor Cs -3, scanning signal line VSEL5-4;

Then, as shown in FIG. 9 , the source and drain regions are ion-implanted to form the transistor source and drain regions, and the transistor source and drain regions include: the source and drain regions of the transistor T1 and the source and drain regions of the transistor T2; wherein, the source and drain regions of the transistor T1 include transistors Source region 6-11 of T1 and drain region 6-12 of transistor T1; source-drain region of transistor T2 includes source region 6-21 of transistor T2 and drain region 6-22 of transistor T2; annealing to activate implanted ions; deposition of dielectric layer; etching to form a contact hole 8;

Then, as shown in FIG. 10, deposit a second metal layer; etch the source and drain metal to form the source and drain electrodes of the T1 transistor, the source and drain electrodes of the transistor T2, the second electrode 9-3 of the storage capacitor _CS , and the data signal line Vdata 9-4, power signal line VDD 9-5; the source and drain electrodes of the T1 transistor include: the source electrode 9-11 of the transistor T1, the drain electrode 9-12 of the transistor T1; the source and drain electrodes 2 of the transistor T2 include: The source electrode 9-21 of the transistor T2, the drain electrode 9-22 of the transistor T2;

Then, as shown in FIG. 11 , grow a planarization layer, and etch a stroke via hole 11;

Then, as shown in FIG. 12 , a transparent conductive electrode ITO layer is deposited, and the ITO is etched to form an ITO region 12;

Then, as shown in FIG. 13 , an OLED layer 13 is vapor-deposited.

A cross-sectional view of the completed pixel circuit is shown in FIG. 14 .

In FIG. 14, the buffer layer 1 can be silicon dioxide SiO2, silicon nitride SiNX, or a double-layer structure formed by overlapping the two.

The active layer of the transistor includes: a transistor active channel region 2-1 made of amorphous silicon (a-Si) and a transistor active channel region 2-1 made of low-temperature polysilicon (LTPS) formed by MILC crystallization technology 2.

The gate insulating layer can be silicon dioxide SiO2, silicon nitride SiNX, or a double-layer structure formed by overlapping the two. The gate insulating layer includes: a gate insulating layer of the T1 transistor, a gate insulating layer of the T2 transistor, and a first metal layer.

The first metal layer is used to form the gate electrode, the VSEL pattern and the first electrode of the storage capacitor Cs, and may be other metal or alloy materials such as Mo. The first metal layer includes: a gate electrode 5-1 of the transistor T1, a gate electrode 5-2 of the transistor T2, a first electrode 5-3 of the storage capacitor Cs, and a scanning signal line VSEL5-4.

The source and drain regions of the transistor (heavily doped transistor source and drain regions formed by ion implantation) include the source and drain regions of the transistor T1, the source and drain regions of the transistor T2, the dielectric layer 7, the source and drain contact holes 8, and the second metal layer .

The source and drain regions of the transistor T1 include a source region 6-11 of the transistor T1 and a drain region 6-12 of the transistor T1.

The source and drain regions of the transistor T2 include a source region 6-21 of the transistor T2 and a drain region 6-22 of the transistor T2.

The dielectric layer 7 can be silicon dioxide SiO2, silicon nitride SiNX, or a double-layer structure formed by overlapping the two.

The source-drain contact hole 8 realizes the connection of the upper and lower metal layers by etching the insulating layer in a designated area.

The second metal layer is used to form the source-drain electrodes, Vdata, VDD patterns, and the second electrode of the storage capacitor Cs, and may be other metals or alloy materials such as Mo.

The second metal layer includes the source-drain electrodes of the T1 transistor, the source-drain electrodes 9-2 of the transistor T2, the second electrode 9-3 of the storage capacitor CS, the data signal line Vdata 9-4, the power signal line VDD9-5, and planarization Layer 10, planarization layer via hole 11, transparent conductive electrode ITO layer 12, organic light emitting layer 13.

The source and drain electrodes of the T1 transistor include: the source electrode 9-11 of the transistor T1, and the drain electrode 9-12 of the transistor T1.

The source and drain electrodes of the transistor T2 include the source electrode 9-21 of the transistor T2 and the drain electrode 9-22 of the transistor T2.

The planarization layer 10 can be silicon dioxide SiO2, silicon nitride SiNX, or a double-layer structure formed by overlapping them.

The planarization layer via hole 11 realizes the connection between the ITO layer and the second metal layer by etching the planarization layer in a designated area.

The transparent conductive electrode ITO layer 12 is a transparent conductive thin film indium tin oxide (Indium-Tin Oxide, ITO).

The organic light emitting layer 13 is an organic light emitting diode (Organic Light Emitting Diode, OLED) composed of multilayer organic thin films.

The present invention utilizes the technical means of MILC technology to realize regional crystallization, combines the respective advantages of low-temperature polysilicon TFT and amorphous silicon TFT, utilizes MILC technology to prepare TFT transistors with high consistency, and effectively reduces the leakage current of TFT transistors through pixel design , so as to improve the image gray level and the display quality of the picture of the OLED display device.

The above description is a preferred embodiment of the present invention. It should be pointed out that for those of ordinary skill in the art, some improvements can be made without departing from the principle of the present invention, and these improvements should also be regarded as the present invention. protection scope of the invention.

Claims (7)

1. A pixel circuit, comprising: a drive unit, a switch unit, an energy storage unit, and an organic light emitting diode; The first input end of the drive unit is connected to the power supply voltage, the second input end of the drive unit is connected to the output end of the switch unit, the output end of the drive unit is connected to the first end of the organic light emitting diode, Used to output a current signal for driving the organic light emitting diode to emit light; the driving unit is composed of a polysilicon transistor; The first input terminal of the switch unit inputs a row scan signal, and the second input terminal of the switch unit inputs a data voltage; Both ends of the energy storage unit are connected to the drive unit for storing voltage; and The second terminal of the organic light emitting diode is grounded; The drive unit includes: a polysilicon transistor; The first input end of the driving unit is the first pole of the polysilicon transistor, the second input end of the driving unit is the gate of the polysilicon transistor, and the output end of the driving unit is the gate of the polysilicon transistor. second pole; The switch unit includes: a first amorphous silicon transistor, a second amorphous silicon transistor, and a third amorphous silicon transistor; The first input terminal of the switch unit includes a first sub-input terminal and a second sub-input terminal; The first sub-input terminal of the switch unit is the gate of the first amorphous silicon transistor and the gate of the second amorphous silicon transistor, respectively connected to the first row scanning signal; The second sub-input terminal of the switch unit is the gate of the third amorphous silicon transistor, connected to the second row scanning signal; The second input terminals of the switch unit are respectively the first pole of the first amorphous silicon transistor and the first pole of the third amorphous silicon transistor; The output end of the switch unit is the second pole of the first amorphous silicon transistor; The second pole of the third amorphous silicon transistor is connected to the first pole of the second amorphous silicon transistor, and the second pole of the second amorphous silicon transistor is connected to the output terminal of the driving unit. 2. The pixel circuit according to claim 1, wherein the switch unit comprises: an amorphous silicon transistor; The first input terminal of the switch unit is the gate of the amorphous silicon transistor; the second input terminal of the switch unit is the first pole of the amorphous silicon transistor, and the output terminal of the switch unit is the gate of the amorphous silicon transistor. The second pole of the amorphous silicon transistor. 3. The pixel circuit according to claim 2, characterized in that, The first pole of the polysilicon transistor is the drain, and the second pole of the polysilicon transistor is the source; or, the second pole of the polysilicon transistor is the drain, and the first pole of the polysilicon transistor is the source; The second pole of the amorphous silicon transistor is the drain, and the first pole of the amorphous silicon transistor is the source; or, the first pole of the amorphous silicon transistor is the drain, and the second pole of the amorphous silicon transistor is Very source. 4. The pixel circuit according to claim 1, characterized in that, The first pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the source; or, the second pole of the first amorphous silicon transistor is the drain, and the second pole of the first amorphous silicon transistor is the drain. a first electrode of an amorphous silicon transistor; The first pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the source; or, the second pole of the second amorphous silicon transistor is the drain, and the second pole of the second amorphous silicon transistor is the drain. The first pole of the two amorphous silicon transistors is the source; The first pole of the third amorphous silicon transistor is the drain, and the second pole of the third amorphous silicon transistor is the source; or, the second pole of the third amorphous silicon transistor is the drain, and the second pole of the third amorphous silicon transistor is the drain. The first pole of the three amorphous silicon transistors is the source. 5. The pixel circuit according to claim 1, wherein the energy storage unit comprises any combination of one or more of the following capacitors: a first capacitor, the first end of the first capacitor is connected to a power supply voltage, and the second end of the first capacitor is connected to the second input end of the drive unit; a second capacitor, the first end of the second capacitor is connected to a power supply voltage, and the second end of the second capacitor is connected to the output end of the drive unit; A third capacitor, the first terminal of the third capacitor is connected to the second input terminal of the driving unit, and the second terminal of the third capacitor is connected to the output terminal of the driving unit. 6. The pixel circuit according to claim 1, wherein the energy storage unit comprises any combination of one or more of the following capacitors: a first capacitor, the first end of the first capacitor is connected to the second input end of the drive unit; the second end of the first capacitor is connected to the second pole of the third amorphous silicon transistor; A second capacitor, the first end of the second capacitor is connected to the power supply voltage; the second end of the second capacitor is connected to the second pole of the third amorphous silicon transistor. 7. The pixel circuit according to claim 1, wherein the polysilicon transistor is formed by a metal-induced lateral crystallization (MILC) process.