CN102707756B - A kind of wide load linearity adjustor using dynamic ESR to compensate resistance - Google Patents
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance Download PDFInfo
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Abstract
The present invention be more particularly directed to a kind of wide load linearity adjustor using dynamic ESR to compensate resistance, including band-gap reference section and LDO loop segments, described LDO loop compensates resistance as dynamic adjustable resistance by the dynamic ESR of Mc equivalence, the change of load, the position of ESR equivalent resistance regulation system zero point is followed according to the input stage level of Buffer.It is stable at loading range inner ring road quickly that this programme achieves LDO system, and substantially increases system bandwidth, has speeded loop response speed.
Description
Technical field
The present invention relates to electricity field, particularly to a kind of wide load linearity adjustor using dynamic ESR to compensate resistance.
Background technology
The acp chip processing speeds such as modern electronic equipment quickly grows, processor carry soon day by day, conventional linear manipulator
(LDO) loop bandwidth is little, and response speed is slow, and load capacity is poor, cannot meet the contemporary electronic systems that performance improves day by day
Requirement, and the noise of Switching Power Supply and bigger output ripple cannot meet requirement in a lot of high-precision applications fields.
Summary of the invention
Being to provide the wide load linearity adjustor of a kind of heavy load ability, it compensates resistance by ESR the mesh of the present invention
It is stable at loading range inner ring road quickly that compensation technique achieves LDO system, and substantially increases system bandwidth, has speeded ring
Road response speed.
For achieving the above object, the technical solution used in the present invention is:
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance, it is characterised in that include band-gap reference section
With LDO loop segments, described LDO loop compensates resistance as dynamic adjustable resistance, foundation by the dynamic ESR of Mc equivalence
The input stage level of Buffer follows the change of load, the position of ESR equivalent resistance regulation system zero point.
The formula of described ESR equivalent resistance regulation system dead-center position is as follows:
Described band-gap reference section includes three bipolar transistors, seven p-type metal-oxide-semiconductors, an amplifier, an electric current leakage
With two resistance.
The concrete components and parts of described band-gap reference section connect as follows:
The input that the grid of the 0th p-type metal-oxide-semiconductor MP0, the drain electrode of the 0th p-type metal-oxide-semiconductor MP0 are leaked with electric current is connected；First
Operational amplifier A 1 outfan, the grid of the first p-type metal-oxide-semiconductor MP1, the grid of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor
The grid of MP3 connects；The drain electrode of the first p-type metal-oxide-semiconductor MP1 is connected with the source electrode of the 4th p-type metal-oxide-semiconductor MP4；Second p-type metal-oxide-semiconductor
The drain electrode of MP2 is connected with the source electrode of the 5th p-type metal-oxide-semiconductor MP5；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3 is with the 6th p-type metal-oxide-semiconductor MP6's
Source electrode connects；The in-phase input end of the first operational amplifier A 1, the drain electrode of the 5th p-type metal-oxide-semiconductor MP5, one end of resistance R1 connect；
The inverting input of the first operational amplifier A 1, the drain electrode of the 4th p-type metal-oxide-semiconductor MP4 and the collection of the first p-type bipolar transistor Q1
Electrode connects；The other end of resistance R1 and the colelctor electrode of the second p-type bipolar transistor Q2 connect；6th p-type metal-oxide-semiconductor MP6's
Drain electrode, one end of resistance R2 are connected with bandgap voltage reference outfan Vref；The other end of resistance R2 and the 3rd ambipolar crystalline substance of p-type
The colelctor electrode of body pipe Q3 connects；
The source electrode of the 0th p-type metal-oxide-semiconductor MP0, the source electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2,
The source electrode of three p-type metal-oxide-semiconductor MP3 is connected with power vd D；
Electric current leakage outfan, the base stage of the first p-type bipolar transistor Q1, the first p-type bipolar transistor Q1 send out
Emitter-base bandgap grading, the base stage of the second p-type bipolar transistor Q2, the emitter stage of the second p-type bipolar transistor Q2, the 3rd p-type are ambipolar
The base stage of transistor Q3, the emitter stage of the 3rd p-type bipolar transistor Q3 are connected with ground GND.
Described LDO loop segments includes two electric capacity, two resistance, 11 p-type metal-oxide-semiconductors and six N-type metal-oxide-semiconductors.
The described concrete components and parts of LDO loop segments connect as follows:
The source electrode of the first p-type metal-oxide-semiconductor P1, the source electrode of the 4th p-type metal-oxide-semiconductor P4, the grid of the 6th p-type metal-oxide-semiconductor P6, the 7th P
The grid of type metal-oxide-semiconductor P7, the source electrode of the 5th p-type metal-oxide-semiconductor P5, one end of electric capacity C, the source electrode of the 8th p-type metal-oxide-semiconductor P8 and resistance R1
One end connect；The drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the source electrode of the 3rd p-type metal-oxide-semiconductor MP3
Connect；The grid of the second p-type metal-oxide-semiconductor MP2, one end of R2 are connected with one end of R3；The grid of the 3rd p-type metal-oxide-semiconductor MP3 and benchmark
Voltage Vref connects；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 and the leakage of the first N-type metal-oxide-semiconductor MN1
Pole connects；The drain electrode of the drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 and the second N-type metal-oxide-semiconductor MN2 is even
Connect；The grid of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5, drain electrode and the 3rd N-type of the 6th p-type metal-oxide-semiconductor MP6
The drain electrode of metal-oxide-semiconductor MN3 connects；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th p-type metal-oxide-semiconductor MP6；5th p-type
The drain electrode of metal-oxide-semiconductor MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；The drain electrode of the 7th p-type metal-oxide-semiconductor MP7, the 4th N-type metal-oxide-semiconductor
The drain electrode of MN4, the grid of the 9th p-type metal-oxide-semiconductor MP9 are connected with the source electrode of p-type metal-oxide-semiconductor Mc；The drain electrode of the 8th p-type metal-oxide-semiconductor MP8,
The source electrode of the 9th p-type metal-oxide-semiconductor MP9 and the grid of the 7th N-type metal-oxide-semiconductor MN7 connect；The source electrode of the 7th N-type metal-oxide-semiconductor MN7, p-type MOS
The grid of pipe Mpass and the drain electrode of the 6th N-type metal-oxide-semiconductor MN6 connect；The drain electrode of p-type metal-oxide-semiconductor Mpass, one end of electric capacity CL, electricity
Hold one end of Cc, the other end of R2 is connected with LDO output end vo ut；The other end of electric capacity Cc connects with the drain electrode of p-type metal-oxide-semiconductor Mc
Connect；
The grid of the first p-type metal-oxide-semiconductor MP1, the grid of the 8th p-type metal-oxide-semiconductor MP8 are connected with bias voltage Vpb1；6th p-type
The grid of metal-oxide-semiconductor MP6, the grid of the 7th p-type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2；The grid of the first N-type metal-oxide-semiconductor MN1,
The grid of the 6th N-type metal-oxide-semiconductor MN6, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1；3rd N-type metal-oxide-semiconductor MN3
Grid, the grid of the 4th N-type metal-oxide-semiconductor MN4 is connected with bias voltage Vnb2；The grid of p-type metal-oxide-semiconductor Mc is with bias voltage VB even
Connect；
The source electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5,
The source electrode of eight p-type metal-oxide-semiconductor MP8, the drain electrode of the 7th N-type metal-oxide-semiconductor MN7 are connected with power supply Vsys；The source electrode of p-type metal-oxide-semiconductor Mpass with
Power supply Vin connects；
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the source electrode of the 6th N-type metal-oxide-semiconductor MN6,
The drain electrode of nine p-type metal-oxide-semiconductor MP9, the other end of resistance R1, the other end of electric capacity CL are connected with ground GND.
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance that the present invention provides, it is mended by dynamic ESR
Repay resistance compensation technology and achieve LDO system at loading range inner ring road quickly stably, and substantially increase system bandwidth, increase
Fast loop response speed.
Accompanying drawing explanation
Fig. 1 is band-gap reference section circuit structure diagram of the present invention.
Fig. 2 is LDO loop segments circuit structure diagram of the present invention.
Fig. 3 is that the dynamic ESR of the present invention compensates circuit structure diagram.
Detailed description of the invention
Below in conjunction with the drawings and specific embodiments, the present invention will be further described.
The present embodiment is for electricity field of power supplies, a kind of wide load linearity using dynamic ESR to compensate resistance
Adjustor, is provided with band-gap reference section and LDO loop segments, wherein band-gap reference section include bipolar transistor Q1, Q2,
Q3, p-type metal-oxide-semiconductor MP0, MP1, MP2, MP3, MP4, MP5, MP6, an amplifier, an electric current leakage and resistance R1, R2, such as Fig. 1 institute
Showing, it is specifically connected as: the grid of the 0th p-type metal-oxide-semiconductor MP0, the drain electrode of the 0th p-type metal-oxide-semiconductor MP0 connect with the input of electric current leakage
Connect；First operational amplifier A 1 outfan, the grid of the first p-type metal-oxide-semiconductor MP1, the grid of the second p-type metal-oxide-semiconductor MP2 and the 3rd P
The grid of type metal-oxide-semiconductor MP3 connects；The drain electrode of the first p-type metal-oxide-semiconductor MP1 is connected with the source electrode of the 4th p-type metal-oxide-semiconductor MP4；Second p-type
The drain electrode of metal-oxide-semiconductor MP2 is connected with the source electrode of the 5th p-type metal-oxide-semiconductor MP5；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3 and the 6th p-type metal-oxide-semiconductor
The source electrode of MP6 connects；The in-phase input end of the first operational amplifier A 1, the drain electrode of the 5th p-type metal-oxide-semiconductor MP5, one end of resistance R1
Connect；The inverting input of the first operational amplifier A 1, drain electrode and the first p-type bipolar transistor of the 4th p-type metal-oxide-semiconductor MP4
The colelctor electrode of Q1 connects；The other end of resistance R1 and the colelctor electrode of the second p-type bipolar transistor Q2 connect；6th p-type metal-oxide-semiconductor
The drain electrode of MP6, one end of resistance R2 are connected with bandgap voltage reference outfan Vref；The other end of resistance R2 and the 3rd p-type are double
The colelctor electrode of bipolar transistor Q3 connects；The source electrode of the 0th p-type metal-oxide-semiconductor MP0, the source electrode of the first p-type metal-oxide-semiconductor MP1, the second p-type
The source electrode of metal-oxide-semiconductor MP2, the source electrode of the 3rd p-type metal-oxide-semiconductor MP3 are connected with power vd D；The outfan of electric current leakage, the first p-type are bipolar
The base stage of transistor npn npn Q1, the emitter stage of the first p-type bipolar transistor Q1, the base stage of the second p-type bipolar transistor Q2,
The emitter stage of two p-type bipolar transistor Q2, the base stage of the 3rd p-type bipolar transistor Q3, the 3rd p-type bipolar transistor Q3
Emitter stage with ground GND be connected.
LDO loop segments includes electric capacity CL, Cc, resistance R1, R2, p-type metal-oxide-semiconductor MP1, MP2, MP3, MP4, MP5, MP6,
MP7, MP8, MP9, MPass, Mc and N-type metal-oxide-semiconductor MN1, MN2, MN3, MN4, MN5, MN6, as in figure 2 it is shown, it is specifically connected as:
The source electrode of the first p-type metal-oxide-semiconductor P1, the source electrode of the 4th p-type metal-oxide-semiconductor P4, the grid of the 6th p-type metal-oxide-semiconductor P6, the 7th p-type metal-oxide-semiconductor P7
Grid, the source electrode of the 5th p-type metal-oxide-semiconductor P5, one end of electric capacity C, the source electrode of the 8th p-type metal-oxide-semiconductor P8 and resistance R1 one end even
Connect；The source electrode of the drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3 connects；The
The grid of two p-type metal-oxide-semiconductor MP2, one end of R2 are connected with one end of R3；The grid of the 3rd p-type metal-oxide-semiconductor MP3 and reference voltage
Vref connects；The drain electrode of the drain electrode of the second p-type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 and the first N-type metal-oxide-semiconductor MN1 is even
Connect；The drain electrode of the drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 and the second N-type metal-oxide-semiconductor MN2 connects；The
The grid of four p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5, drain electrode and the 3rd N-type metal-oxide-semiconductor of the 6th p-type metal-oxide-semiconductor MP6
The drain electrode of MN3 connects；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th p-type metal-oxide-semiconductor MP6；5th p-type metal-oxide-semiconductor
The drain electrode of MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；The drain electrode of the 7th p-type metal-oxide-semiconductor MP7, the 4th N-type metal-oxide-semiconductor MN4
Drain electrode, the grid of the 9th p-type metal-oxide-semiconductor MP9 are connected with the source electrode of p-type metal-oxide-semiconductor Mc；The drain electrode of the 8th p-type metal-oxide-semiconductor MP8, the 9th P
The source electrode of type metal-oxide-semiconductor MP9 and the grid of the 7th N-type metal-oxide-semiconductor MN7 connect；The source electrode of the 7th N-type metal-oxide-semiconductor MN7, p-type metal-oxide-semiconductor
The grid of Mpass and the drain electrode of the 6th N-type metal-oxide-semiconductor MN6 connect；The drain electrode of p-type metal-oxide-semiconductor Mpass, one end of electric capacity CL, electric capacity
One end of Cc, the other end of R2 are connected with LDO output end vo ut；The other end of electric capacity Cc is connected with the drain electrode of p-type metal-oxide-semiconductor Mc；
The grid of the first p-type metal-oxide-semiconductor MP1, the grid of the 8th p-type metal-oxide-semiconductor MP8 are connected with bias voltage Vpb1；6th p-type metal-oxide-semiconductor MP6
Grid, the grid of the 7th p-type metal-oxide-semiconductor MP7 is connected with bias voltage Vpb2；The grid of the first N-type metal-oxide-semiconductor MN1, the 6th N-type
The grid of metal-oxide-semiconductor MN6, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1；The grid of the 3rd N-type metal-oxide-semiconductor MN3,
The grid of the 4th N-type metal-oxide-semiconductor MN4 is connected with bias voltage Vnb2；The grid of p-type metal-oxide-semiconductor Mc is connected with bias voltage VB；First
The source electrode of p-type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5, the 8th p-type metal-oxide-semiconductor MP8
Source electrode, the drain electrode of the 7th N-type metal-oxide-semiconductor MN7 is connected with power supply Vsys；The source electrode of p-type metal-oxide-semiconductor Mpass is connected with power supply Vin；
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the source electrode of the 6th N-type metal-oxide-semiconductor MN6, the 9th p-type MOS
The drain electrode of pipe MP9, the other end of resistance R1, the other end of electric capacity CL are connected with ground GND.
Such as Fig. 3, the LDO described by this programme uses dynamic ESR to compensate resistance compensation technology, dynamic by Mc equivalence
ESR compensation resistance, as dynamic adjustable resistance, is followed the change of load due to the input stage level of Buffer and is changed, ESR etc.
Effect resistance also can be according to the position of the change dynamic adjusting system zero point of loadWith compensate by
In the phase shift that system dominant pole produces, thus ensure stablizing of system.
Being above illustrating the present invention, this programme is not solely restricted in above example, at this programme
Any change made under inventive concept falls within scope.
Claims (4)
1. one kind use dynamic ESR compensate resistance wide load linearity adjustor, it is characterised in that include band-gap reference section and
LDO loop segments, described LDO loop compensates resistance as dynamic adjustable resistance, foundation Buffer by the dynamic ESR of Mc equivalence
Input stage level follow the change of load, the position of ESR equivalent resistance regulation system zero point；Wherein band-gap reference section includes
Three bipolar transistors, seven p-type metal-oxide-semiconductors, an amplifier, an electric current leakage and two resistance；And band-gap reference section tool
Volume elements device connects as follows:
The input that the grid of the 0th p-type metal-oxide-semiconductor MP0, the drain electrode of the 0th p-type metal-oxide-semiconductor MP0 are leaked with electric current is connected；First computing
Amplifier A1 outfan, the grid of the first p-type metal-oxide-semiconductor MP1, the grid of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3's
Grid connects；The drain electrode of the first p-type metal-oxide-semiconductor MP1 is connected with the source electrode of the 4th p-type metal-oxide-semiconductor MP4；The leakage of the second p-type metal-oxide-semiconductor MP2
Pole is connected with the source electrode of the 5th p-type metal-oxide-semiconductor MP5；The drain electrode of the 3rd p-type metal-oxide-semiconductor MP3 is with the source electrode of the 6th p-type metal-oxide-semiconductor MP6 even
Connect；The in-phase input end of the first operational amplifier A 1, the drain electrode of the 5th p-type metal-oxide-semiconductor MP5, one end of resistance R1 connect；First fortune
Calculate the inverting input of amplifier A1, the drain electrode of the 4th p-type metal-oxide-semiconductor MP4 connects with the colelctor electrode of the first p-type bipolar transistor Q1
Connect；The other end of resistance R1 and the colelctor electrode of the second p-type bipolar transistor Q2 connect；The drain electrode of the 6th p-type metal-oxide-semiconductor MP6, electricity
One end of resistance R2 is connected with bandgap voltage reference outfan Vref；The other end of resistance R2 and the 3rd p-type bipolar transistor Q3
Colelctor electrode connect；
The source electrode of the 0th p-type metal-oxide-semiconductor MP0, the source electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2, the 3rd p-type
The source electrode of metal-oxide-semiconductor MP3 is connected with power vd D；
Electric current leakage outfan, the base stage of the first p-type bipolar transistor Q1, the emitter stage of the first p-type bipolar transistor Q1,
The base stage of the second p-type bipolar transistor Q2, the emitter stage of the second p-type bipolar transistor Q2, the 3rd p-type bipolar transistor
The base stage of Q3, the emitter stage of the 3rd p-type bipolar transistor Q3 are connected with ground GND.
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance the most as claimed in claim 1, it is characterised in that
The formula of described ESR equivalent resistance regulation system dead-center position is as follows:
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance the most as claimed in claim 1, it is characterised in that
Described LDO loop segments includes two electric capacity, two resistance, 11 p-type metal-oxide-semiconductors and six N-type metal-oxide-semiconductors.
A kind of wide load linearity adjustor using dynamic ESR to compensate resistance the most as claimed in claim 3, it is characterised in that
The described concrete components and parts of LDO loop segments connect as follows:
The source electrode of the first p-type metal-oxide-semiconductor P1, the source electrode of the 4th p-type metal-oxide-semiconductor P4, the grid of the 6th p-type metal-oxide-semiconductor P6, the 7th p-type MOS
The grid of pipe P7, the source electrode of the 5th p-type metal-oxide-semiconductor P5, one end of electric capacity C, the source electrode and the one of resistance R1 of the 8th p-type metal-oxide-semiconductor P8
End connects；The source electrode of the drain electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the second p-type metal-oxide-semiconductor MP2 and the 3rd p-type metal-oxide-semiconductor MP3 is even
Connect；The grid of the second p-type metal-oxide-semiconductor MP2, one end of R2 are connected with one end of R3；The grid of the 3rd p-type metal-oxide-semiconductor MP3 and benchmark electricity
Pressure Vref connects；The drain electrode of the second p-type metal-oxide-semiconductor MP2, the source electrode of the 3rd N-type metal-oxide-semiconductor MN3 and the drain electrode of the first N-type metal-oxide-semiconductor MN1
Connect；The drain electrode of the drain electrode of the 3rd p-type metal-oxide-semiconductor MP3, the source electrode of the 4th N-type metal-oxide-semiconductor MN4 and the second N-type metal-oxide-semiconductor MN2 connects；
The grid of the 4th p-type metal-oxide-semiconductor MP4, the grid of the 5th p-type metal-oxide-semiconductor MP5, drain electrode and the 3rd N-type MOS of the 6th p-type metal-oxide-semiconductor MP6
The drain electrode of pipe MN3 connects；The drain electrode of the 4th p-type metal-oxide-semiconductor MP4 is connected with the source electrode of the 6th p-type metal-oxide-semiconductor MP6；5th p-type metal-oxide-semiconductor
The drain electrode of MP5 is connected with the source electrode of the 7th p-type metal-oxide-semiconductor MP7；The drain electrode of the 7th p-type metal-oxide-semiconductor MP7, the 4th N-type metal-oxide-semiconductor MN4
Drain electrode, the grid of the 9th p-type metal-oxide-semiconductor MP9 are connected with the source electrode of p-type metal-oxide-semiconductor Mc；The drain electrode of the 8th p-type metal-oxide-semiconductor MP8, the 9th P
The source electrode of type metal-oxide-semiconductor MP9 and the grid of the 7th N-type metal-oxide-semiconductor MN7 connect；The source electrode of the 7th N-type metal-oxide-semiconductor MN7, p-type metal-oxide-semiconductor
The grid of Mpass and the drain electrode of the 6th N-type metal-oxide-semiconductor MN6 connect；The drain electrode of p-type metal-oxide-semiconductor Mpass, one end of electric capacity CL, electric capacity
One end of Cc, the other end of R2 are connected with LDO output end vo ut；The other end of electric capacity Cc is connected with the drain electrode of p-type metal-oxide-semiconductor Mc；
The grid of the first p-type metal-oxide-semiconductor MP1, the grid of the 8th p-type metal-oxide-semiconductor MP8 are connected with bias voltage Vpb1；6th p-type MOS
The grid of pipe MP6, the grid of the 7th p-type metal-oxide-semiconductor MP7 are connected with bias voltage Vpb2；The grid of the first N-type metal-oxide-semiconductor MN1,
The grid of six N-type metal-oxide-semiconductor MN6, the grid of the second N-type metal-oxide-semiconductor MN2 are connected with bias voltage Vnb1；3rd N-type metal-oxide-semiconductor MN3's
Grid, the grid of the 4th N-type metal-oxide-semiconductor MN4 are connected with bias voltage Vnb2；The grid of p-type metal-oxide-semiconductor Mc is with bias voltage VB even
Connect；
The source electrode of the first p-type metal-oxide-semiconductor MP1, the source electrode of the 4th p-type metal-oxide-semiconductor MP4, the source electrode of the 5th p-type metal-oxide-semiconductor MP5, the 8th p-type
The source electrode of metal-oxide-semiconductor MP8, the drain electrode of the 7th N-type metal-oxide-semiconductor MN7 are connected with power supply Vsys；The source electrode of p-type metal-oxide-semiconductor Mpass and power supply
Vin connects；
The source electrode of the first N-type metal-oxide-semiconductor MN1, the source electrode of the second N-type metal-oxide-semiconductor MN2, the source electrode of the 6th N-type metal-oxide-semiconductor MN6, the 9th p-type
The drain electrode of metal-oxide-semiconductor MP9, the other end of resistance R1, the other end of electric capacity CL are connected with ground GND.
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| CN104049660A (en) * | 2013-03-15 | 2014-09-17 | 深圳市海洋王照明工程有限公司 | Low drop-out voltage stabilizing circuit and electronic equipment |
| CN105786071B (en) * | 2014-12-24 | 2018-06-22 | 联芯科技有限公司 | A kind of low-dropout linear voltage-regulating circuit and low pressure difference linearity stable-pressure device |
| CN106292816B (en) * | 2015-06-11 | 2018-01-09 | 京微雅格（北京）科技有限公司 | A kind of LDO circuit and its method of supplying power to, fpga chip |
| US10133287B2 (en) * | 2015-12-07 | 2018-11-20 | Macronix International Co., Ltd. | Semiconductor device having output compensation |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN1662862A (en) * | 2002-06-28 | 2005-08-31 | 飞思卡尔半导体公司 | Low drop-out voltage regulator and method |
| CN101038497A (en) * | 2006-03-17 | 2007-09-19 | 深圳赛意法微电子有限公司 | Compensation method, compensated regulator and electronic circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7719241B2 (en) * | 2006-03-06 | 2010-05-18 | Analog Devices, Inc. | AC-coupled equivalent series resistance |
| US7679437B2 (en) * | 2008-03-06 | 2010-03-16 | Texas Instruments Incorporated | Split-feedback technique for improving load regulation in amplifiers |
-
2012
- 2012-05-30 CN CN201210179271.9A patent/CN102707756B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1662862A (en) * | 2002-06-28 | 2005-08-31 | 飞思卡尔半导体公司 | Low drop-out voltage regulator and method |
| US6765374B1 (en) * | 2003-07-10 | 2004-07-20 | System General Corp. | Low drop-out regulator and an pole-zero cancellation method for the same |
| CN101038497A (en) * | 2006-03-17 | 2007-09-19 | 深圳赛意法微电子有限公司 | Compensation method, compensated regulator and electronic circuit |
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