CN102693944A - Method for improving read redundancy of static random access memory - Google Patents
Method for improving read redundancy of static random access memory Download PDFInfo
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- CN102693944A CN102693944A CN2012101433843A CN201210143384A CN102693944A CN 102693944 A CN102693944 A CN 102693944A CN 2012101433843 A CN2012101433843 A CN 2012101433843A CN 201210143384 A CN201210143384 A CN 201210143384A CN 102693944 A CN102693944 A CN 102693944A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000003068 static effect Effects 0.000 title claims abstract description 19
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 20
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims abstract description 20
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 4
- 238000005516 engineering process Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000010409 thin film Substances 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 3
- 238000005137 deposition process Methods 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000137 annealing Methods 0.000 abstract description 5
- 230000006835 compression Effects 0.000 description 8
- 238000007906 compression Methods 0.000 description 8
- 238000003860 storage Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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- Static Random-Access Memory (AREA)
Abstract
The invention discloses a method for improving the read redundancy of a static random access memory, comprising the following steps of: providing a static random access memory substrate including a first NMOS area, a PMOS area, and a second NMOS area which are adjacent to each other, wherein the first NMOS area is used for preparing a pull down MOS, the PMOS area is used for preparing a pull up MOS, and the second NMOS area is used for preparing a pass gate; forming shallow slot isolation areas among the first NMOS area, the PMOS area, and the second NMOS area; opening the second NMOS area by a photomask and simultaneously carrying out a source-drain germanium injection process on the PMOS area, and carrying out a germanium injection for the second NMOS area; and carrying out a rapid annealing process to form a germanium-silicon lattice structure on both ends of the NMOS area. The method of the invention reduces the carrier mobility of pass gate components and increases the equivalent resistance of the pass gate.
Description
Technical field
The present invention relates to the semiconductor fabrication technical field, relate in particular to a kind of method that static random access memory is read redundancy that improves.
Background technology
Static random access memory (SRAM) has obtained using widely in high-speed data exchange systems such as computer, communication, multimedia as one type of staple product in the semiconductor memory.Shown in Figure 1 is the domain structure of one the 90 common sram cell below the nanometer; Include these three levels of source region, polysilicon gate and contact hole, what zone 1 was marked among the figure is control valve (Pass Gate), and this device is a nmos device; What zone 2 was marked is following trombone slide (Pull Down MOS); This device is similarly a nmos device, and what zone 3 was marked is last trombone slide (Pull Up MOS), and this device is a PMOS device.
Reading redundancy is to weigh sram cell to read an important parameter of performance, and Fig. 2 is the work sketch map of a SRAM device when reading, and 4 is control valve among the figure; 5 are following trombone slide, and 6 is last trombone slide, suppose that node 7 storage data are high potential (promptly store data and be " 1 "); And corresponding, node 8 storage data are electronegative potential (promptly store data and be " 0 "), before reading action; Bit line 9 can be precharged to high potential with bit line 10, and when reading the action beginning, word line 11 is opened; Because the data of node 7 storage are high potential, thus the voltage on the bit line 9 remain unchanged, and because the data of node 8 storages are electronegative potential; Voltage meeting quilt on the bit line 10 is accomplished the action of reading of sram cell to drop-down through perception bit line 9 and the voltage difference on the bit line 10.A condition that must guarantee is arranged in readout, can not change the data of original storage in the sram cell exactly.After word line 11 is opened; Voltage on the bit line 10 is by drop-down the time; The current potential of node 8 also can be pulled up to an intermediate potential simultaneously; Promptly no longer keep " 0 ", the size of intermediate potential is to be determined by the ratio of trombone slide and control valve down, promptly can be regarded as drop-down pipe and control valve equivalent resistance ratio determined.In order not change in the sram cell data of original storage, the intermediate potential of node 8 is asked to must be less than certain numerical value, promptly descends the ratio of the equivalent resistance of trombone slide and control valve must be less than certain value.Here it is, and SRAM reads the requirement of reading redundancy when moving, and increases the equivalent resistance of control valve, can reduce the intermediate potential of node 8, thereby increases the redundancy of reading of sram cell.
Along with the progress of technology generations, particularly in the following technology generations of 65 nanometers, in PMOS device preparation technology process; Before injection technology is leaked in the source, can carry out germanium to the PMOS device and inject, it is decrystallized that this on the one hand can the realization source leaks; To form ultra shallow junction, in subsequent annealing technology, can leak formation germanium silicon lattice structure on the other hand in the source; Finally in the PMOS device channel, produce compression, with the hole carrier mobility of raising PMOS device, thus the performance of raising PMOS device.But the compression in the raceway groove can reduce the mobility of electronics, so for nmos device, generally do not adopt this method.Fig. 3 is the sketch map when carrying out source leakage germanium injection technology of nmos device, PMOS device and control valve in the common technology; Wherein common nmos device 5 is covered by photoresist 0 with control valve 4; Only can carry out the source to PMOS device 6 and leak the germanium injection, through subsequent annealing technology, two ends are leaked in PMOS device 6 sources can form the germanium silicon lattice structure; Thereby form the compression in PMOS device 6 raceway grooves, this compression helps to improve the hole mobility of PMOS device.Do not leak the germanium injection because nmos device 5 all carries out the source with control valve 4, so can not be created in the compression in the raceway groove thus, therefore electron mobility can not reduce.
Summary of the invention
Problem to above-mentioned existence; The purpose of this invention is to provide a kind of method that static random access memory is read redundancy that improves; Make control valve on channel direction, produce compression; Reduced the carrier mobility of control valve device, increased the equivalent resistance of control valve, improved random asccess memory and read redundancy.
The objective of the invention is to realize through following technical proposals:
A kind ofly improve the method that static random access memory is read redundancy, wherein, comprise the following steps:
The static random access memory substrate is provided; Comprise the first adjacent successively nmos area territory, PMOS zone and the second nmos area territory on the said substrate; The said first nmos area territory is used to prepare trombone slide down, and said PMOS zone is used to prepare trombone slide, and the said second nmos area territory is used to prepare control valve;
Between the said first nmos area territory, said PMOS zone and the said second nmos area territory, form shallow trench isolation region;
In said PMOS zone being carried out source leakage germanium injection technology process, make reticle open the said second nmos area territory simultaneously, simultaneously germanium is implemented in the said second nmos area territory and injected;
Carry out rta technique, two ends, the said second nmos area territory form the germanium silicon lattice structure.
In a preferred embodiment of the invention, in the manufacturing process of accomplishing said PMOS zone or said first nmos area territory or the said second nmos area territory, be included in deposition of gate material on the silicon thin film, etching forms grid and makes side wall.
In a preferred embodiment of the invention, said deposition process adopts chemical gas-phase method.
In a preferred embodiment of the invention, said etching adopts dry etching.
In a preferred embodiment of the invention, said silicon thin film is silicon nitride or silica.
In a preferred embodiment of the invention, said substrate is a silicon substrate.
Compared with present technology, beneficial effect of the present invention is:
1, do not increase existing processing step;
2, through logical operation (Logic Operation), leak in the germanium injection technology process in the PMOS source, make reticle open control valve simultaneously, when the PMOS device being carried out the injection of source leakage germanium, simultaneously control valve is implemented germanium and inject.Through annealing process afterwards, the control valve two ends also can form the germanium silicon lattice structure, thereby in the control valve raceway groove, form compression, have reduced the carrier mobility of control valve device, have increased the equivalent resistance of control valve;
3, in reading process, reduced the current potential of node 8, thereby improved the redundancy of reading of random asccess memory.
Description of drawings
Fig. 1 is a SRAM domain sketch map in the prior art;
Fig. 2 is a SRAM electrical block diagram in the prior art.
Fig. 3 is that germanium injection sketch map is leaked in the source in the prior art;
A kind of static random access memory that improves of Fig. 4 the present invention is read source leakage germanium injection sketch map in the method for redundancy.
Embodiment
Below in conjunction with schematic diagram and concrete operations embodiment the present invention is described further.
As shown in Figure 4, the present invention improves the method that static random access memory is read redundancy, it is characterized in that, comprises the following steps:
The static random access memory substrate is provided; Comprise the adjacent successively first nmos area territory 5, the 6 and second nmos area territory 4, PMOS zone on the substrate; The first nmos area territory 5 is used to prepare trombone slide down, and PMOS zone 6 is used to prepare trombone slide, and the second nmos area territory 4 is used to prepare control valve;
In the first nmos area territory 5, the PMOS zone forms shallow trench isolation region between the 6 and second nmos area territory 4;
In PMOS zone 6 being carried out source leakage germanium injection technology process, make reticle 0 open the second nmos area territory 4 simultaneously, simultaneously germanium are implemented in the second nmos area territory 4 and injected;
Carry out rta technique, 4 two ends, the second nmos area territory form the germanium silicon lattice structure.
Preferably, in the manufacturing process of accomplishing the PMOS 6 or first nmos area territory 5, zone or the second nmos area territory 4, be included in deposition of gate material on the silicon thin film, etching forms grid and makes side wall.
Preferably, deposition process adopts chemical gas-phase method, and etching adopts dry etching.
Further, silicon thin film is silicon nitride or silica, and substrate is a silicon substrate.
To sum up, the present invention is leaked in the germanium injection technology process in the PMOS source through logical operation (Logic Operation), makes reticle open control valve simultaneously, when the PMOS device being carried out the injection of source leakage germanium, simultaneously control valve is implemented germanium and injects.Through annealing process afterwards, the control valve two ends also can form the germanium silicon lattice structure, thereby in the control valve raceway groove, form compression, have reduced the carrier mobility of control valve device, have increased the equivalent resistance of control valve.
More than specific embodiment of the present invention is described in detail, but the present invention is not restricted to the specific embodiment of above description, it is just as example.To those skilled in the art, any equivalent modifications and alternative also all among category of the present invention.Therefore, not breaking away from impartial conversion and the modification of having done under the spirit and scope of the present invention, all should contain within the scope of the invention.
Claims (6)
1. one kind is improved the method that static random access memory is read redundancy, it is characterized in that, comprises the following steps:
The static random access memory substrate is provided; Comprise the first adjacent successively nmos area territory, PMOS zone and the second nmos area territory on the said substrate; The said first nmos area territory is used to prepare trombone slide down, and said PMOS zone is used to prepare trombone slide, and the said second nmos area territory is used to prepare control valve;
Between the said first nmos area territory, said PMOS zone and the said second nmos area territory, form shallow trench isolation region;
In said PMOS zone being carried out source leakage germanium injection technology process, make reticle open the said second nmos area territory simultaneously, simultaneously germanium is implemented in the said second nmos area territory and injected;
Carry out rta technique, two ends, the said second nmos area territory form the germanium silicon lattice structure.
2. raising static random access memory as claimed in claim 1 is read the method for redundancy; It is characterized in that; In the manufacturing process of accomplishing said PMOS zone or said first nmos area territory or the said second nmos area territory, be included in deposition of gate material on the silicon thin film, etching forms grid and makes side wall.
3. raising static random access memory as claimed in claim 2 is read the method for redundancy, it is characterized in that, said deposition process adopts chemical gas-phase method.
4. raising static random access memory as claimed in claim 2 is read the method for redundancy, it is characterized in that, said etching adopts dry etching.
5. raising static random access memory as claimed in claim 2 is read the method for redundancy, it is characterized in that, said silicon thin film is silicon nitride or silica.
6. raising static random access memory as claimed in claim 1 is read the method for redundancy, it is characterized in that, said substrate is a silicon substrate.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579244A (en) * | 2013-10-18 | 2014-02-12 | 上海华力微电子有限公司 | Static random access memory and method for improving writing-in redundancy rate of static random access memory |
| CN103579243A (en) * | 2013-10-18 | 2014-02-12 | 上海华力微电子有限公司 | Static random access memory in embedded germanium silicon process and write-in redundancy improving method |
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| CN1581508A (en) * | 2003-08-12 | 2005-02-16 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacturing method |
| US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
| CN101055872A (en) * | 2006-04-10 | 2007-10-17 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN101207130A (en) * | 2006-12-19 | 2008-06-25 | 国际商业机器公司 | integrated circuit |
| CN102341897A (en) * | 2008-12-31 | 2012-02-01 | 英特尔公司 | Quantum well MOSFET channel with uniaxial strain induced by metal source/drain and conformally regrown source/drain |
| CN102420231A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | SRAM unit structure based on pseudo through hole etching stop layer technology and preparation method thereof |
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- 2012-05-10 CN CN2012101433843A patent/CN102693944A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1581508A (en) * | 2003-08-12 | 2005-02-16 | 台湾积体电路制造股份有限公司 | Semiconductor element and its manufacturing method |
| US20070173022A1 (en) * | 2006-01-20 | 2007-07-26 | Chih-Hao Wang | Defect-free SiGe source/drain formation by epitaxy-free process |
| CN101055872A (en) * | 2006-04-10 | 2007-10-17 | 台湾积体电路制造股份有限公司 | Semiconductor structure and manufacturing method thereof |
| CN101207130A (en) * | 2006-12-19 | 2008-06-25 | 国际商业机器公司 | integrated circuit |
| CN102341897A (en) * | 2008-12-31 | 2012-02-01 | 英特尔公司 | Quantum well MOSFET channel with uniaxial strain induced by metal source/drain and conformally regrown source/drain |
| CN102420231A (en) * | 2011-04-29 | 2012-04-18 | 上海华力微电子有限公司 | SRAM unit structure based on pseudo through hole etching stop layer technology and preparation method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103579244A (en) * | 2013-10-18 | 2014-02-12 | 上海华力微电子有限公司 | Static random access memory and method for improving writing-in redundancy rate of static random access memory |
| CN103579243A (en) * | 2013-10-18 | 2014-02-12 | 上海华力微电子有限公司 | Static random access memory in embedded germanium silicon process and write-in redundancy improving method |
| CN103579243B (en) * | 2013-10-18 | 2016-08-17 | 上海华力微电子有限公司 | SRAM and write redundancy ameliorative way in embedded germanium silicon technology |
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Application publication date: 20120926 |