CN102683173B - Reduce method and the method for manufacturing integrated circuit of wafer arc discharge - Google Patents
Reduce method and the method for manufacturing integrated circuit of wafer arc discharge Download PDFInfo
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- CN102683173B CN102683173B CN201210093549.0A CN201210093549A CN102683173B CN 102683173 B CN102683173 B CN 102683173B CN 201210093549 A CN201210093549 A CN 201210093549A CN 102683173 B CN102683173 B CN 102683173B
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- 238000010891 electric arc Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title abstract description 9
- 238000002161 passivation Methods 0.000 claims abstract description 44
- 238000005530 etching Methods 0.000 claims description 30
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000002184 metal Substances 0.000 description 9
- 238000001241 arc-discharge method Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- Drying Of Semiconductors (AREA)
Abstract
The invention provides a kind of method reducing wafer arc discharge and method for manufacturing integrated circuit.Described wafer includes laser mark area, the top layer metallic layer of described wafer being disposed with passivation layer；The method of the minimizing wafer arc discharge according to the present invention includes：Making the size of opening of the described passivation layer in the region in described laser mark area, to open size than all other floor on the wafer in the region in described laser mark area little.According to the present invention so that passivation layer open size than other layers or top layer metallic layer to open size little, such that it is able to avoid exposing other layers or top layer metallic layer to collect electric charge, thus reducing the probability of wafer arc discharge.
Description
Technical field
The present invention relates to field of semiconductor manufacture, it is more particularly related to a kind of minimizing wafer arc discharge
Method and employ this minimizing wafer arc discharge method method for manufacturing integrated circuit.
Background technology
Wafer arc discharge (Wafer Arcing) electric discharge is that the one kind occurring in ic manufacturing process does not expect
The phenomenon occurring.The basic reason of the wafer arc discharge that dielectric etch causes is the wafer caused by plasma unstable
On horizontal DC voltage drop.
Wafer arc discharge can cause a lot of defects to wafer.For example, Fig. 1 schematically shows wafer arc discharge,
Wherein label 1 denotes the region of wafer arc discharge.
Because a kind of defect that wafer arc discharge is led to includes the survey of isolation that damages due to wafer arc discharge
Examination bond structure.
Details with regard to wafer arc discharge can be with further reference to Shawming Ma, Neil Hanabusa, Brad Mays
Et al. paper " the Backend Dielectric Etch Induced Wafer Arcing Mechanism that delivers on IEEE
And Solution " (0-7803-7747-8/03 2003, IEEE, 178-181 page).
Although prior art has employed some measures to prevent the generation of wafer arc discharge, the one of wafer
Still wafer arc discharge occurs in a little regions.
Due to the side effect of wafer arc discharge, it is therefore desirable to provide a kind of method that can reduce wafer arc discharge.
Content of the invention
The technical problem to be solved is that there is drawbacks described above in prior art, provides one kind can reduce
The method of wafer arc discharge and employ this minimizing wafer arc discharge method method for manufacturing integrated circuit.
According to the first aspect of the invention, there is provided a kind of method reducing wafer arc discharge, described wafer includes swashing
Light logo area, the top layer metallic layer of described wafer is disposed with passivation layer；Wherein said method includes so that described laser mark
Described passivation layer in the region in area open size than all other floor on the wafer in the region in described laser mark area
To open size little.
Preferably so that described passivation layer in the region in described laser mark area open size than described laser mark
All other floor on wafer in the region in area to open size little 0.1 micron.
Preferably so that described passivation layer in the region in described laser mark area open size than described laser mark
All other floor on wafer in the region in area to open size little 0.05 micron to 5 microns.
According to the second aspect of the invention, there is provided a kind of method reducing wafer arc discharge, described wafer includes swashing
Light logo area, the top layer metallic layer of described wafer is disposed with passivation layer；Wherein said method includes so that described laser mark
Described passivation layer in the region in area open size than the top layer metallic layer on the wafer in the region in described laser mark area
To open size little.
Preferably, methods described includes：Form the pattern of described top layer metallic layer, wherein make described laser mark area
The size of etching window is first size；Hereafter, form the pattern of passivation layer, wherein make the etching window in described laser mark area
The size of mouth is the second size；Wherein, described second it is smaller in size than described first size.
Preferably so that described passivation layer in the region in described laser mark area open size than described laser mark
The top layer metallic layer on wafer in the region in area to open size little 0.1 micron.
Preferably so that described passivation layer in the region in described laser mark area open size than described laser mark
The top layer metallic layer on wafer in the region in area to open size little 0.05 micron to 5 microns.
According to the third aspect of the invention we, there is provided a kind of employ minimizing wafer described according to a first aspect of the present invention
The method for manufacturing integrated circuit of the method for arc discharge.
According to the present invention so that passivation layer open size than other layers or top layer metallic layer to open size little, from
And can avoid exposing other layers or top layer metallic layer to collect electric charge, thus reduce the probability of wafer arc discharge.
Brief description
In conjunction with accompanying drawing, and by reference to detailed description below, it will more easily have more complete understanding to the present invention
And its adjoint advantages and features are more easily understood, wherein：
Fig. 1 schematically shows wafer arc discharge.
The method that Fig. 2 schematically shows minimizing wafer arc discharge according to embodiments of the present invention.
Fig. 3 shows the diagram in laser mark area.
Fig. 4 schematically shows the wafer arc discharge in laser mark area.
It should be noted that accompanying drawing is used for the present invention is described, and the unrestricted present invention.Note, represent that the accompanying drawing of structure can
Can be not necessarily drawn to scale.And, in accompanying drawing, same or like element indicates same or like label.
Specific embodiment
In order that present disclosure is more clear and understandable, with reference to specific embodiments and the drawings in the present invention
Appearance is described in detail.
Shown in Fig. 3, typically, during wafer is processed to produce desired chip or integrated circuit, meeting exists
The such as outer region of wafer manufactures a laser mark area (laser maker) 3.
This laser mark area 3 is used for a code name of marking wafer, and this code name marked code or coding or serial number, should
Code name is typically made up of 8 to 9 bit digital or character；Just processed wafer can be identified by reading this code, for example, obtain
Know the information such as the batch lot number of processed wafer.
Fig. 3 shows the diagram in laser mark area.As shown in figure 3, illustrated therein is the laser mark area 3 on wafer.Example
As citing is got on very well, and in the example depicted in fig. 3, the information of laser mark area 3 record is " A616049.18 ".
The favourable discovery of the present inventor, although taking the measure that some prevent wafer arc discharge, swashs
Wafer arc discharge still easily occurs in light logo area 3.Fig. 4 schematically shows the wafer arc discharge in laser mark area.
As shown in the reference number 4 of Fig. 4, in laser mark area 3 or near it, wafer arc discharge 4 still occurs.
Thus, the method for minimizing wafer arc discharge according to embodiments of the present invention be by formed top layer metallic layer and
Formed in the technique of passivation layer, making the size of opening of the passivation layer in laser mark area 3, to open size than top layer metallic layer little
To prevent or to reduce the wafer arc discharge in laser mark area 3.It is described hereinafter according to a particular embodiment of the invention.
The method that Fig. 2 schematically shows minimizing wafer arc discharge according to embodiments of the present invention.
As shown in Fig. 2 in chip area A, the edge (in figure of the region B that laser mark area and top layer metallic layer are opened
Dotted line shown in) outside the region C that passivation layer is opened.In other words, the region C that passivation layer is opened is smaller in size than laser mark
The region B that area 3 and top layer metallic layer are opened.
Specifically, typically, conventionally, as laser mark area 3 is used for one code of record or code name, so
Formation to laser mark area 3, needs to make laser mark area 3 not form figure (in this laser mark area 3 in etch step
There is not photoresistance), and make code in laser mark area 3 or code name be formed at the bottom (such as substrate layer) of silicon chip, this
Coding or the lot number information of wafer can be found out using viewing tool by checking this code or code name afterwards.
And, general, opening or etching for laser mark area 3, to laser mark in the etching process of all levels
The etching size (opening size) in area 3 is unified, thus Ge Cengzhong laser mark area 3 to open window identical.Just because of such as
, if error in technique it is likely that causing the exposure of metal in metal level and so that the metal line of metal level is received in this
Collection electric charge is thus produce wafer arc discharge.
Therefore, the embodiment of the present invention by control laser mark area 3 etching reduce wafer arc discharge generation can
Can property.Specifically, so that (etching) size of opening of passivation layer open (etching) size than top layer metallic layer little, by
This can be avoided exposing top layer metallic layer, the top layer metallic layer thus not exposed collecting electric charge, thus reducing wafer electric arc
The probability of electric discharge.
It is further preferred that as shown in Fig. 2 in chip area A, region that the other layers outside passivation layer are opened is all etc.
It is same as the region B that the laser mark area shown in Fig. 2 and top layer metallic layer are opened, so, the edge of the other layers outside passivation layer
(shown in the dotted line of in figure) is outside the region C that passivation layer is opened.In other words, being smaller in size than of the region C that passivation layer is opened is blunt
The region B that other layers outside change layer are opened, other layers can be passivated the medium of layer during the plasma etching of passivation layer
Cover thus avoiding the arc discharge that charge-trapping is triggered.
Specifically, so that (etching) size of opening of passivation layer in laser mark area 3 region compares laser mark
The reason (etching) size is little to be just avoided that arc discharge of opening of all other floor on wafer in area 3 region is, can
To avoid the metal collection electric charge exposing the metal level comprising top layer metallic layer, thus not exposing, thus reducing wafer
The probability of arc discharge.
" opening size " refers specifically to for example expose size, the such as etching size of the pattern after etching.
Wherein, one of ordinary skill in the art will appreciate that in " top layer metallic layer " metal interconnection layer of referring to
Positioned at a top metal interconnection layer.
Further, for example in a specific embodiment, form the pattern of top layer metallic layer in the first step,
The size wherein making the etching window in laser mark area is first size.
Hereafter, the pattern forming passivation layer in the second step (forms passivation after forming the pattern of top layer metallic layer
The pattern of layer).The size wherein making the etching window in laser mark area is the second size.
Wherein so that second is smaller in size than first size, that is, passivation layer open size open than top layer metallic layer little,
So that the overlay area of passivation layer is completely covered the overlay area of top layer metallic layer, thus avoiding of top layer metallic layer
Divide in the etching being exposed to passivation layer.
More particularly, it is preferable that ground, the size of the passivation layer in the outer region of wafer is only made to compare top layer metallic layer
Size little, thus not exposing the top layer metallic layer of the perimeter region of wafer.I.e. so that passivation layer covers the perimeter region of wafer
Domain, thus do not expose the top layer metallic layer of the perimeter region of wafer.
In one particular embodiment of the present invention it is preferable that (etching) size of opening of passivation layer can be made to compare top layer
Metal level to open (etching) size little such as 0.1 micron.Certainly, in another specific embodiment of the present invention it is preferable that
Can make passivation layer open (etching) size open than top layer metallic layer (etching) size little such as 0.05 micron micro- to 5
Rice.It will be appreciated by persons skilled in the art that numerical value " 0.1 micron " and " 0.05 micron to 5 microns " are only preferably,
It is of course possible to using other suitable numerical value.
Similarly, so that passivation layer open (etching) size than all other layer to open (etching) size little,
So that except passivation layer open (etching) size in addition to all other layer open (etching) equivalently-sized, and be passivated
Layer to open (etching) size less than them.
In one particular embodiment of the present invention it is preferable that (etching) size of opening of passivation layer can be made to compare other
Layer to open (etching) size little such as 0.1 micron.Certainly, it is preferable that permissible in another specific embodiment of the present invention
Making (etching) size of opening of passivation layer, open (etching) size than other layers little such as 0.05 micron to 5 microns.This area
Technical staff it is understood that numerical value " 0.1 micron " and " 0.05 micron to 5 microns " be only preferably it is of course possible to
Using other suitable numerical value.
According to another embodiment of the present invention, also provide a kind of collection of the method employing above-mentioned minimizing wafer arc discharge
Become circuit fabrication method.
Although it is understood that the present invention is disclosed as above with preferred embodiment, but above-described embodiment being not used to
Limit the present invention.For any those of ordinary skill in the art, without departing under technical solution of the present invention ambit,
The technology contents that the disclosure above all can be utilized are made many possible variations and modification, or are revised as to technical solution of the present invention
Equivalent embodiments with change.Therefore, every content without departing from technical solution of the present invention, according to the technical spirit pair of the present invention
Any simple modification made for any of the above embodiments, equivalent variations and modification, all still fall within the scope of technical solution of the present invention protection
Interior.
Claims (4)
1. a kind of method reducing wafer arc discharge, described wafer includes laser mark area, the top layer metallic layer of described wafer
On be disposed with passivation layer；It is characterized in that methods described includes making the described passivation layer in the region in described laser mark area
Open size open than all other floor on the wafer in the region in described laser mark area size little so that described laser
Described passivation layer in the region of logo area open size than on the wafer in the region in described laser mark area all its
Its layer to open size little 0.1 micron.
2. a kind of method reducing wafer arc discharge, described wafer includes laser mark area, the top layer metallic layer of described wafer
On be disposed with passivation layer；It is characterized in that methods described includes making the described passivation layer in the region in described laser mark area
Opening size, to open size than the top layer metallic layer on the wafer in the region in described laser mark area little；Make described laser
Described passivation layer in the region of logo area open size than on the wafer in the region in described laser mark area top layer gold
Belong to layer to open size little 0.1 micron.
3. the method reducing wafer arc discharge according to claim 2 is it is characterised in that methods described includes：Form institute
State the pattern of top layer metallic layer, the size wherein making the etching window in described laser mark area is first size；
Hereafter, form the pattern of passivation layer, the size wherein making the etching window in described laser mark area is the second size；
Wherein, described second it is smaller in size than described first size.
4. a kind of integrated circuit system of the method for minimizing wafer arc discharge employing according to one of claims 1 to 3
Make method.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210093549.0A CN102683173B (en) | 2012-03-31 | 2012-03-31 | Reduce method and the method for manufacturing integrated circuit of wafer arc discharge |
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| CN201210093549.0A CN102683173B (en) | 2012-03-31 | 2012-03-31 | Reduce method and the method for manufacturing integrated circuit of wafer arc discharge |
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| CN102683173B true CN102683173B (en) | 2017-03-08 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105826240B (en) * | 2015-01-07 | 2019-05-31 | 中芯国际集成电路制造(上海)有限公司 | The method for avoiding wafer from generating point discharge defect |
| CN106405372B (en) * | 2016-08-22 | 2020-01-10 | 上海华力微电子有限公司 | Defect detection method for avoiding arc discharge generated in electron beam scanning process |
| CN110349846B (en) * | 2019-06-19 | 2020-10-02 | 长江存储科技有限责任公司 | Etching method of semiconductor device and three-dimensional memory |
| CN111257727A (en) * | 2020-01-17 | 2020-06-09 | 上海华力集成电路制造有限公司 | Device and method for detecting arc discharge in WAT test |
| CN115831865A (en) * | 2023-02-24 | 2023-03-21 | 广州粤芯半导体技术有限公司 | Structure and method for reducing arc discharge in wafer marking area |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5451801A (en) * | 1989-10-03 | 1995-09-19 | Trw Inc. | Adaptive configurable gate array |
| CN1614771A (en) * | 2003-11-04 | 2005-05-11 | 松下电器产业株式会社 | Semiconductor device and its manufacture |
| CN1649154A (en) * | 2004-01-26 | 2005-08-03 | 雅马哈株式会社 | Semiconductor wafer and its producing method |
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2012
- 2012-03-31 CN CN201210093549.0A patent/CN102683173B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5451801A (en) * | 1989-10-03 | 1995-09-19 | Trw Inc. | Adaptive configurable gate array |
| CN1614771A (en) * | 2003-11-04 | 2005-05-11 | 松下电器产业株式会社 | Semiconductor device and its manufacture |
| CN1649154A (en) * | 2004-01-26 | 2005-08-03 | 雅马哈株式会社 | Semiconductor wafer and its producing method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140425 |
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Effective date of registration: 20140425 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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