Summary of the invention
To the problems referred to above, the purpose of this invention is to provide a kind of rotating speed measurement method of accurate electromechanical equipment, this method all has higher measuring accuracy when the high rotating speed and the slow-speed of revolution.
For realizing above-mentioned purpose; The present invention takes following technical scheme: a kind of motor speed measurement method that is used for accurate electromechanical equipment; It adopts grating encoder that the motor speed of said accurate electromechanical equipment is measured; Step is following: the two-way phase differential that at first export grating encoder (1) is that 90 ° sinusoidal signal is amplified, shaping, makes it become the output of two-way square-wave signal; (2) with carrying out XOR in the two-way square-wave signal input FPGA module, obtain two frequency multiplication signals; (3) in the FPGA module, adopt constant-temperature crystal oscillator as reference clock, two frequency multiplication signals are counted, its count value is N1, and the number that reference clock is counted is N2; Wherein, this constant-temperature crystal oscillator frequency is that 10MHz, degree of stability are ± 5 * 10
-10(4) FPGA module two count value N1, the N2 that will obtain transfer to external microcontroller or dsp chip, according to the relational expression of the frequency of selected constant-temperature crystal oscillator, two count value N1 and N2 and rotating speed and frequency, can obtain the motor speed that will measure.
In the said step (3); The method of counting of said two frequency multiplication signals and reference clock is following: the rising edge that 1. adopts two frequency multiplication signals is a trigger pip; To the reference clock signal counting, produce 1 rising edge,, counting produces 1 negative edge when reaching 10000000 times; At this moment, clock signal D that the high level width is 1S of output; 2. when 1. said step counted beginning, adopting the clock signal D rising edge that produces was trigger pip, and two frequency multiplication signals are counted, and when the negative edge of clock signal D finishes, finished the counting to two frequency multiplication signals, and this moment, count value was N1; 3. when finishing to two frequency multiplication signal-count; As trigger pip, begin when promptly finishing the reference clock signal counting with the negative edge of clock signal D, with the rising edge of two frequency multiplication signals as count end signal; Stop the reference clock signal counting, the count value of this moment is N2.
In the said step (4), motor speed Z
sMethod for solving is following: since the cycle of N1 two frequency multiplication signals with two frequency multiplication signals at last by the time of truncated signal with equal 1 second, then obtain equality:
Obtain the frequency f of two frequency multiplication signals through following formula
xFor:
According to the relational expression of rotating speed and frequency, obtain motor speed Z again
sFor:
In the formula, m is the grating line number of grating encoder; f
cBe the reference clock frequency.
In the said step (4), said FPGA module provides parallel interface and two kinds of interfaces of SPI interface that said enumeration data N1 and N2 are transferred to single-chip microcomputer or dsp chip.
Said parallel interface comprises 8 data lines; 3 address wires; 1 reading signal lines, low level is effective; 1 busy signal line, busy signal are that height is then represented to measure, and busy signal is represented during for low level to measure and finished; 1 heel piece selects signal, and chip selection signal is that low level is effective.
Said serial line interface comprises that 1 heel piece selects signal wire, and low level is effective; 1 clock cable; 1 master goes into from going out signal wire; 1 goes out from going into signal wire and 1 busy signal line with main, and busy signal is that height is then represented to measure, and busy signal is represented to measure during for low level and finished.
The present invention is owing to take above technical scheme, and it has the following advantages: 1, the present invention is because when measuring, in the FPGA module, adopting frequency is that 10MHz, degree of stability are ± 5 * 10
-10Constant-temperature crystal oscillator as reference clock, two frequency multiplication signals of the two-way square-wave signal of grating encoder output are counted, therefore, can improve measuring accuracy effectively.2, the present invention is to two frequency multiplication signal-count the time; When each counting begins; Rising edge with two frequency multiplication signals is the time starting point, and producing a time width is the 1s clock signal of (second), in the time of this 1S; Two frequency multiplication signals are counted, and just the clock signal of 1s will be carried out with two frequency multiplication signals of measured signal synchronously.Owing to when time width is the clock signal negative edge end of 1s, finish to two frequency multiplication signal-count; Calculate motor speed and can produce truncation error this moment, and truncation error is the cycle of two frequency multiplication signals to the maximum, therefore is employed in when finishing two frequency multiplication signal-count; Blocked in the remaining cycle at two frequency multiplication signals reference clock signal is counted; According to the count value of two frequency multiplication signals and reference signal is found the solution motor speed, therefore, can further improve the precision of measurement then.3, the present invention is owing to adopt being to two frequency multiplication signal-count value N1 at time width in the clock signal of 1s; Negative edge when finishing with the clock signal that with the time width is 1s is a starting point, and two frequency multiplication signals by these two count results of count value N2 of the reference signal in the rest period after being blocked, are calculated motor speed jointly; Therefore; No matter motor speed is in lower or higher state, can compensate effect through count value N2, has therefore guaranteed the accuracy that the present invention measures.The present invention can be extensively in various accurate electromechanical equipment tachometric surveies be used.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is carried out detailed description.
A kind of motor speed measurement method that is used for accurate electromechanical equipment provided by the invention, it adopts the high precision grating encoder that the motor speed of accurate electromechanical equipment is measured, and concrete steps are following:
1) the two-way phase differential of at first grating encoder being exported is that 90 ° sinusoidal signal is amplified, shaping, makes it become two-way square-wave signal A, B output.
2) with in two-way square-wave signal A, B input FPGA (CPLD) module, carry out XOR, obtain two frequency multiplication signal X (as shown in Figure 1);
3) in the FPGA module, adopt constant-temperature crystal oscillator as reference clock, two frequency multiplication signal X are counted, its count value is N1, and the number that reference clock is counted is N2; Wherein, reference clock signal is C, and frequency is f
C
As shown in Figure 2, the method for counting of two frequency multiplication signal X and reference clock is following:
1. the rising edge that adopts two frequency multiplication signal X is a trigger pip, to reference clock signal C counting, and produces 1 rising edge, when counting reaches 10000000 times, produces 1 negative edge, at this moment, exports the clock signal D that the high level width is 1S;
2. when 1. step counted beginning, adopting the clock signal D rising edge that produces was trigger pip, and two frequency multiplication signal X are counted, and when the negative edge of clock signal D finishes, finished the counting to two frequency multiplication signal X, and this moment, count value was N1;
Because when the counting that finishes two frequency multiplication signal X; The negative edge of clock signal D might not align with the rising edge of two frequency multiplication signal X, and just therefore the cycle of signal X is contained by truncation part; If the count value N1 that produces with this moment calculates motor speed; Then can produce truncation error, the maximal value of this truncation error is the cycle 1/fx of two frequency multiplication signal X, and fx is the frequency of two frequency multiplication signal X.
3. when finishing to two frequency multiplication signal X counting; As trigger pip, begin counting when promptly finishing to reference clock signal C with the negative edge of clock signal D, with the rising edge of two frequency multiplication signal X as count end signal; Stop the counting to reference clock signal C, the count value of this moment is N2.
4) FPGA module two count value N1, the N2 that will obtain transfer to external microcontroller or dsp chip, according to the relational expression of the frequency of selected constant-temperature crystal oscillator, two count value N1 and N2 and rotating speed and frequency, can obtain the motor speed that will measure.
Above-mentioned steps 3) in, in order to improve the precision of measurement, the constant-temperature crystal oscillator frequency that the present invention adopts in the FPGA module is that 10MHz, degree of stability are ± 5 * 10
-10
Above-mentioned steps 4) in, the method for solving of motor speed is following: since the cycle of N1 two frequency multiplication signal X with two frequency multiplication signal X at last by the time of truncated signal with equal 1 second, therefore, can obtain following equality:
Can obtain the frequency f of two frequency multiplication signal X according to step formula (1)
xFor:
Because two frequency multiplication signal X are two frequency multiplication signals of two-way square-wave signal A, B, therefore can be according to the relational expression of rotating speed and frequency, obtain motor speed Zs (rev/min) expression formula following:
In the following formula, m is the grating line number of grating encoder.
Above-mentioned steps 4) in; Because the tach signal of measuring through the FPGA module is divided into 2 parts; Account for 8 bytes altogether, preceding 4 bytes store are to the counting number N1 of two frequency multiplication signal X, and back four bytes store are to the counting number N2 of reference clock; Therefore, the FPGA module can provide parallel interface and two kinds of interfaces of SPI interface that enumeration data N1 and N2 are transferred to single-chip microcomputer or dsp chip.Be example with the single-chip microcomputer below, specifically introduce the interface of FPGA module and single-chip microcomputer:
Parallel communication interface: as shown in Figure 3, parallel interface comprises 8 data lines; 3 address wires; 1 reading signal lines, low level is effective; 1 busy signal line, busy signal are that height is then represented to measure, and busy signal is represented during for low level to measure and finished; 1 heel piece selects signal, and chip selection signal is that low level is effective.Measure when finishing, single-chip microcomputer can read the count value N1 and the N2 of FPGA module, and calculates motor speed according to formula (3).
As shown in Figure 4, serial communication interface: serial line interface comprises that 1 heel piece selects signal wire, and low level is effective; 1 clock cable; 1 master goes into from going out signal wire; 1 follows the master to go out from going into signal wire and 1 busy signal line, and busy signal is a same signal wire with the busy signal that uses in the parallel interface, the expression same meaning.
In sum, the present invention because when motor speed is low, in width is the synchronizing clock signals D of 1S, has than mistake two frequency multiplication signal X count value N1 of measured signal in use, and the truncation error of this moment is bigger.But owing to be that start time is counted reference clock signal C with the truncated signal simultaneously, count results is N2.The present invention adopts and calculates motor speed jointly by count value N2, N1, has therefore played compensating action.When motor speed was higher, because the frequency of measured signal is higher, the precision of tachometric survey this moment mainly leaned on count value N1 to guarantee that at this moment, count value N2 also can play certain compensating action.
Above-mentioned each embodiment only is used to explain the present invention; The connection of each parts and structure all can change to some extent; On the basis of technical scheme of the present invention; All improvement and equivalents of the connection and the structure of individual component being carried out according to the principle of the invention all should not got rid of outside protection scope of the present invention.