CN102664844A - Method for timing recovering of chip and removing of carrier frequency offset in demodulator - Google Patents
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Abstract
The invention discloses a method for timing recovering of a chip and removing of a carrier frequency offset in a demodulator. A phase discriminator for capturing a modulator of a physical layer of an ultra-low power wireless communication system and timing a tracking chip is provided. The phase discriminator samples by using a sampling clock with the at least twice chip rate, is not affected by the signal carrier frequency offset on timing recovery of the chip, is not sensitive to noise, and can utilize a common low-cost crystal oscillator as a clock source. The used method for timing recovering of the chip is relatively low in realization complexity and calculation complexity. The method for removing of the carrier frequency offset is a quite simple method based on phase differential demodulation and is relatively low in realization complexity and calculation complexity. The method disclosed by the invention can achieve the purpose of removing the effect of the frequency offset on the performance without moving a signal centre frequency, so that the performance of a phase differential demodulator at a certain frequency offset and the performance without the frequency offset are kept consistent.
Description
Technical field
The present invention relates to the method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of ultra-low power consumption wireless communication system physical layer demodulator, belong to wireless communication technology field.
Background technology
ZigBee be a kind of closely, low complex degree, low-power consumption, low data rate, two-way wireless communication technology cheaply.The basis of ZigBee is IEEE 802.15.4, and this is that (Personal Area Network, PAN) working group standard is known as IEEE 802.15.4 (ZigBee) technical standard to the IEEE wireless personal local area network.ZigBee alliance has adopted IEEE802.15.4 as its physical layer and medium Access Layer standard when formulating the ZigBee standard.On its basis, ZigBee alliance has formulated data link layer (DLL), network layer (NWK) and API (APl) standard, and the work of aspects such as responsible higher layer applications, test and marketing.The ZigBee technology mainly is embedded in consumer electronics device, family and the equipment such as building automation equipment, industrial control device, computer peripheral equipment, medical energy converter, toy and game machine; Support among a small circle based on Application for Field such as the control of radio communication and automations, also support geographic positioning functionality simultaneously.ZigBee has very wide application prospect.
In the prior art chip timings of the half-sine OQPSK signal stipulated among the 802.15.4 2450MHz PHY being recovered to eliminate with frequency deviation is the method realization through following:
At first use an analog to digital converter than high sampling rate (ADC) that the Low Medium Frequency or the zero intermediate frequency output signal of Receiver Module are sampled, this sample rate need equal N OQPSK signal spreading rate doubly usually, and wherein N is the integer more than or equal to 4.
Sampled data stream is divided into the rate data streams of N out of phase, and the speed of each data flow equals 1 times of OQPSK signal spreading rate., the chip sequence of leading symbol (preamble) use N parallel correlator (each correlator length is 32 chips) to carry out related operation with the leading symbol that N rate data streams stored respectively at this locality simultaneously respectively during arriving; Compare N correlator output result's peak value then, Dynamic Selection that sampling phase rate data streams that wherein degree of correlation is the highest is sent into the frequency deviation cancellation module.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix afterwards and use the corresponding low speed sampled data stream of the last sampling phase of confirming.
The frequency deviation cancellation module is at leading symbol chip sequence device, and the data flow that upper level is sent into multiply by the multiple sinusoidal signal of M+1 different frequency respectively, produces the data flow of M+1 different frequency deviations; Wherein, the frequency of the multiple sinusoidal signal of this M+1 is generally { M Δ f ,-(M-1) Δ f; ,-Δ f, 0; Δ f ... (M-1) Δ f, M Δ f }.The chip sequence that uses M+1 rate data streams to store respectively at this locality then carries out related operation, and the correlator that it is 32 chips that this process need be used M+1 length again carries out computing.In M+1 correlated results, select the maximum data path of peak value as the final data path that uses.After the chip sequence of leading symbol finishes, stop this comparison procedure, all fix afterwards and use the corresponding low speed sampled data stream of the last sampling phase of confirming.
Existing chip timings method is through using the over-sampling much larger than Nyquist rate; And use a plurality of parallel correlators to obtain one near correct sampling phase initial value; And this sampling phase can't be from the correct sampling phase of motion tracking after the chip sequence of leading symbol finishes; So not only increase the complexity (ADC and more correlator that need higher rate) of equipment, and can cause the sampling clock required precision of equipment very high, increased the cost of equipment greatly.If the use common crystals then can produce too high transmitted error rate, make equipment performance be difficult to the requirement of the standard that reaches (PER when signal to noise ratio snr is 5-6dB < 1%).
The sampling clock required precision that existing frequency deviation removing method uses equipment in the complexity that has increased equipment equally is very high, and after the chip sequence of leading symbol finishes, can't follow the tracks of correct frequency deviation from using.This performance to equipment all has bigger negative interaction with stability.
Summary of the invention
Technical problem to be solved by this invention is:
A kind of phase discriminator of catching and following the tracks of the sheet timing that is used for ultra-low power consumption wireless communication system physical layer demodulator is provided; This phase discriminator makes and uses the sampling clock of minimum 2 times of spreading rates to become possibility, and the influence that not chip timings is recovered by the signal carrier wave frequency deviation.
A kind of very simple carrier wave frequency deviation removing method that is used for ultra-low power consumption wireless communication system physical layer demodulator phase difference demodulator is provided.This method can need not to move signal center frequency and reach the elimination frequency deviation to Effect on Performance.
For solving the problems of the technologies described above; The present invention provides the method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of demodulator; The method that chip timings is recovered and carrier wave frequency deviation is eliminated in a kind of demodulator; It is characterized in that, comprise one be used for ultra-low power consumption wireless communication system physical layer demodulator catch and follow the tracks of sheet phase discriminator regularly, this phase discriminator uses the sampling clock of minimum 2 times of spreading rates to sample.
Said phase discriminator adopts the above any sample rate of 2 times of spreading rates that the intermediate frequency or the baseband signal that receive are sampled,
Interior slotting phase place through the control interpolation filter obtains the sample sequence that uniform sampling is spaced apart Tc/2; { r (n); R (n+1/2), r (n+1), r (n+1+1/2) ...; The odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence;
Phase discriminator calculates the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced as sample-timing error signal Te (n),
Ph_dif1(n)?=?arctan(r(n)/r(n-1/2)) （1）
Ph_dif2(n)?=?arctan(r(n-1/2)/r(n-1)) （2）
Te(n)?=?abs(Ph_dif1(n))-?abs(Ph_dif2(n)) （3）
Wherein, Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that signal turns in two 1/2 chip-spaced; R (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half in the chip and the phase change amount of back half the time.
Sample-timing error signal Te (n) is sent into loop filter promote whole timing loop; The timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is fed back to phase discriminator as the input of said phase discriminator, forms chip timing error close-loop feedback control.
When data contained carrier wave frequency deviation, the step of estimation and elimination frequency deviation was:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input ph_dif (n) of the change amount of a chip phase as differential decoding,
Ph_dif(n)?=?Ph_dif1(n)?+?Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip is pi/2+Δ f*Tc and-pi/2+Δ f*Tc, and in the formula, Tc is a chip period;
If the probability of two kinds of phase change generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct the influence that Δ f*Tc eliminates frequency deviation then,
Ph_dif’(n)?=?Ph_dif(n)?-?E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
The beneficial effect that the present invention reached:
The present invention uses feedback control loop control to catch and follow the tracks of the chip timings recovery; The core of its feedback control loop control is the chip timings phase discriminator; The present invention proposes a kind of implementation method of phase discriminator, the adjustment that this method uses the first half time in the same chip and the change amount of back half the time signal phase to come control loop, the performance of this phase discriminator is not influenced by the carrier wave frequency deviation in the signal; To insensitive for noise; And the chip timings of using this phase discriminator recovers very low to the frequency and the required precision of sampling clock, is merely the arbitrary velocity more than or equal to 2 times spreading rate, can use common low-cost crystal oscillator as the clock source.Chip timings restoration methods used in the present invention has lower implementation complexity and computation complexity.
The carrier wave frequency deviation removing method that the present invention uses is a kind of very simple method based on the phase difference demodulation, and lower implementation complexity and computation complexity are arranged.The present invention need not to move signal center frequency and reaches and eliminate frequency deviation to Effect on Performance, makes that the phase difference demodulator can be consistent in the property retention of the performance under certain frequency deviation when not having frequency deviation.
Description of drawings
Fig. 1 is the theory diagram that is used for ultra-low power consumption wireless communication physical layer demodulator;
Fig. 2 is that the chip timings among Fig. 1 is recovered and the module frame chart of carrier wave frequency deviation cancellation module;
Fig. 3 is a phase discriminator internal structure sketch map among Fig. 2;
Fig. 4 is the internal structure sketch map of the carrier wave frequency deviation cancellation module among Fig. 2.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.Following examples only are used for technical scheme of the present invention more clearly is described, and can not limit protection scope of the present invention with this.
The present invention uses the circuit of " phase discriminator+feedback control loop+interpolater filter " structure to catch and follow the tracks of the most approaching desirable chip samples phase place; Catch simultaneously and tracking frequency offset; Through using a new phase discriminator, the influence that makes frequency deviation is issued to the condition of using the difference phase demodulation method in the prerequisite that does not move frequency spectrum and minimizes.Half-sine OQPSK signal to stipulate in the 802.15.4 2450MHz PHY standard is an example, and the top-level module block diagram of the demodulator that the present invention proposes is as shown in Figure 1, has comprised the digital demodulator of rf analog front-end respectively.Wherein phase discriminator of the present invention and carrier wave frequency deviation cancellation module have been comprised in " chip timings is recovered and carrier wave frequency deviation is eliminated " module; This module frame chart is as shown in Figure 2, and main design of the present invention is a characteristic of utilizing signal itself definition, promptly the phase difference of former and later two chips of half-sine OQPSK signal have only pi/2 with-pi/2 two kinds maybe; If adopting the above any sample rate of 2 times of spreading rates samples to the intermediate frequency or the baseband signal that receive; Can obtain the sample sequence that uniform sampling is spaced apart Tc/2, { r (n), r (n+1/2) through the interior slotting phase place of control interpolation filter; R (n+1); R (n+1+1/2) ..., the odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence.Phase discriminator can calculate the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced in view of the above as sample-timing error signal Te (n),
Ph_dif1(n)?=?arctan(r(n)/r(n-1/2))；（1）
Ph_dif2(n)?=?arctan(r(n-1/2)/r(n-1))；（2）
Te(n)?=?abs(Ph_dif1(n))-?abs(Ph_dif2(n))；（3）
Wherein Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that signal turns in two 1/2 chip-spaced, n the chip estimated value that r (n) exports for interpolation filter.The phase change amount of phase change amount of the first half and back half the time in chip of Te (n).
This difference is sent into loop filter promote whole timing loop; The timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of reconstruction and is fed back to phase discriminator as the input of phase discriminator, forms chip timing error close-loop feedback control.
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input Ph_dif (n) of the change amount of a chip phase as differential decoding
Ph_dif(n)?=?Ph_dif1(n)?+?Ph_dif2(n)；（4）
When the data after the ADC contain carrier wave frequency deviation; Though demodulation uses the mode of phase difference demodulation can tolerate the existence of frequency deviation; But frequency deviation still can cause certain influence to demodulator performance, in order to make the consistent influence that must effectively estimate and eliminate frequency deviation of demodulator performance in certain frequency deviation region.If according to the signal definition frequency deviation is Δ f; Phase changing capacity between adjacent chip becomes pi/2+Δ f*Tc and-pi/2+Δ f*Tc; Suppose that the probability that two kinds of phase change take place is identical (also being like this in the reality); Just can from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct Δ f*Tc then to eliminate the influence of frequency deviation.
Ph_dif’(n)?=?Ph_dif(n)?-?E(Ph_dif(n))；（5）
E (Ph_dif (n))=Δ f*Tc wherein, in the following formula, Tc is a chip period.
Frequency deviation is eliminated both can use feed forward architecture, can also use the feedback control loop control structure.
The reaction type structure of using in the present embodiment, Fig. 3, Fig. 4 have described phase discriminator internal structure and the internal structure of carrier wave frequency deviation cancellation module among Fig. 2 respectively.
The above only is a preferred implementation of the present invention; Should be pointed out that for those skilled in the art, under the prerequisite that does not break away from know-why of the present invention; Can also make some improvement and distortion, these improvement and distortion also should be regarded as protection scope of the present invention.
Claims (5)
1. chip timings is recovered the method with the carrier wave frequency deviation elimination in the demodulator; It is characterized in that; Comprise the phase discriminator of catching and follow the tracks of the sheet timing of a ultra-low power consumption wireless communication system physical layer demodulator, this phase discriminator uses the sampling clock of minimum 2 times of spreading rates to sample.
2. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 1 is characterized in that, said phase discriminator adopts the above any sample rate of 2 times of spreading rates that the intermediate frequency or the baseband signal that receive are sampled,
Interior slotting phase place through the control interpolation filter obtains the sample sequence that uniform sampling is spaced apart Tc/2; { r (n); R (n+1/2), r (n+1), r (n+1+1/2) ...; The odd number sampled point corresponds to chip center sampling sample value constantly in this sequence, and the even number of samples point corresponds to adjacent chip intermediate point sampling instant sample value in this sequence;
Phase discriminator calculates the difference of the phase change amount that signal turns in adjacent two 1/2 chip-spaced as sample-timing error signal Te (n),
Ph_dif1(n)?=?arctan(r(n)/r(n-1/2)) （1）
Ph_dif2(n)?=?arctan(r(n-1/2)/r(n-1)) （2）
Te(n)?=?abs(Ph_dif1(n))-?abs(Ph_dif2(n)) （3）
Wherein, Ph_dif1 (n) and Ph_dif2 (n) are the phase difference that signal turns in two 1/2 chip-spaced; R (n) is n chip estimated value of interpolation filter output, and Te (n) is the phase change amount of the first half in the chip and the phase change amount of back half the time.
3. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 2; It is characterized in that; Sample-timing error signal Te (n) is sent into loop filter promote whole timing loop; The timing offset that interpolation filter produces according to previous stage is estimated to produce in position the sampled data of rebuilding and is fed back to phase discriminator as the input of said phase discriminator, forms chip timing error close-loop feedback control.
4. the method that chip timings is recovered and carrier wave frequency deviation is eliminated in the demodulator according to claim 3 is characterized in that, when data contained carrier wave frequency deviation, the step of estimation and elimination frequency deviation was:
Ph_dif1 (n) and Ph_dif2 (n) addition are obtained the soft information input ph_dif (n) of the change amount of a chip phase as differential decoding,
Ph_dif(n)?=?Ph_dif1(n)?+?Ph_dif2(n)；
If frequency deviation is Δ f, the phase changing capacity between adjacent chip is pi/2+Δ f*Tc and-pi/2+Δ f*Tc, and in the formula, Tc is a chip period;
If the probability of two kinds of phase change generations is identical, from Ph_dif (n), extract DC component and estimate frequency deviation Δ f*Tc, from Ph_dif (n), deduct the influence that Δ f*Tc eliminates frequency deviation then,
Ph_dif’(n)?=?Ph_dif(n)?-?E(Ph_dif(n))
Wherein, E (Ph_dif (n))=Δ f*Tc.
5. chip timings is recovered the method with the carrier wave frequency deviation elimination in the demodulator according to claim 4, it is characterized in that, and the structure of said elimination frequency deviation or be feed forward architecture, or be the feedback control loop control structure.
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| CN103220246A (en) * | 2012-12-14 | 2013-07-24 | 西安英菲泰尔电子科技有限公司 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
| CN108337011A (en) * | 2018-01-16 | 2018-07-27 | 上海富芮坤微电子有限公司 | The construction method of Symbol Synchronization Circuit in GFSK receivers |
| CN109407121A (en) * | 2018-11-15 | 2019-03-01 | 北京遥感设备研究所 | A kind of compatible acquisition and tracking device of configurable navigation signal |
| CN111397645A (en) * | 2020-04-06 | 2020-07-10 | 华中科技大学 | Phase difference decomposition and adjustment method and system |
| CN115473775A (en) * | 2022-07-26 | 2022-12-13 | 西安电子科技大学 | A Parallel Symbol Timing Recovery Method Applicable to LEO Satellite Internet System |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103220246A (en) * | 2012-12-14 | 2013-07-24 | 西安英菲泰尔电子科技有限公司 | Method for timing recovery and combination carrier wave frequency offset elimination of chip in frequency shift keying (FSK) demodulator |
| CN108337011A (en) * | 2018-01-16 | 2018-07-27 | 上海富芮坤微电子有限公司 | The construction method of Symbol Synchronization Circuit in GFSK receivers |
| CN109407121A (en) * | 2018-11-15 | 2019-03-01 | 北京遥感设备研究所 | A kind of compatible acquisition and tracking device of configurable navigation signal |
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| CN115473775A (en) * | 2022-07-26 | 2022-12-13 | 西安电子科技大学 | A Parallel Symbol Timing Recovery Method Applicable to LEO Satellite Internet System |
| CN115473775B (en) * | 2022-07-26 | 2024-04-16 | 西安电子科技大学 | A parallel symbol timing recovery method for low-orbit satellite internet systems |
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