CN102664782B - Discrete transceiver circuit suitable for high-speed 1553 bus - Google Patents

Abstract

The purpose of the present invention is to overcome the deficiencies in the prior art and provide a discrete transceiver circuit suitable for high-speed 1553 bus, including a transmitter and a receiver. The transmitter The transmitter is connected with the protocol processor to complete the transmission of the high-speed Manchester code, including a voltage conversion drive circuit, LDMOS (or NMOS) and a resistor/capacitor with a certain resistance and capacitance. The receiver includes a first-order active filter, a comparator, a voltage reference and a voltage conversion driving circuit, and is connected with the protocol processor through the voltage conversion driving circuit. The advantage is that the present invention realizes the transmission of 1553 bus data at a rate of 10 Mbps by cooperating with an external protocol processor, does not change the original bus structure, and is built with discrete devices, which is flexible and convenient to implement.

Description

Discrete Transceiver Circuit for High Speed 1553 Bus

technical field

The invention relates to a transceiver circuit, in particular to a discrete transceiver circuit suitable for high-speed 1553 bus.

Background technique

MIL-STD-1553 data bus is widely used in aircraft, aviation, aerospace and other fields because of its high reliability and many advantages. In the past half a century, MIL-STD-1553 has been considered as the origin of what we commonly call cyber warfare today. It has realized the information sharing and transmission of various electronic equipment such as sensors, and has fundamentally changed the The way its allies fight. However, with the birth of faster processors, the miniaturization of packaging and the innovation of software technology, the data transmission speed of 1553B, which is only 1Mbps, has undoubtedly become the bottleneck of information and data transmission, and it is imminent to launch a faster transmission method.

The research on the high-speed 1553 bus abroad is relatively early. As early as 2006, John Keller published an article entitled "Rebirth of the 1553 databus" on AVIONICS magazine, introducing the high-speed 1553 bus Extended 1553 developed by Edgewater and the Hyper 1553 of DDC. The way of carrier wave transmission, on the basis of not changing the original cables and interfaces, modulates high-frequency and low-frequency signals into different channels for transmission, realizing high-speed signal transmission on the original 1553 platform. In addition, Andrew D. Parker also published an article entitled "Product Focus: High-Speed 1553: Technology Advances Boost Performance" on AVIONICS magazine, talking about the 10M system between 1M1553 and 100M1553: Enhanced Bitstream 1553 , developed by SAE.

The main disadvantages of the 100M 1553 similar to the Extended 1553 and Hyper1553 are: 1. Although there is no need to change the original bus structure, cables, devices, etc., due to the modulation and demodulation carrier transmission mode, the transceiver circuit part needs Making relatively large changes will greatly increase the development cycle.

As for SAE's 10M1553, according to the article, its transceiver circuit uses the RS485 bus transceiver, which also has some shortcomings: 1. RS485 is an established protocol standard, and there is no room for change in the protocol, and the terminal resistance, wire There are also clear regulations on length and so on, and the flexibility is poor; 2. Although RS485 can reach a transmission speed of 10Mbps and can also transmit a long distance, it is difficult to ensure that the voltage on the bus reaches the 28Vpp required by the 1553 bus specification during high-speed transmission; 3 1. The transceiver circuit using RS485, its transmission medium is no longer the original 1553 cable, it must be replaced by a dedicated RS485 cable, and the bus interface must also be replaced, which will undoubtedly increase the cost of system development and will take a long time It is time to redeploy the existing 1553 system.

Contents of the invention

The purpose of the present invention is to overcome the deficiencies in the prior art, to provide a discrete transceiver circuit suitable for high-speed 1553 bus, and to realize the transmission of 10Mbps rate 1553 bus data by cooperating with an external protocol processor without changing the original The bus structure is built with discrete devices, which is flexible and convenient to implement.

According to the technical solution provided by the present invention, the discrete transceiver circuit applicable to the high-speed 1553 bus includes a transmitter and a receiver, and the transmitter completes Manchester code transmission at a rate of 10 Mbps, including: a voltage conversion drive circuit with a three-state output The input terminal of the voltage conversion driving circuit with three-state output is connected to the protocol processor, the first output terminal of the voltage conversion drive circuit with three-state output is connected to the gate of the first power MOS transistor through a resistor, and the drain of the first power MOS transistor is connected to the first power MOS transistor through a capacitor. The gate of the power MOS tube is connected to the grid, and is connected to pin 1 of the isolation transformer through a resistor; the output end of the voltage conversion drive circuit with three-state output is connected to the grid of the second power MOS tube through a resistor, and the second power MOS tube The drain is connected to the gate of the second power MOS tube through a capacitor, and connected to pin 3 of the isolation transformer through a resistor; the two ends of the input coil of the isolation transformer are pin 1 and pin 3, and the middle tap of the input coil is pin 2. The two ends of the output coil are 4-pin and 8-pin respectively, and the three intermediate taps are 5-pin, 6-pin, and 7-pin in turn, of which 3-pin and 8-pin are terminals with the same name, 2-pin of the isolation transformer is connected to +5V power supply, and 5-pin and the indirect load between pin 7; the receiver includes: the positive input of the bus positive Manchester code analog signal connected to the negative input of the first first-order active filter and the positive input of the second first-order active filter, and the negative Manchester code of the bus The analog signal is connected to the positive input of the first first-order active filter and the negative input of the second first-order active filter; the output of the first first-order active filter is connected to the negative input of the first comparator, The positive input terminal of the first comparator is connected to the voltage reference, and the negative output terminal of the first comparator outputs a negative Manchester code digital signal, which is sent to the receiving negative signal terminal of the protocol processor through voltage conversion; the output of the second first-order active filter The terminal is connected to the negative input terminal of the second comparator, the positive input terminal of the second comparator is connected to the voltage reference, the negative output terminal of the second comparator outputs a positive Manchester code digital signal, and is sent to the receiving positive signal of the protocol processor after voltage conversion end.

The protocol processor sends the 3.3V signal to the transmitter. The voltage conversion driver adopts the integrated circuit SN74LVC2T45. The voltage conversion driver converts the 10Mbps, 3.3V signal into a 10Mbps, 5V signal, and converts the first power MOS tube and the second power MOS tube The level of the gate of the tube is raised to ensure that the drain has a large enough current during high-speed data transmission, and the VCC of the integrated circuit SN74LVC2T45 can be used as the enable terminal of the transmitter.

The first power MOS transistor and the second power MOS transistor are LDMOS or NMOS.

The LDMOS or NMOS adopts a high-speed power transistor with a switching speed not lower than 1800MHz, which satisfies the turn-on voltage of 1.9V, and when the gate-source voltage reaches 5.65V, the drain current can reach 3.1A.

The receiver receives the 10MHz Manchester code from the 1553 bus, and generates a TTL level signal matching the protocol processor through filtering, comparison, and level conversion.

The bandwidth of the first first-order active filter and the second first-order active filter is not lower than 140MHz, and the conversion rate is not lower than 480V/μs.

The frequency of the input terminal of the comparator is not lower than 90MHz, and has a delay of 4ns under the working voltage of 5V.

The voltage reference provides a stable 1.8V output voltage reference.

The advantages of the present invention are:

1) Do not change the original bus structure, do not need to change cables and interface methods, saving a lot of cost and time;

2) It is built with discrete devices, which saves expensive tape-out costs and is flexible and convenient to implement;

3) Due to the use of discrete devices, the requirements of different transmission rates can be met by changing parameters such as different capacitors and resistors, and it has good versatility and strong scalability.

Description of drawings

Fig. 1 is a circuit block diagram of a protocol processor related to the present invention.

Fig. 2 is the circuit pin diagram of the SN74LVC2T45 voltage conversion driver circuit of the present invention model.

Fig. 3 is the pin diagram of the BLF6G21-10G LDMOS of the present invention.

Fig. 4 is a pin diagram of the isolation transformer of the present invention.

Fig. 5 is the circuit pin diagram of THS4521 high-speed operational amplifier model of the present invention.

Fig. 6 is the pin diagram of the AD8611 comparator circuit of the present invention.

Fig. 7 is a pin diagram of the LM4120-1.8 voltage reference circuit of the present invention.

Fig. 8 is a structural block diagram of the high-speed 1553 bus discrete device transmitter of the present invention.

Fig. 9 is a structural block diagram of the high-speed 1553 bus discrete device receiver of the present invention.

Fig. 10 is a circuit schematic diagram of the first-order active filter of the present invention.

Fig. 11 is a schematic diagram of the voltage reference circuit of the present invention.

Fig. 12 is a schematic diagram of the comparator circuit of the present invention.

Detailed ways

The present invention will be further described below in conjunction with drawings and embodiments.

The present invention adopts the method of building discrete devices, and is divided into two parts: a transmitter and a receiver.

The transmitter is connected with the protocol processor to complete the transmission of high-speed Manchester code. It consists of a bidirectional voltage conversion driver with three-state output, LDMOS (or NMOS) and resistors/capacitors with certain resistance and capacitance. The structural block diagram of the high-speed protocol processor circuit, and the circuit pin diagrams of SN74LVC2T45 and LDMOS-BLF6G21-10G are shown in Figure 1, Figure 2 and Figure 3, respectively.

As shown in Figure 1, the high-speed protocol processor circuit includes: a dual-channel communication protocol processing module, an external interface logic module, a configuration register module, a storage management module, a bit width selection module, a bus monitoring module, a bus control module, and a remote terminal Control module and clock/reset module; the dual-channel communication protocol processing module, configuration register module, storage management module, bit width selection module, bus monitoring module, bus control module, remote terminal control module and clock/reset module through the 1533 bus interconnected, the dual-channel communication protocol processing module is connected to external devices through an external interface logic module. The external interface logic module includes a terminal for sending a positive signal Txa, a terminal for sending a negative signal Txa_n, a terminal for receiving a positive signal Rxa, and a terminal for receiving a negative signal Rxa_n.

The transmitter completes Manchester code transmission at a rate of 10 Mbps, including: the input end of the voltage conversion drive circuit with three-state output is connected to the protocol processor, and the first output terminal B1 of the voltage conversion drive circuit with three-state output passes through The resistor is connected to the gate of the first power MOS transistor M1, the drain of the first power MOS transistor M1 is connected to the gate of the first power MOS transistor M1 through a capacitor, and connected to pin 1 of the isolation transformer through a resistor; the three-state The output terminal B2 of the output voltage conversion drive circuit is connected to the gate of the second power MOS transistor M2 through a resistor, and the drain of the second power MOS transistor M2 is connected to the gate of the second power MOS transistor M2 through a capacitor, and is isolated through a resistor connection 3 pins of the transformer. The receiver includes: the bus positive Manchester code analog signal RXIN+ is connected to the negative input terminal of the first first-order active filter and the positive input terminal of the second first-order active filter, and the bus negative Manchester code analog signal RXIN- is connected to the second The positive input of the first-order active filter and the negative input of the second first-order active filter; the output of the first first-order active filter is connected to the negative input of the first comparator, and the first comparator The positive input terminal is connected to the voltage reference, and the negative output terminal of the first comparator outputs a negative Manchester code digital signal RXOUT-, which is sent to the receiving negative signal terminal Rxa_n of the protocol processor after voltage conversion; the output terminal of the second first-order active filter Connect the negative input terminal of the second comparator, the positive input terminal of the second comparator is connected to the voltage reference, the negative output terminal of the second comparator outputs the positive Manchester code digital signal RXOUT+, and sends it to the receiving positive signal of the protocol processor after voltage conversion Terminal Rxa.

The integrated circuit SN74LVC2T45 is a bidirectional voltage conversion driver with a three-state output. Since the signal sent by the protocol processor to the transmitter is a 3.3V level signal, in order to ensure that the drain of the LDMOS has a large enough current during high-speed data transmission, the level of the gate needs to be raised. The voltage conversion driver can convert the 3.3V high-speed level signal into a 5V high-speed level signal. The A1 and A2 pins of the circuit SN74LVC2T45 are respectively connected to the positive signal terminal Txa and the negative signal terminal Txa_n of the protocol processor, and VCC is used as Transmitter enable terminal.

LDMOS adopts NXP's high-speed power transistor BLF6G21-10G, the switching speed is not lower than 1800MHz, the turn-on voltage is 1.9V, when the gate-source voltage reaches 5.65V, the drain current can reach 3.1A, and the input and output capacitance is several pF~tens Between a few pF, it meets the design requirements.

The pinout of the isolation transformer is shown in Figure 4. The effective output end of the isolation transformer is a transformer coupling output end of 1:1.79, and the middle tap (pin 2) of the input end of the transformer is connected to the +5V power supply. The two ends of the input coil of the isolation transformer are 1-pin and 3-pin respectively, the middle tap of the input coil is 2-pin, the two ends of the output coil of the isolation transformer are 4-pin and 8-pin respectively, and the three middle taps are 5-pin and 6-pin in turn , 7 feet. Among them, pin 3 and pin 8 are terminals with the same name, and pin 5 and pin 7 are indirectly loaded.

The receiver part receives the high-speed Manchester code from the 1553 bus, and generates a TTL level signal that matches the protocol processor through filtering, comparison, and level conversion.

The filter is a first-order active filter built with a high-speed operational amplifier. It is required that the bandwidth is not lower than 140MHz, and the conversion rate is not lower than 480V/μs. The schematic diagram of the circuit is shown in Figure 10.

The comparator used requires the device to have a delay of less than 4ns under 5V operating voltage under the condition that the frequency of the input terminal is not lower than 90MHz. The voltage reference in the comparator is required to provide a stable 1.8V output voltage reference, and its circuit schematic diagram is shown in Figure 12.

The filter adopts the first-order active filter built by TI's operational amplifier THS4521. The bandwidth of THS4521 can reach 145MHz, and the conversion rate can reach 490V/μs. Its pins are shown in Figure 5.

The comparator adopts the comparator AD8611 of ADI Company, the frequency of the input terminal of this device can reach 100MHz, and it has a time delay of 4ns under the working voltage of 5V, as shown in Figure 6.

The voltage reference in the comparator adopts LM4120 from National Semiconductor Company, which can provide a stable 1.8V output voltage reference, as shown in Figure 7, and its circuit schematic diagram is shown in Figure 11.

The transceiver circuit of the high-speed 1553 bus discrete device of the present invention is divided into two parts: sending and receiving. For the discrete device transmitter shown in the dotted line box in Figure 8, the protocol processor generates a pair of differential signals Txa, Txa_n and sends them to the A1 and A2 ports of the SN74LVC2T45. To control the on and off of the transmitter, the power supply terminal VCCB is connected to a 5.0V power supply. This is because the protocol processor uses a 3.3V standard port voltage. In order to ensure that the LDMOS has enough current to drive the next stage, the protocol processor outputs The signal is converted to 5V voltage by a level conversion device. The direction control terminal DIR is connected to a high level, so that the data signal is sent from the A terminal to the B terminal. The ground terminal GND is connected to the ground terminal of the circuit board. The level-shifted signal passes through a 10Ω resistor to reduce signal reflection. Then the two differential signals are respectively sent to the gate Pin2 of the two LDMOS transistors, the source Pin3 is connected to the substrate and connected to the ground, and the drain Pin1 is used as the output and a 2Ω resistor is connected in series to the primary terminals Pin1 and Pin3 of the transformer. The gate and drain of the LDMOS are connected across a 100pF feedback capacitor to adjust the staircase phenomenon of the signal. The signal passes through the isolation transformer to the secondary, and the load is connected between pin 5 and pin 7 of the isolation transformer. The transmitter works as follows.

When the Mann code corresponding to Txa is high level, the Mann code corresponding to Txa_n should be low level. At this time, the first power MOS transistor in Figure 8 is turned on, so the No. 1 tap of the transformer is pulled to the ground, and the current flows from the middle The tap Pin2 flows to the No. 1 tap, and the coupling between the No. 3 tap and the middle tap at the input end of the transformer generates a current in the opposite direction, so that a Mann code of positive and negative levels is formed between the No. 1 and No. 3 taps; similarly, when When the Mann code corresponding to Txa_n is high level, the Mann code corresponding to Txa should be low level. At this time, the second power MOS transistor is turned on, so the No. 3 tap of the transformer is pulled to the ground, and the current flows from the middle tap to No. 3 tap. flow. Coupling between tap 1 and the middle tap at the input end of the transformer produces opposite currents, so that Mann codes of positive and negative levels are also formed between taps 1 and 3.

The output of the transmitter is directly connected to the input of the receiver, that is, TXOUT+ in Figure 8 is connected to RXIN+ in Figure 9, and TXOUT- in Figure 8 is connected to RXIN- in Figure 9, through the first-order active in Figure 9 The filter (see Figure 10), the comparator (see Figure 12), and the voltage conversion driver model SN74LVC2T45 are sent to the Rxa and Rxa_n terminals of the protocol processor respectively.

The first-order active filter is composed of a high-speed operational amplifier. The differential signal output by the transmitter is divided by 1/2 and connected to its differential input terminals Pin1 and Pin8 to reduce the common-mode voltage signal so that the operational amplifier can respond normally. The power supply Vs+ (Pin3) is connected to +5V, Vs- (Pin6) is grounded, and the common mode voltage input terminal VOCM (Pin2) is connected to a 0.1uF capacitor to ground to reduce coupling noise on the pins.

For a first-order active filter, its cutoff frequency is:

(Formula 1)

By selecting appropriate R and C values, signals within a certain frequency range can pass through. In order to avoid the influence of high-frequency noise signal on the normal Mann code, here we choose: , substituting into formula 1 has:

(Formula 2)

Right now , which can satisfy the fifth harmonic component of the square wave to pass, while higher harmonic components (mostly noise) are filtered out.

In order to enable the comparator to have higher sensitivity, the output signal of the filter needs to be amplified, and the amplification factor is selected to be 6 here. Therefore, the positive output VOUT+ (Pin4) of the operational amplifier and the negative input VIN- (Pin1) are connected across the feedback resistor R _F .

The magnification of the operational amplifier is determined by the following formula:

(Formula 3)

The output (Pin4) of the active filter is connected to the negative input terminal IN- (Pin3) of the comparator, and the gate of the comparator is limited to 1.8V, so the voltage reference is the input terminal VIN (Pin4) of the LM4120 and the enable terminal Enable ( Pin3) is connected to the +5V power supply, the REF terminal (Pin1) is suspended, GND (Pin2) is connected to the common ground terminal, and its output (VOUT) is connected to the positive input terminal IN+ (Pin2) of the comparator. When the level of the filter output waveform is higher than 1.8V, the output level is high (+5V), and when the output level is lower than 1.8V, the output level is low (0V). In this way, the Manchester code after the bus transmission is filtered and shaped to prevent the noise signal from causing the protocol processor to misoperate.

Finally, the output 5V signal needs to go through a level conversion circuit to convert it into a 3.3V level signal that the protocol processor can receive. The input terminals A1 and A2 are respectively connected to RXOUT- and RXOUT+. Unlike the connection of the voltage conversion driver in the transmitter, the receiver does not need to be enabled, so VCCA is connected to a fixed 3.3V level, and DIR is grounded so that the data The signal is sent from terminal B to terminal A. The output signals B1 and B2 are respectively sent to Rxa_n and Rx of the protocol processor.

Claims (8)

1. be applicable to the discrete transceiver circuit of 1553 buses at a high speed, comprise transmitter and receiver, it is characterized in that: the Manchester code that described transmitter completes 10Mbps speed sends, comprise: the input of the voltage transitions drive circuit of band ternary output is connected with protocol processor, A1 and the A2 pin of circuit SN74LVC2T45 meets transmission positive signal end Txa, the transmission negative signal end Txa_n of protocol processor respectively, and VCC is used as the Enable Pin of transmitter; First output (B1) of the voltage transitions drive circuit of described band ternary output is connected by the grid of resistance with the first power MOS pipe (M1), first power MOS pipe (M1) drain electrode is connected with the first power MOS pipe (M1) grid by electric capacity, and is connected with 1 pin of isolating transformer by resistance; The output (B2) of the voltage transitions drive circuit of described band ternary output is connected by the grid of resistance with the second power MOS pipe (M2), second power MOS pipe (M2) drain electrode is connected with the second power MOS pipe (M2) grid by electric capacity, and connects 3 pin of isolating transformer by resistance; The two ends of isolating transformer input coil are respectively 1 pin and 3 pin, the centre tap of input coil is 2 pin, the two ends of isolating transformer output winding are respectively 4 pin and 8 pin, three centre taps are followed successively by 5 pin, 6 pin, 7 pin, wherein 3 pin and 8 pin are Same Name of Ends, 2 pin of isolating transformer connect+5V power supply, the indirect load of 5 pin and 7 pin; Described receiver comprises: the positive Manchester code analog signal (RXIN+) of bus connects the negative input end of the first first-order active filter and the positive input terminal of the second first-order active filter, and bus is born Manchester code analog signal (RXIN-) and connect the positive input terminal of the first first-order active filter and the negative input end of the second first-order active filter; The output of the first first-order active filter connects the negative input end of the first comparator, first comparator positive input termination voltage reference, first comparator negative output terminal exports negative Manchester code digital signal (RXOUT-), and delivers to the reception negative signal end (Rxa_n) of protocol processor through voltage transitions; The output of the second first-order active filter connects the negative input end of the second comparator, second comparator positive input termination voltage reference, the negative output terminal of the second comparator exports positive Manchester code digital signal (RXOUT+), and delivers to the reception positive signal end (Rxa) of protocol processor through voltage transitions.

2. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 1, it is characterized in that, protocol processor gives transmitter 3.3V signal, voltage transitions driver adopts integrated circuit SN74LVC2T45, the signal of 10Mbps, 3.3V is converted to the signal of 10Mbps, 5V by voltage transitions driver, the level of the first power MOS pipe (M1) and the second power MOS pipe (M2) grid is raised, during guarantee high speed data transfer, drain terminal has enough large electric current, and the VCC of integrated circuit SN74LVC2T45 can be used as the Enable Pin of transmitter simultaneously.

3. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 1, it is characterized in that, described first power MOS pipe (M1) and the second power MOS pipe (M2) are LDMOS or NMOS.

4. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 3, it is characterized in that, described LDMOS or NMOS adopts switching speed to be not less than 1800MHz high-speed power transistor, meets cut-in voltage 1.9V, and when gate source voltage reaches 5.65V, drain current can reach 3.1A.

5. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 1, it is characterized in that, described receiver receives the Manchester code of 10MHz from 1553 buses, by filtering, compare, level conversion produces the Transistor-Transistor Logic level signal mated with protocol processor.

6. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 1, it is characterized in that, described first first-order active filter and the second first-order active filter require that bandwidth is not less than 140MHz, and switching rate is not less than 480V/ μ s.

7. be applicable to the discrete transceiver circuit of at a high speed 1553 buses as claimed in claim 1, it is characterized in that, the frequency of comparator input terminal is not less than 90MHz, and the time delay of 4ns under there is 5V operating voltage.

8. be applicable to the discrete transceiver circuit of 1553 buses at a high speed as claimed in claim 1, it is characterized in that, described voltage reference provides stable 1.8V output voltage benchmark.