CN102664152A - NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and device structure - Google Patents
NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and device structure Download PDFInfo
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- CN102664152A CN102664152A CN201210170372XA CN201210170372A CN102664152A CN 102664152 A CN102664152 A CN 102664152A CN 201210170372X A CN201210170372X A CN 201210170372XA CN 201210170372 A CN201210170372 A CN 201210170372A CN 102664152 A CN102664152 A CN 102664152A
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- tension stress
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- carrier mobility
- hard mask
- nmos device
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 239000004065 semiconductor Substances 0.000 title abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title abstract 2
- 150000004706 metal oxides Chemical class 0.000 title abstract 2
- 239000000463 material Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 238000005516 engineering process Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims description 25
- 238000012856 packing Methods 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000005549 size reduction Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000002800 charge carrier Substances 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000000908 ammonium hydroxide Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000001312 dry etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to the manufacturing field of integrated circuits, in particular to an NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and a device structure. The NMOS device manufacturing method includes the following steps of providing a substrate containing an NMOS active area and a circumferential area, forming a plurality of shallow groove isolation structures in the circumferential area of the substrate; etching areas on the substrate between adjacent shallow groove isolation structures to form tensile stress grooves; and filling tensile stress materials in the tensile stress grooves. By the aid of the NMOS device manufacturing method, shape of the NMOS device is free from damage, performance interference by manufacturing technology can be avoided, technological requirements for the manufacturing technology are low, continuous size reduction of the NMOS device is facilitated, meanwhile the carrier mobility can be improved, and accordingly performance of the NMOS device is improved.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of manufacture method and device architecture that improves the nmos device of carrier mobility.
Background technology
Along with development of semiconductor, the semiconductor related manufacturing process is constantly brought forth new ideas and the IC chip size development trend of constantly dwindling proportionally, inevitably makes transistor and the constant material and the physical effect of other elements runnings be affected.Get into after the 40nm technology, how to improve device performance, when reaching high firing current, suppress to turn-off the key problem that electric leakage becomes designs.
It is more and more obvious in the aspect of performance role of semiconductor technology and device that the proof stress engineering is implemented in research, the stress engineering suit on the semiconductor device of improvement transistor carrier mobility, thereby improve performance of semiconductor device.
Keeping the key factor of performance in the field-effect transistor is carrier mobility, and different types of stress has different influence to the charge carrier in the device (being electronics and hole) mobility.The suffered stressor layers influence of mobility of charge carrier rate discloses in the stress field of current semiconductor device to some extent; Be to apply tension stress on the channel direction of nmos device; Then can the electron mobility in the nmos device be greatly improved, thereby improve the performance of nmos device.
Propose a large amount of structure and materials in the prior art and be applied to comprise in the semi-conducting material tension stress or compression; For example in Chinese patent CN102110611A, provide a kind of and directly in the source area of NMOS, contact hole above the drain region, form material, for example tungsten with tension stress character; Thereby the channel region to NMOS applies tension stress; Then optionally remove all or part of grid structure layer, thereby the nmos device channel region is applied the manufacture method of tension stress, but this manufacture craft has changed original device shape and character; Device performance is caused interference; And manufacturing process is complicated, can not effectively reduce the technology cost, and be unfavorable for device size continue dwindle.
Summary of the invention
The shortcoming of prior art in view of the above; The present invention provides a kind of manufacture method of new semiconductor device; Can not damage and avoid the interference of manufacture craft to device shape to device performance; And manufacture process requirement is low, also help device size continue dwindle, improve device performance thereby improved carrier mobility simultaneously.
For realizing above-mentioned purpose and other relevant purposes, a kind of manufacture method that improves the nmos device of carrier mobility is provided, may further comprise the steps: the substrate that comprises NMOS active area and neighboring area is provided; Form a plurality of shallow trench isolations in the neighboring area of said substrate from (STI) structure; The adjacent shallow trench isolation of etching from the substrate between (STI) structure to form the tension stress groove; And in said tension stress groove, fill the tension stress material.
Alternatively, the step that forms a plurality of fleet plough groove isolation structures in the neighboring area of said substrate comprises: on said substrate, form oxide layer; On said oxide layer, form hard mask layer; On said hard mask layer, form patterned photoresist; With said patterned photoresist is that said hard mask layer of mask etching and oxide layer form patterned hard mask layer and patterned oxide layer; With said patterned hard mask layer is mask, and the said substrate of etching forms isolated groove; In said isolated groove and on the patterned hard mask layer, form packing material; Carry out chemical mechanical milling tech and remove the packing material on the patterned hard mask layer; And carry out the packing material that etching technics is removed the isolated groove top, to form fleet plough groove isolation structure.
Alternatively, in said tension stress groove, fill after the step of tension stress material, also comprise: remove remaining patterned hard mask layer and said patterned oxide layer.
Alternatively, in said tension stress groove, fill after the step of tension stress material, also comprise: on said NMOS active area, form grid structure; Form grid curb wall at said grid structure sidewall; And carry out ion implantation technology and form P type well region.
Alternatively, the substrate between the fleet plough groove isolation structure that wet etching is adjacent is to form the tension stress groove.
Alternatively, in said tension stress groove, fill the tension stress material through epitaxially grown mode.
Alternatively, said tension stress material is SiC.
Alternatively, said hard mask layer is a silicon nitride layer.
The present invention also comprises a kind of nmos device that adopts said method to make.
As stated; The present invention forms a plurality of shallow trench isolations from (STI) structure through the neighboring area at substrate; Substrate between the adjacent fleet plough groove isolation structure of etching to be forming the tension stress groove, and in said tension stress groove, fills the tension stress material, and then puts on this tension stress of nmos device channel region through fleet plough groove isolation structure; Can not damage and avoid the interference of manufacture craft to device shape to device performance; And manufacture process requirement is low, also help device size continue dwindle, improve device performance thereby improved carrier mobility simultaneously.
Description of drawings
Fig. 1 to Fig. 9 is the generalized section of each step corresponding construction of the nmos device manufacture method that the embodiment of the invention provided;
Figure 10 is the flow chart of the nmos device manufacturing approach that the embodiment of the invention provided
The element numbers explanation
Patterned oxide layer 11a
Patterned hard mask layer 12a
Isolated groove 14a
Fleet plough groove isolation structure 14
Grid oxic horizon 171
Polysilicon gate 172
Grid curb wall 173
Source, drain region 18
Embodiment
Below through specific instantiation execution mode of the present invention is described, those skilled in the art can understand other advantages of the present invention and effect easily by the content that this specification disclosed.The present invention can also implement or use through other different embodiment, and each item details in this specification also can be based on different viewpoints and application, carries out various modifications or change under the spirit of the present invention not deviating from.
Need to prove; The diagram that is provided in the present embodiment is only explained basic conception of the present invention in a schematic way; Satisfy only show in graphic with the present invention in relevant assembly but not component count, shape and plotted when implementing according to reality; Kenel, quantity and the ratio of each assembly can be a kind of random change during its actual enforcement, and its assembly layout kenel also maybe be more complicated.
The present invention provides a kind of and improves the stress that channel region is applied through tension stress structural stress engineering; Thereby improve the method for carrier mobility; In conjunction with Figure 10, it may further comprise the steps for the flow chart of the nmos device manufacturing approach that the embodiment of the invention provided, this method:
Step S1 provides the substrate that comprises NMOS active area and neighboring area;
Step S2 forms a plurality of fleet plough groove isolation structures in the neighboring area of said substrate;
Step S3, the substrate between the adjacent fleet plough groove isolation structure of etching is to form the tension stress groove; And
Step S4 fills the tension stress material in said tension stress groove.
To combine generalized section that the method and the device architecture thereof of this raising carrier mobility of the present invention are described in more detail below; The preferred embodiments of the present invention have wherein been represented; Should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.
At first, execution in step S1 provides the substrate 10 that comprises NMOS active area and neighboring area, and said substrate 10 includes but not limited to silicon, germanium, silicon-germanium alloy substrate etc., preferred silicon substrate in the present embodiment.
Then, execution in step S2 forms a plurality of shallow trench isolations from (STI) structure in the neighboring area of said substrate 10, to shown in Figure 5, specifically adopt following steps like Fig. 1:
As shown in Figure 1, on said substrate 10, form oxide layer 11, adopt thermal oxidation technology to form oxide layer 11 in the present embodiment, said oxide layer 11 materials are silicon dioxide, its compact structure can be protected underlying substrate 10 when forming hard mask layer 12; Then, on said oxide layer 11, form hard mask layer 12, hard mask layer 12 preferably uses silicon nitride material in the present embodiment.Said hard mask layer 12 can utilize technology well known in the art to form, and for example adopts but is not limited to chemical vapor deposition (CVD) technology; Afterwards, on said hard mask layer 12, form patterned photoresist 13;
As shown in Figure 2; With said patterned photoresist 13 is that the said hard mask layer 12 of mask etching forms patterned hard mask layer 12a and patterned oxide layer 11a with oxide layer 11; Remove the patterned photoresist 13 on the hard mask layer 12 then; Be mask with said patterned hard mask layer 12a then, the said substrate 10 of dry etching forms isolated groove 14a;
As shown in Figure 3, form packing material 15 in said isolated groove 14a and on the patterned hard mask layer 12a, said packing material generally uses silicon dioxide;
As shown in Figure 4, cmp (CMP) is removed the packing material 15 on the patterned hard mask layer 12a, makes the surface of remaining packing material and the flush of patterned hard mask layer 12a;
As shown in Figure 5, wet etching is removed the packing material of said isolated groove 14a top, thereby forms shallow trench isolation from (STI) structure 14.
Then, execution in step S3, the adjacent shallow trench isolation of etching to form tension stress groove 16a, to shown in Figure 7, specifically adopts following steps like Fig. 6 from the substrate between (STI) structure 14:
As shown in Figure 6, remove patterned hard mask layer and the patterned oxide layer of adjacent shallow trench isolation from substrate 10 tops between (STI) structure 14, preferably adopt wet-etching technology here, generally select for use phosphoric acid corrosion liquid to accomplish;
As shown in Figure 7, the adjacent shallow trench isolation of etching to form tension stress groove 16a, preferably adopts wet-etching technology from the substrate 10 between (STI) structure 14 here, generally select for use alkaline solution for example ammonium hydroxide accomplish.
Then; Execution in step S4; In said tension stress groove 16a, fill the tension stress material and form tension stress structure 16, as shown in Figure 8, in said tension stress groove 16a, fill the tension stress material through epitaxially grown mode; Usually adopt the process for vapor phase epitaxy method in said tension stress structure 16, to fill tension stress material, the preferred carbofrax material of said tension stress material in the present embodiment.
Further, in said tension stress groove 16a, fill after the step of tension stress material, as shown in Figure 8, remove remaining patterned hard mask layer 12a and said patterned oxide layer 11a.
At last; As shown in Figure 9, carry out ion implantation technology and form P type well region (not shown), and on said NMOS active area, form grid structure 17; Said grid structure 17 comprises grid oxic horizon 171 and polysilicon gate 172, and forms grid curb wall 173 at said grid structure 17 sidewalls.After forming grid structure 17, ion injects formation source, drain region 18.
Shown in figure 10, the tension stress that tension stress structure 16 produces puts on the sketch map that the nmos device channel region is formed at the channel direction tension stress through shallow trench isolation from (STI) structure 14.Because carborundum (SiC) is inconsistent with silicon (Si) lattice; Tension stress generates thereupon when through epitaxial growth original pattern filling being substituted by carborundum (SiC), and tension stress puts on said nmos device channel region through said shallow trench isolation from (STI) structure subsequently.The process for making of being enumerated by present embodiment can not damage and avoid the interference of manufacture craft to device performance to device shape; And manufacture process requirement is low; Also help device size continue dwindle, improve device performance thereby improved carrier mobility simultaneously.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention.Any be familiar with this technological personage all can be under spirit of the present invention and category, the foregoing description is modified or is changed.Therefore, have common knowledge the knowledgeable in the affiliated such as technical field, must contain by claim of the present invention not breaking away from all equivalence modifications of being accomplished under disclosed spirit and the technological thought or changing.
Claims (9)
1. a manufacture method that improves the nmos device of carrier mobility is characterized in that, comprising:
The substrate that comprises NMOS active area and neighboring area is provided;
Form a plurality of fleet plough groove isolation structures in the neighboring area of said substrate;
Substrate between the adjacent fleet plough groove isolation structure of etching is to form the tension stress groove; And
In said tension stress groove, fill the tension stress material.
2. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that: the step that forms a plurality of fleet plough groove isolation structures in the neighboring area of said substrate comprises:
On said substrate, form oxide layer;
On said oxide layer, form hard mask layer;
On said hard mask layer, form patterned photoresist;
With said patterned photoresist is that said hard mask layer of mask etching and oxide layer form patterned hard mask layer and patterned oxide layer;
With said patterned hard mask layer is mask, and the said substrate of etching forms isolated groove;
In said isolated groove and on the patterned hard mask layer, form packing material;
Carry out chemical mechanical milling tech and remove the packing material on the patterned hard mask layer; And
Carry out etching technics and remove the packing material of isolated groove top, to form fleet plough groove isolation structure.
3. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that, in said tension stress groove, fills after the step of tension stress material, also comprises:
Remove remaining patterned hard mask layer and said patterned oxide layer.
4. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that, in said tension stress groove, fills after the step of tension stress material, also comprises:
Carry out ion implantation technology and form P type well region;
On said NMOS active area, form grid structure; And
Form grid curb wall at said grid structure sidewall.
5. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that: the substrate between the adjacent fleet plough groove isolation structure of wet etching is to form the tension stress groove.
6. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that: in said tension stress groove, fill the tension stress material through epitaxially grown mode.
7. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that: said tension stress material is SiC.
8. the manufacture method of the nmos device of raising carrier mobility according to claim 1 is characterized in that: said hard mask layer is a silicon nitride layer.
9. one kind is adopted any nmos device that described manufacture method is made of claim 1-8.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210170372XA CN102664152A (en) | 2012-05-28 | 2012-05-28 | NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and device structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210170372XA CN102664152A (en) | 2012-05-28 | 2012-05-28 | NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and device structure |
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| CN201210170372XA Pending CN102664152A (en) | 2012-05-28 | 2012-05-28 | NMOS (N-channel metal oxide semiconductor) device manufacturing method capable of improving carrier mobility and device structure |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050233540A1 (en) * | 2004-04-15 | 2005-10-20 | Texas Instruments, Incorporated | Minimizing transistor variations due to shallow trench isolation stress |
| US20070090484A1 (en) * | 2005-08-25 | 2007-04-26 | Chartered Semiconductor Manufacturing, Ltd. | Integrated circuit stress control system |
| US20070111452A1 (en) * | 2005-11-16 | 2007-05-17 | Pei-Yu Chou | fabricating method of cmos and mos device |
| US7384851B2 (en) * | 2005-07-15 | 2008-06-10 | International Business Machines Corporation | Buried stress isolation for high-performance CMOS technology |
-
2012
- 2012-05-28 CN CN201210170372XA patent/CN102664152A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050233540A1 (en) * | 2004-04-15 | 2005-10-20 | Texas Instruments, Incorporated | Minimizing transistor variations due to shallow trench isolation stress |
| US7384851B2 (en) * | 2005-07-15 | 2008-06-10 | International Business Machines Corporation | Buried stress isolation for high-performance CMOS technology |
| US20070090484A1 (en) * | 2005-08-25 | 2007-04-26 | Chartered Semiconductor Manufacturing, Ltd. | Integrated circuit stress control system |
| US20070111452A1 (en) * | 2005-11-16 | 2007-05-17 | Pei-Yu Chou | fabricating method of cmos and mos device |
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Application publication date: 20120912 |