CN102655410B - Voltage controlled oscillator, and test system and test method for detecting technological fluctuation - Google Patents

Abstract

The invention belongs to the technical field of microelectronics, and specifically relates to a voltage-controlled oscillator (VCO), a test system for detecting process fluctuations and a test method thereof. The VCO includes a ring oscillator and a flow control MOS tube, and the ring oscillator includes an odd number of CMOS inverters; wherein, the bias voltage is applied to the gate terminal of the flow control MOS tube to make it work in the sub-threshold region, thereby controlling the flow The current passing through one of the CMOS inverters makes the output frequency of the voltage-controlled oscillator reflect the threshold voltage of the current-controlled MOS transistor. The test system is formed based on the VCO. The random fluctuation value of the threshold voltage between different MOS tubes in the chip is tested by the testing method of the present invention. The VCO circuit of the present invention is simple and easy to implement digitally. Moreover, the VCO-based test system can obtain random fluctuation values of the threshold voltage with high sensitivity when the test process fluctuates, and the test accuracy is good.

Description

Voltage-controlled oscillator, test system for detecting process fluctuations and test method thereof

technical field

The invention belongs to the technical field of microelectronics and relates to the detection of chip process fluctuations, in particular to a voltage-controlled oscillator (Voltage Control Oscillator, VCO)-based test system and a test method for detecting process fluctuations. the

Background technique

With the continuous development of microelectronics manufacturing technology, the feature size of the device is getting smaller and smaller, and the size of the process generation is also getting smaller and smaller. Despite the continuous development of chip manufacturing technology, the problem of random process fluctuations is inevitable, and even its impact on chip performance cannot be ignored.

Generally, process fluctuations are caused by slight process errors between the same batch or between different batches, which will also cause slight changes in the structural parameters of the device, for example, MOS (Metal Oxide Semiconductor, metal oxide Material-semiconductor) channel length, channel doping concentration, etc. For MOS tubes, changes in these structural parameters will be reflected in changes in the threshold voltage (V _TH ) of the MOS tubes. Therefore, the process fluctuation of the chip array is usually reflected by measuring the random fluctuation value of the threshold voltage in the chip array MOS transistor. This is a method commonly used in the industry to detect process fluctuations. This method can be used to detect process fluctuations of the same chip, process fluctuations of the same batch of chips, or random process fluctuation characteristics of different batches of chips.

Intel and Purdue University presented a paper entitled "Accurate Characterization of Random Process Variations Using a Robust Low-Voltage High-Sensitivity Sensor Featuring Replica-Bias Circuit" at the ISSCC International Academic Conference in 2010 (ISSCC 2010 / SESSION 9 / DIGITAL CIRCUITS & SENSORS / 9.7) discloses a technical solution for testing the random fluctuation value of the threshold voltage. In this technical solution, the sub-threshold current signal of the MOS tube under test (that is, DUT, Device Under Test, device under test) is converted into a voltage signal output. Since there is a relatively uniform functional relationship between the sub-threshold current and the threshold voltage, therefore , under the condition that the bias voltage of the gate terminal of the MOS transistor under test is constant, the output voltage signal strongly depends on the threshold voltage V _TH of the tube under test. Usually, one of the MOS transistor arrays of the tube under test (for example, it is manufactured by the same batch process) is first selected as the calibration unit, and a certain range of calibration voltage V _CALIB is biased on the gate terminal of the calibration unit, And scan in this range to measure the output voltage V _OUT , and obtain the functional relationship curve between the output voltage V _OUT and the calibration voltage V _CALIB (V _OUT =f(V _CALIB )). Further, for any other MOS tube under test, bias the voltage V _DD lower than the threshold voltage on its gate terminal and measure its output voltage V _OUT at the same time, and obtain the V _OUT of the MOS tube under test according to the above function relationship curve Corresponding to the calibration voltage V _CALIB of the calibration unit, namely f ^-1 (V _OUT ), therefore, the random fluctuation value of the threshold voltage between the MOS tube under test and the calibration unit △V _TH = f ^-1 (V _OUT )— V _DD . ΔV _TH also reflects the process fluctuation between the calibration unit and the MOS tube under test. Likewise, the process fluctuation characteristics of the MOS transistor array can be reflected by measuring each MOS transistor.

However, the method proposed by Intel etc. has the following disadvantages:

(1) Since the output voltage V _OUT is generally 0-0.3V, the input voltage is easily disturbed and the measurement of V _OUT is inaccurate, so △V _TH is difficult to accurately reflect the characteristics of process fluctuations;

(2) At the same time, it is necessary to consider the influence of process corner (process conner) fluctuations on the test, and another circuit needs to be designed for process corner compensation in the test circuit;

(3) The output voltage V _OUT is an analog signal, and the output of the analog signal requires a buffer (buffer), and the introduced buffer will generate errors, which may easily lead to untrue V _OUT . At the same time, the circuit for this test is an analog circuit as a whole, and it is difficult to guarantee its normal operation after it is prepared and formed in the early process.

In view of this, it is necessary to propose a new method or circuit to accurately measure the random fluctuation value ΔV _TH of the threshold voltage to accurately reflect the characteristics of process fluctuations.

Contents of the invention

The technical problem to be solved by the present invention is to accurately measure the random fluctuation value ΔV _TH of the threshold voltage between DUTs to accurately reflect the characteristics of process fluctuations.

In order to solve the above technical problems, according to one aspect of the present invention, a voltage controlled oscillator is provided. The voltage-controlled oscillator includes a ring oscillator and a current-controlled MOS transistor, and the ring oscillator includes a plurality of CMOS inverters, wherein the voltage is biased at the gate terminal of the current-controlled MOS transistor to make it work in a sub-threshold region and further controlling the current flowing through one of the CMOS inverters, so that the output frequency of the voltage-controlled oscillator reflects the threshold voltage of the current-controlled MOS transistor.

Preferably, the ring oscillator includes three or more odd-numbered CMOS inverters.

Specifically, the output terminal of each CMOS inverter is connected to the input terminal of another CMOS inverter.

According to an embodiment of the voltage-controlled oscillator provided by the present invention, the fluidic MOS transistor is a PMOS transistor and/or an NMOS transistor.

Specifically, the functional relationship between the output frequency of the voltage-controlled oscillator and the sub-threshold current of the fluidic MOS tube operating in the sub-threshold region:

F_out=I _sub /Q

Wherein, F_out is the output frequency of the voltage-controlled oscillator, I _sub is the subthreshold current of the flow-controlled MOS transistor, and Q is the total charge stored in the parasitic capacitance of the frequency output terminal.

Specifically, the functional relationship between the output frequency of the voltage-controlled oscillator and the threshold voltage of the flow-controlled MOS transistor and the bias voltage at the gate terminal:

F_out=F（V _CC ︱ V _TH ）

Wherein, F_out is the output frequency of the voltage-controlled oscillator, V _TH is the threshold voltage of the flow control MOS transistor, and V _CC is the gate terminal bias voltage of the flow control MOS transistor.

Specifically, when the threshold voltage of the flow control MOS transistor is constant, the relational formula F_out=F(V _CC ︱ V _TH ) scans and changes the gate bias voltage to obtain the output frequency and the gate bias voltage The functional relation of :

F_out=f(V _CC )

Wherein, F_out is the output frequency of the voltage-controlled oscillator, V _TH is the threshold voltage of the flow control MOS transistor, and V _CC is the gate terminal bias voltage of the flow control MOS transistor.

Preferably, the source/drain of the flow control MOS transistor is electrically connected to the source/drain of a PMOS of one of the CMOS inverters.

According to another aspect of the present invention, there is provided a test system for detecting process fluctuations, which detects the process fluctuations of the chip by testing the random fluctuation values of the threshold voltages between different MOS transistors in the chip, the test system It includes one of the voltage-controlled oscillators mentioned above, wherein any of the MOS transistors in the chip is used as a flow-controlled MOS transistor of the voltage-controlled oscillator.

According to an embodiment of the test system provided by the present invention, wherein the test system further includes:

A switch array for gating the MOS transistors in the chip;

an address decoder for decoding an input address and outputting it to the switch array; and

divider.

Preferably, the different MOS transistors in the chip include a calibration MOS transistor and a MOS transistor used as a device under test. The calibration MOS transistor is randomly selected from multiple MOS transistors in the chip.

Preferably, different MOS transistors in the chip are manufactured and formed simultaneously under the same set process conditions.

According to still another aspect of the present invention, a kind of test method of above-mentioned test system is provided, is used for testing the random fluctuation value of the threshold voltage between different MOS transistors in the test chip, and it comprises the following steps:

(1) Select the calibration MOS tube in the chip to form the voltage-controlled oscillator as mentioned above;

(2) Scan and input the gate bias voltage of the calibrated MOS transistor to obtain the functional relationship between the output frequency F_out of the voltage-controlled oscillator corresponding to the calibrated MOS transistor and its gate bias voltage V _calib : F_out =f (V _calib );

(3) Selecting the Nth MOS transistor used as the device under test in the chip to form a voltage-controlled oscillator as described above;

(4) The gate terminal of the Nth MOS transistor is biased with a voltage V _CCN to make the MOS transistor work in a sub-threshold region;

(5) According to the output frequency F_outN of the voltage-controlled oscillator corresponding to the Nth MOS transistor, the inverse function V _calib =f ^-1 (F_out) of the functional relationship F_out = f (V _calib ) is used to calculate V _calibN , wherein, V _calibN represents the required bias voltage of the gate terminal of the calibration MOS transistor when the output frequency of the voltage-controlled oscillator corresponding to the calibration MOS transistor is F_outN.

(6) The random fluctuation of the threshold voltage between the Nth MOS transistor and the calibration MOS transistor is obtained by the difference between V _calibN and the biased voltage V _CCN at the gate terminal of the Nth MOS transistor Value ΔV _THN .

Wherein, N is an integer greater than or equal to 1.

Specifically, when N changes, the steps (3) to (6) are repeated.

Preferably, each time the step (4) is repeated, the gate terminal of each MOS transistor is set to be the same by the bias voltage V _CCN .

Preferably, the calibration MOS transistors are randomly determined among the plurality of MOS transistors in the chip.

The technical effect of the invention is that the VCO circuit provided by the invention is simple, the output frequency information can accurately reflect the threshold voltage information of each flow control MOS tube, and it is easy to implement digitally. Moreover, when the test system using the VCO is used to test process fluctuations, a highly sensitive threshold voltage random fluctuation value can be obtained, and the test accuracy is good.

Description of drawings

The above and other objects and advantages of the present invention will become more fully apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein the same or similar elements are denoted by the same reference numerals.

FIG. 1 is a schematic diagram of a circuit structure of a VCO provided according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of a circuit structure of a VCO provided according to yet another embodiment of the present invention.

FIG. 3 is a schematic diagram of a circuit structure of a VCO provided according to yet another embodiment of the present invention.

Fig. 4 is a block diagram of a test system for detecting process fluctuations according to an embodiment of the present invention.

FIG. 5 is a specific circuit schematic diagram of the VCO in the test system shown in FIG. 4 .

Fig. 6 is a schematic diagram of a test method when the test system of the present invention is used to detect process fluctuations.

Detailed ways

The following introduces some of the possible embodiments of the present invention, which are intended to provide a basic understanding of the present invention, but are not intended to identify key or decisive elements of the present invention or limit the scope of protection. It is easy to understand that, according to the technical solution of the present invention, those skilled in the art may propose other alternative implementation manners without changing the essence and spirit of the present invention. Therefore, the following specific embodiments and drawings are only exemplary descriptions of the technical solution of the present invention, and should not be regarded as the entirety of the present invention or as a limitation or restriction on the technical solution of the present invention.

In the present invention, a Voltage Control Oscillator (Voltage Control Oscillator, VCO) is an oscillator whose output frequency (F_out-) and input voltage (V, ie the control voltage) function, that is, there is F_out-=f( V) functional relationship.

FIG. 1 is a schematic diagram of a circuit structure of a VCO provided according to an embodiment of the present invention. The VCO of this embodiment can be specifically used to measure the random fluctuation value ΔV _TH of the threshold voltage between different MOS transistors to detect the characteristic of its process fluctuation. As shown in FIG. 1 , the VCO is a ring oscillator (Ring Oscillator) that adjusts the oscillator frequency based on transmission delay. The VCO includes a ring oscillator part and a flow control MOS transistor 312 (M0). The ring oscillator part is implemented in this embodiment by connecting an odd number (greater than or equal to 3) inverters in series to form a loop. Specifically, the output terminal of each inverter in the 4 inverters 341 and 1 CMOS inverter 342 is connected to the input terminal of another inverter, and connected in series end to end in order to form a loop; wherein the CMOS inverter The source or drain of one of the MOS transistors (M1) in the CMOS inverter 342 is connected in series to the source or drain of the flow control MOS transistor 312, and the source or drain of the other MOS transistor (M2) in the CMOS inverter 342 The drain input voltage V _DD , therefore, the gate bias voltage V _CC of the current control MOS transistor 312 makes the current control MOS transistor work in the sub-threshold region, and the current flowing through the CMOS inverter 342 is controlled by V _CC . Generally, the four inverters 341 can also be the same CMOS inverters as 342, but in this embodiment, the CMOS inverter 342 is selected as a series connection with the flow control MOS transistor 312 (input voltage V _DD direction) In other embodiments, the source or drain of the flow control MOS transistor 312 can also be connected in series with the source or drain of any one PMOS transistor in the other four inverters 341 .

The output frequency F_out of the VCO is determined by the total propagation delay of the inverters connected in series. And when the voltage V _CC input to the voltage control terminal (ie gate terminal) of the current control MOS transistor 312 is lower than the threshold voltage of the MOS transistor 312 , the current flowing through it is a sub-threshold current. Since the sub-threshold current is usually relatively small, for the inverter 342 connected to the flow control MOS transistor 312, its transmission delay mainly depends on the flow control MOS transistor 312 (the voltage V _DD is sequentially changed from M2, M1 to M0 of the inverter 342 transmission). Therefore, the transmission delay of the CMOS inverter 342 is much longer than the transmission delay of other inverters 341, and the output frequency F_out basically depends on the transmission delay of the CMOS inverter 342, that is, the output frequency F_out can basically reflect the flow The sub-threshold current information of the control MOS transistor 312 is used to further reflect the threshold voltage information of the flow control MOS transistor 312.

Therefore, when the bias voltage V _CC at the gate terminal of the MOS transistor 312 is lower than the threshold voltage for turning on the MOS transistor 312 , the MOS transistor 312 will work _in the sub-threshold region. The output frequency F_out mainly depends on the magnitude of V _CC itself and the threshold voltage V _TH of the MOS transistor 312, that is, mainly depends on the difference between the threshold voltage V _TH and V _CC .

Taking the VCO of the embodiment shown in FIG. 1 as an example, V _CC is biased so that the flow control MOS transistor 312 works in the subthreshold region. At this time, the output frequency F_out is closely related to the subthreshold current I _sub of the flow control MOS transistor 312. The following relationship can be obtained:

F_out=I _sub /Q (1)

Where Q is the total charge stored in the parasitic capacitance of the frequency output terminal, and I _sub is the subthreshold current of the flow control MOS transistor 312 .

Further, according to the calculation formula of the sub-threshold current of the MOS transistor 312, it can be known that I _sub is closely related to the threshold voltage V _TH of the MOS transistor 312. Therefore, the relational expression can be further obtained from the relational expression (1):

F_out=F(V _CC ︱ V _TH ) (2)

Relational formula (2) represents the functional relationship F between the output frequency and the variables V _CC and V _TH . For this embodiment, the current control MOS transistor 312 is an NMOS transistor, and V _TH is greater than 0. Therefore, V _CC can be biased between 0 and V _TH , and F_out mainly depends on the difference between the threshold voltage V _TH and V _CC .

In the relationship (2), if the input control voltage V _CC changes (making the MOS transistor 312 work in the sub-threshold region), for example, scanning the input V _CC within a certain range, different outputs can be obtained from The frequency F_out, thus, V _CC and F_out can form a functional relationship curve, that is, F_out=f(V _CC ) (that is, the functional relationship evolved when V _TH is a constant in the relationship (2)). At this time, the fluidic MOS tube 312 can be used as a calibration MOS tube, and in this embodiment, the calibration MOS tube can be randomly selected.

When the flow control MOS tube 312 is represented as a different MOS tube, the threshold voltage of different MOS tubes manufactured in the same batch will fluctuate due to process fluctuation factors, so the threshold voltage of each MOS tube is not absolutely equal . When the control voltage V _CC input on different MOS tubes remains unchanged, F_out may change due to random fluctuations in its threshold voltage (the difference between V _TH and V _CC also changes at this time) (according to the relationship ( 2)).

In summary, it can be seen that the output frequency F_out of the VCO of the present invention can effectively reflect the threshold voltage V _TH and the gate voltage V _CC of the flow control MOS transistor 312, and can accurately reflect the same frequency when testing different flow control MOS transistors. The random fluctuation value △V _TH of the threshold voltage between flow control MOS tubes can accurately reflect the characteristics of process fluctuations. The specific test method will be described in detail in the following steps. Moreover, the output frequency F_out is easy to implement digitally, and the output signal is accurate.

It should be noted that the specific form of the ring oscillator is not limited by the specific embodiment shown in FIG. 1 , for example, it may also be formed by series connection of an even number of inverters connected in reverse at a certain stage. In addition, in this embodiment, the number of inverters 341 may be an even number greater than or equal to 2, for example, it may be 16.

In the embodiment shown in FIG. 1 , the flow control MOS transistor 312 is an NMOS transistor. Likewise, the ring oscillator in the VCO of the present invention can also be connected with PMOS, or can be connected with PMOS and NMOS simultaneously.

FIG. 2 is a schematic diagram of a circuit structure of a VCO provided according to another embodiment of the present invention. In this embodiment, the ring oscillator in the VCO is connected to the PMOS, which is used to measure the random fluctuation value of the threshold voltage of the PMOS transistor. Compared with the VCO of the embodiment shown in FIG. 1 , the only difference is that the flow control MOS transistor 312 of NMOS is replaced by the flow control MOS transistor 313 of PMOS. The basic working principle is similar to that of the VCO of the embodiment shown in FIG. 1 . No more details here.

FIG. 3 is a schematic diagram of a circuit structure of a VCO provided according to yet another embodiment of the present invention. In this embodiment, the ring oscillator in the VCO is connected to the PMOS and the NMOS at the same time, and it can be used to measure the random fluctuation value of the threshold voltage of the PMOS transistor, and can also be used to measure the random fluctuation value of the threshold voltage of the NMOS transistor. Compared with the VCO of the embodiment shown in FIG. 1 , the only difference is that the flow control MOS transistor 313 of the PMOS is added, and its basic working principle is similar to that of the VCO of the embodiment shown in FIG. 1 , which will not be repeated here.

FIG. 4 is a schematic diagram of a module structure of a test system for detecting process fluctuations provided according to an embodiment of the present invention. As mentioned above, the VCO provided by the present invention can be used to detect process fluctuation characteristics. The testing system of the present invention is based on the VCO formation of the present invention. In this embodiment, the test system 300 is schematically illustrated based on the VCO shown in FIG. 1 .

Referring to FIG. 4 , the test system 300 is used to detect the process fluctuation of the chip 310 , which detects the process fluctuation of the chip 310 by testing the random fluctuation value of the threshold voltage between different MOS transistors in the chip 310 . The chip 310 includes a calibration MOS transistor 311 used as a calibration unit, and a DUT array 312 used as a tested MOS transistor (ie, a device under test). Preferably, the test system 300 further includes a switch array 320 , an address decoder 330 , a ring oscillator (RO) 340 , and a frequency divider 350 . A switch array 320 is arranged in series between the ring oscillator (RO) 340 and the chip 310 under test. Specifically, each MOS transistor of the chip 310 corresponds to a switching device (such as a MOS transistor) in the switch array 320, so that the The switch array 320, at least one MOS transistor in the selection chip 310 and one CMOS inverter in the RO 340 are connected in series to form the VCO shown in FIG. 1 . The address decoder 330 receives the address signal from the outside, and outputs the decoded signal to the switch array 320, and the switch array 320 can control the switching device in it to be turned on or off according to the input signal, so as to realize the gating of the MOS tube under test . Therefore, one or more MOS transistors in the chip 310 can be specifically selected for testing. Preferably, the output frequency of the RO 340 is output through the frequency divider 350, and the frequency divider 350 has the function of dividing the high-frequency oscillation signal (the output signal of the RO 340) into a medium-low frequency oscillation signal for testing by a certain multiple.

FIG. 5 is a specific schematic circuit diagram of the VCO in the test system shown in FIG. 4 . As shown in FIG. 5 , through the decoded address, a certain MOS transistor is selected in the switch array 320 , so that one of the MOS transistors in the chip 310 is selected as a flow control MOS transistor, and forms a VCO together with the RO 340 .

It should be noted that the address decoder 330 , the switch array 320 , the RO 340 , the frequency divider 350 , etc. in the test system 300 can be integrated with the chip 310 and realized in the form of the same chip.

Fig. 6 shows the test method when the test system of the present invention is used to detect process fluctuations. The testing method of this embodiment will be specifically described below with reference to FIG. 4 , FIG. 5 and FIG. 6 .

In step S510, firstly, the switch device corresponding to the calibration MOS transistor is selected in the switch array.

In this step, the calibration MOS tubes and the tested MOS tubes are manufactured in the same batch, that is, the calibration MOS tubes and the tested MOS tubes are manufactured simultaneously under the same set process conditions. Therefore, preferably, one of the MOS transistors in the chip 310 can be randomly selected as the calibration MOS transistor 311 in a random manner, and it is assumed that the actual threshold voltage of the calibration MOS transistor 311 is V _TH0 . The switching device corresponding to the calibration MOS transistor in the gate switch array 320 is controlled by the input address, so that the calibration MOS transistor 311 and the RO 340 can form a VCO as shown in FIG. 1 .

Step S520 , scanning and inputting the gate bias voltage V _calib of the calibrated MOS transistor, and obtaining the functional relationship F_out =f(V _calib ) between the output frequency F_out of the VCO corresponding to the calibrated MOS transistor and V _calib .

In this step, preferably, the gate bias voltage V _calib of the calibration MOS transistor is smaller than its threshold voltage V _TH0 , so that the calibration MOS transistor works in a sub-threshold region. From this, the relationship curve between F_out and V _calib can be obtained.

In step S530, the switch device corresponding to the Nth MOS transistor under test is selected in the switch array.

In this step, specifically, if there are M MOS transistors in the DUT array, it is necessary to measure random fluctuation values of threshold voltages of all M MOS transistors relative to the calibration MOS unit. Taking the initial value of N as 1 as an example, the switching device corresponding to the Nth MOS transistor to be tested in the strobe switch array 320 is controlled through the input address, so that the Nth MOS transistor to be tested and RO340 can be formed as shown in the figure 1 shows the VCO. Assume that the actual threshold voltage of the Nth MOS transistor under test is V _CCN .

In step S540, the gate terminal of the MOS transistor under test is biased with a voltage V _CCN so that the MOS transistor under test operates in a sub-threshold region, and an output frequency F_outN of the VCO corresponding to the MOS transistor under test is obtained. It can be known from the above working principle of the VCO that F_outN mainly depends on the difference between the threshold voltage V _THN and V _CCN . In this embodiment, for each MOS transistor under test (as N varies), preferably, the bias voltage V _CCN at its gate terminal is generally set to be the same.

Step S550 , according to the output frequency F_outN, V _calibN is obtained by using the inverse function V _calib =f ⁻¹ (F_out) of the functional relationship F_out =f(V _calib ). Wherein, V _calibN reflects the required bias voltage value of the gate terminal of the VCO corresponding to the calibration MOS transistor when the output frequency is F_outN.

Step S560 , calculating the difference between V _calibN and V _CCN , the difference reflects the threshold voltage random fluctuation value ΔV _THN between the Nth MOS transistor under test and the calibration MOS transistor.

In this step, the difference between V _calibN and V _CCN is further caused by the threshold voltage difference caused by the process fluctuation between the passive MOS transistor and the calibration MOS transistor. △V _THN can be calculated according to the following formula:

△V _THN =V _THN —V _TH0 =V _CCN —V _calibN (3)

Therefore, the random fluctuation value of the threshold voltage between the target MOS tube and the calibration MOS tube can be accurately obtained, thereby accurately reflecting the process fluctuation characteristics between the target MOS tube and the calibration MOS tube.

Step S570, N=N+1, preparing for further measurement of the next MOS transistor.

Step S580, judge whether (N+1) is less than or equal to M, if judged as "yes", enter step S530, if judged as "no", it means that all the MOS transistors under test in the DUT array are tested.

So far, the random fluctuation value of the threshold voltage of each of the M MOS transistors under test relative to the calibration MOS transistors in the DUT array can be obtained. According to statistical analysis, the process fluctuation characteristics of the chip 310 can be obtained. It should be noted that, indirectly, through the △V _THN corresponding to multiple MOS transistors under test, the random fluctuation value of the threshold voltage between any two MOS transistors under test can be obtained, for example, through the obtained first measured MOS tube The random fluctuation value of the threshold voltage between the measured MOS tube and the calibration MOS tube △V _TH1 , the random fluctuation value of the threshold voltage between the second measured MOS tube and the calibration MOS tube △V _TH2 , (△V _TH1 — △ V _TH2 ) that indirectly obtains the random fluctuation value of the threshold voltage between the first MOS tube under test and the second MOS tube under test.

The above examples mainly illustrate the VCO of the present invention, the testing system and testing method based on the VCO. Although only some of the embodiments of the present invention have been described, those skilled in the art should appreciate that the present invention can be implemented in many other forms without departing from the spirit and scope thereof. The examples and embodiments shown are therefore to be regarded as illustrative and not restrictive, and the invention may cover various modifications without departing from the spirit and scope of the invention as defined in the appended claims with replace.

Claims (12)

1. a voltage controlled oscillator, it is characterized in that comprising ring oscillator and Flow Control metal-oxide-semiconductor, described ring oscillator comprises a plurality of CMOS inverters, wherein, at the grid end bias voltage of described Flow Control metal-oxide-semiconductor so that its electric current that works in sub-threshold region and then control the described CMOS inverter of flowing through, so that the output frequency of described voltage controlled oscillator reflects the threshold voltage of described Flow Control metal-oxide-semiconductor;

The output frequency of described voltage controlled oscillator with the functional relation of subthreshold current that works in the described Flow Control metal-oxide-semiconductor of sub-threshold region is:

F_out=I _sub/Q

The functional relation of the threshold voltage of the output frequency of described voltage controlled oscillator and described Flow Control metal-oxide-semiconductor and grid end bias voltage is:

F_out=F（V _CC ︱V _TH）

In threshold voltage one timing of described Flow Control metal-oxide-semiconductor, by relational expression F_out=F(V _cC ︱v _tH), grid end bias voltage described in scan variations, the functional relation that obtains output frequency and grid end bias voltage is:

F_out=f（V _CC）

Wherein, the output frequency that F_out is described voltage controlled oscillator, I _subfor the subthreshold current of described Flow Control metal-oxide-semiconductor, Q is the total charge dosage that frequency output terminal parasitic capacitance is stored; V _cCgrid end bias voltage for described Flow Control metal-oxide-semiconductor; V _tHthreshold voltage for described Flow Control metal-oxide-semiconductor.

2. voltage controlled oscillator as claimed in claim 1, is characterized in that, described ring oscillator comprises three or three above odd number CMOS inverters.

3. voltage controlled oscillator as claimed in claim 1 or 2, is characterized in that, described in each, CMOS inverter output is connected to the input of CMOS inverter described in another.

4. voltage controlled oscillator as claimed in claim 3, is characterized in that, described Flow Control metal-oxide-semiconductor is PMOS pipe and/or NMOS pipe.

5. voltage controlled oscillator as claimed in claim 1, is characterized in that, source/drain terminal correspondence of described Flow Control metal-oxide-semiconductor is electrically connected at the source/drain terminal of the PMOS of CMOS inverter described in one of them.

6. the test macro for detection of technological fluctuation of the voltage controlled oscillator based on as described in any one in claim 1-5, its random fluctuation value by the threshold voltage between different metal-oxide-semiconductors in test chip detects the technological fluctuation of described chip, it is characterized in that, described test macro comprises the voltage controlled oscillator as described in any one in claim 1-5, wherein, the arbitrary metal-oxide-semiconductor in described chip is as the Flow Control metal-oxide-semiconductor of described voltage controlled oscillator.

7. test macro as claimed in claim 6, is characterized in that, described test macro also comprises:

Switch arrays, for the metal-oxide-semiconductor of chip described in gating;

Address decoder, for decoding to Input Address and exporting described switch arrays to; And

Frequency divider.

8. the test macro as described in claim 6 or 7, is characterized in that, in described chip, different metal-oxide-semiconductors comprise the metal-oxide-semiconductor of calibrating metal-oxide-semiconductor and being used as measured device;

In a plurality of metal-oxide-semiconductors of described calibration metal-oxide-semiconductor in described chip, select at random.

9. a method of testing for the test macro based on as described in one of claim 6-8, the random fluctuation value for the threshold voltage between the different metal-oxide-semiconductors of test chip, is characterized in that, comprises the following steps:

(1) select calibration metal-oxide-semiconductor in described chip to form the voltage controlled oscillator as described in one of claim 1-5;

(2) the grid end bias voltage of described calibration metal-oxide-semiconductor is inputted in scanning, obtains output frequency F_out and its grid end bias voltage V of the voltage controlled oscillator that described calibration metal-oxide-semiconductor is corresponding _calibfunctional relation: F_out=f(V _calib);

(3) select N the metal-oxide-semiconductor as measured device in described chip, to form the voltage controlled oscillator as described in one of claim 1-8;

(4) the grid end of described N metal-oxide-semiconductor is applied to bias voltage V _cCN, make this metal-oxide-semiconductor work in sub-threshold region;

(5) according to the output frequency F_outN of voltage controlled oscillator corresponding to described N metal-oxide-semiconductor, with described functional relation F_out=f(V _calib) inverse function V _calib=f ^-1(F_out) obtain V _calibN, wherein, V _calibNwhen the output frequency that represents the voltage controlled oscillator that described calibration metal-oxide-semiconductor is corresponding is F_outN, the voltage of the required biasing of grid end of described calibration metal-oxide-semiconductor;

(6) pass through V _calibNthe bias voltage V applying with described N metal-oxide-semiconductor _cCNbetween difference, draw the random fluctuation value △ V of the threshold voltage between described N metal-oxide-semiconductor and described calibration metal-oxide-semiconductor _tHN;

Wherein, N is more than or equal to 1 integer.

10. method of testing as claimed in claim 9, is characterized in that, when N changes, repeating said steps (3) is to step (6).

11. method of testings as claimed in claim 9, is characterized in that, while repeating described step (4), by the grid end bias voltage V of each metal-oxide-semiconductor at every turn _cCNbe set to identical.

12. method of testings as described in one of claim 9-11, is characterized in that, described calibration metal-oxide-semiconductor is by determining at random in a plurality of metal-oxide-semiconductors in described chip.