CN102655152B - Storage device, its manufacturing method and operating method - Google Patents

Abstract

The present invention discloses a storage device, a manufacturing method and an operating method thereof. The storage device includes a substrate, a stacking structure, a channel element, a dielectric element, a source element and a bit line. The stacking structure is arranged on the substrate. Each of the stacking structures includes a series selection line, a word line, a ground selection line and an insulating line. The series selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is arranged between the stacking structures. The dielectric element is arranged between the channel element and the stacking structure. The source element is arranged between the upper surface of the substrate and the lower surface of the channel element. The bit line is arranged on the upper surface of the channel element.

Description

Storage device, its manufacturing method and operating method

technical field

The present invention relates to a storage device, its manufacturing method and operating method, in particular to a three-dimensional vertical gate storage device, its manufacturing method and its operating method.

Background technique

Storage devices are used in many products, such as storage elements in MP3 players, digital cameras, computer files, and so on. With the increase of applications, the demand for storage devices also tends to be smaller in size and larger in storage capacity. To meet this demand, it is necessary to manufacture memory devices with high device density.

One way designers have developed to increase the density of memory devices is to use three-dimensional stacked memory devices, thereby achieving higher memory capacities while reducing the cost per bit. However, at present, the size reduction limit of the memory unit of this storage device is still greater than 50nm, and it is difficult to make a major breakthrough. The performance of the storage device may also be limited by the material used for the components.

Contents of the invention

The invention relates to a storage device, its manufacturing method and operating method. Memory devices have very small scaling and good performance.

According to an aspect of the present invention, a storage device is provided. The memory device includes a substrate, a stack structure, a channel element, a dielectric element, a source element and a bit line. The stack structure is configured on the base. Each stack structure includes a string selection line, a word line, a ground selection line and an insulation line. The string selection line, the word line and the ground selection line are separated from each other by insulating lines. The channel elements are disposed between the stacked structures. The dielectric element is disposed between the channel element and the stack structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is arranged on the upper surface of the channel element.

According to another aspect of the present invention, a method for manufacturing a storage device is provided. The method includes the following steps. A stack structure is configured on the base. Each stack structure includes a string selection line, a word line, a ground selection line and an insulation line. The string selection line, the word line and the ground selection line are separated from each other by insulating lines. Channel elements are disposed between the stacked structures. A dielectric element is disposed between the channel element and the stack structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. Bit lines are disposed on the upper surface of the channel element.

According to still another aspect of the present invention, a method for operating a storage device is provided. The method includes the following steps. A storage device is provided. The memory device includes a substrate, a stack structure, a channel element, a dielectric element, a source element and a bit line. The stack structure is configured on the base. Each stack structure includes a string selection line, a word line, a ground selection line and an insulation line. The string selection line, the word line and the ground selection line are separated from each other by insulating lines. The channel elements include channel lines. The channel lines are disposed between the stacked structures and separated from each other. The dielectric element is disposed between the channel line and the stack structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel line. The bit line is disposed on the upper surface of the channel line. At least one of the channel lines is selected to be turned on.

In order to make the above-mentioned purposes, features, and advantages of the present invention more obvious and easy to understand, the preferred embodiments are specifically cited below, together with the accompanying drawings, and are described in detail as follows:

Description of drawings

1 to 13 illustrate manufacturing embodiments of a memory device.

14 to 19 illustrate another fabrication embodiment of a memory device.

FIG. 20 is a perspective view of a storage device in an embodiment.

FIG. 21 is a perspective view of a storage device in an embodiment.

FIG. 22 is a perspective view of a storage device in an embodiment.

FIG. 23 is a perspective view of a storage device in an embodiment.

Figure 24 shows the waveforms used for decoding in some embodiments.

Fig. 25 shows the configuration of the storage device in the embodiment.

Explanation of reference signs

2, 102, 237: Base

4, 154, 238, 516, 518: source components

6: sacrificial layer

8, 104: insulation layer

10, 12, 14: Patterned structures

16, 18: First opening

20, 22, 140: Trench elements

24, 26, 28: Second opening

29A, 29B: Support structure

30, 30B, 54, 118, 217: insulated wire

32: Slit

34, 120: Dielectric components

36, 128, 130: conductive material

40, 42, 44, 46, 108, 110, 208, 210, 212, 214, 216, 308, 310, 312, 404, 406, 408, 410, 412: stacked structure

48, 112, 224, 226, 228, 230, 231, 320, 322, 324, 416, 422, 418, 420, 424, 504: serial selection line

50, 114, 218, 220, 314, 316, 426, 428, 430, 432, 506, 508: word line

52, 116, 222, 318, 414, 510: grounding selection line

56, 58, 60, 62, 142, 144, 146, 148, 219, 221, 223, 232, 234, 236, 336, 338, 444, 446, 448, 512, 514: channel line

64, 66, 134, 136, 138, 240, 502: bit lines

68, 156: upper surface of substrate

70, 72, 158: Lower surface of channel element

74, 76, 160: upper surface of channel element

106: Conductive layer

119: gap

122, 124, 126: dielectric layer

132: mask layer

150, 152: source line

202, 204, 206, 302, 304, 306, 326, 402: contact structure

340, 342, 344, 346, 450, 452: sides of channel lines

T1: Thickness of the serial selection line

T2: Thickness of the ground selection wire

T3: The thickness of the word line

T4, T5: Thickness of insulated wire

W1: Width of the gap

Detailed ways

1 to 13 illustrate manufacturing embodiments of a memory device. Referring to FIG. 1 , a source element 4 is disposed on a substrate 2 . In an embodiment, the source element 4 may include a source layer or a source line. The embodiments shown in FIGS. 1 to 13 are described with the source element 4 as the source layer covering the substrate 2 . The source element 4 may have an N+ conductivity type. In the embodiment, the source element 4 is disposed on the substrate 2 in an insulating manner. For example, the source element 4 and the substrate 2 are separated from each other by a dielectric structure (not shown). Sacrificial layers 6 and insulating layers 8 are alternately stacked on the source element 4 . The sacrificial layers 6 are separated from each other by an insulating layer 8 . The sacrificial layer 6 may include nitride such as silicon nitride. The insulating layer 8 may include oxide such as silicon oxide. The bottommost one of the insulating layers 8 may be a buried oxide layer.

The sacrificial layer 6 and the insulating layer 8 are patterned to form patterned structures 10 , 12 , 14 as shown in FIG. 2 . The first openings 16 , 18 expose the source element 4 . Referring to FIG. 3 , conductive material is disposed in the first openings 16 , 18 to form channel elements 20 , 22 . In the embodiment, the source element 4 is a single crystal material, and the channel elements 20 and 22 are single crystal materials formed by selective epitaxial growth on the source element 4 . In an embodiment, the source element 4 and the channel elements 20, 22 are made of single crystal silicon. A cleaning step may also be performed before the epitaxy to remove the native oxide layer on the source element 4 to form channel elements 20 , 22 with good quality.

A patterning process is performed on the patterned structures 10 , 12 , 14 to form second openings 24 , 26 , 28 and insulating lines 30 as shown in FIG. 4 . The sacrificial layer 6 exposed by the second openings 24 , 26 , 28 is removed to form a slit 32 exposing the channel elements 20 , 22 as shown in FIG. 5 . In an embodiment, hot phosphoric acid (H ₃ PO ₄ ) can be used to remove the sacrificial layer 6 (such as silicon nitride). The etching process used has high selectivity, so the source element 4 (such as monocrystalline silicon) and the insulating line 30 (such as oxide) will not be damaged. In an embodiment, the oxide-insulated line 30 shown in FIG. 5 is adjacent to the sidewall of the support structure (such as the support structure 29A shown in FIG. 6 such as oxide), so there is sufficient strength to maintain the structure. Referring to FIG. 7 , which illustrates a top view of a memory device in some embodiments, the periodically surrounding oxide support structure 29B helps to support the oxide insulating line 30B.

Referring to FIG. 8 , a dielectric element 34 is formed on the channel elements 20 and 22 exposed by the slit 32 . In an embodiment, for example, the dielectric element 34 may have a multilayer structure, such as an ONO composite layer or an ONONO composite layer or a BE-SONOS composite layer (the structure may refer to US Application No. 11/419,977, Patent No. 7414889 ), or include, for example, an ONO structure formed by interleaved stacking of silicon oxide and silicon nitride. The dielectric element 34 can also be a single material layer, including silicon nitride or silicon oxide such as silicon dioxide, silicon oxynitride. Dielectric element 34 may be formed by vapor deposition, such as chemical vapor deposition. Referring to FIG. 9 , the slot 32 is filled with a conductive material 36 . Furthermore, the electrically conductive material 36 fills the second openings 24 , 26 , 28 . The conductive material 36 may also extend onto the channel elements 20 , 22 .

Portions of the conductive material 36 located in the second openings 24 , 26 , 28 are removed, leaving the conductive material 36 filled in the slots 32 to form stack structures 40 , 42 , 44 , 46 as shown in FIG. 10 . Referring to FIG. 10 , the stack structures 40 , 42 , 44 , 46 respectively include, for example, a string select line (SSL) 48 , a word line (WL) 50 , a ground select line (GSL) 52 and an insulating line 54 . The string select line 48 , the word line 50 and the ground select line 52 are separated from each other by an insulating line 54 . After patterning, the channel element 20 and the channel element 22 respectively include channel lines 56 , 58 and channel lines 60 , 62 as shown in FIG. 11 . Channel lines 56 and 58 are separated from each other. Likewise, the channel lines 60 and 62 are separated from each other, as shown in FIG. 12 , which is a cross-sectional view along line AA of FIG. 11 .

Referring to FIG. 13 , bit lines 64 , 66 are formed on channel lines 56 , 58 , 60 , and 62 . In the memory device shown in FIG. 13 , the string select line 48 , the word line 50 , the ground select line 52 and the bit lines 64 and 66 may comprise semiconductor materials such as polysilicon. The string select line 48, the word line 50, the ground select line 52, and the bit lines 64, 66 may also include a metal such as tungsten to reduce resistance. The source element 4 (in this embodiment, the source layer covering the substrate 2) is disposed under the upper surface 68 of the substrate 2 and the channel elements 20, 22 (including, for example, channel lines 56, 58, 60, 62). between the surfaces 70,72. Bit lines 64, 66 are disposed on upper surfaces 74, 76 of channel elements 20, 22 (including, for example, channel lines 56, 58, 60, 62). In the embodiment, the channel elements 20 , 22 and the source element 4 are made of single crystal silicon, which has very good conductivity and low resistance between them.

14 to 19 illustrate another fabrication embodiment of a memory device. Referring to FIG. 14 , insulating layers 104 and conductive layers 106 are alternately stacked on the substrate 102 . The insulating layer 104 may include an oxide such as silicon oxide. The bottommost one of the insulating layers 104 may be a buried oxide layer. Conductive layer 106 may include a metal or a semiconductor material such as polysilicon. In an embodiment, the conductive layer 106 is formed by doping (for example, P-type impurities to improve work function and suppress gate implantation) after forming the polysilicon layer. Conductive layers 106 are separated from each other by insulating layer 104 . The insulating layer 104 and the conductive layer 106 are patterned to form stacked structures 108 , 110 as shown in FIG. 15 . Referring to FIG. 15 , each of the stack structures 108 and 110 includes, for example, a string selection line 112 , a word line 114 , a ground selection line 116 and an insulating line 118 . The string select line 112 , the word line 114 and the ground select line 116 are separated from each other by an insulating line 118 . There is a gap 119 between the stack structure 108 and the stack structure 110 . In an embodiment, the width W1 of the gap 119 is greater than 60 nm.

Referring to FIG. 16 , a dielectric element 120 is formed on the substrate 102 and the stacked structures 108 and 110 exposed by the gap 119 . For example, the dielectric element 120 has a multi-layer structure, such as an ONO composite layer or an ONONO composite layer or a BE-SONOS composite layer (for the structure, please refer to US Application No. 11/419,977, Patent No. 7414889). In an embodiment, the dielectric element 120 has an ONO structure, wherein the dielectric layer 122 is silicon oxide, the dielectric layer 124 is silicon nitride, and the dielectric layer 126 is silicon oxide. In other embodiments, the dielectric element 120 is a single material layer (not shown), including silicon nitride or silicon oxide such as silicon dioxide, silicon oxynitride.

Referring to FIG. 17 , the gap 119 is filled with a conductive material 128 . The conductive material 128 may extend onto the stacked structures 108 , 110 . In an embodiment, the portion of the conductive material 128 (such as polysilicon) extending to the stacked structures 108 and 110 is doped (such as doped with N-type impurities) to form a doped (such as N+) conductive material 130 . A patterned mask layer 132 is formed on the doped conductive material 130 , and portions of the doped conductive material 130 not covered by the mask layer 132 are removed to form bit lines 134 , 136 , 138 as shown in FIG. 18 . And remove the upper portion of the conductive material 128 not covered by the mask layer 132 to form the channel element 140 as shown in FIG. 18 , which includes channel lines 142 , 144 , 146 , 148 for example. The bottom portion left of the conductive material 128 forms a source element 154 as shown in FIG. 18 , including, for example, source lines 150 , 152 . The mask layer 132 is removed to form the memory device as shown in FIG. 19 .

19, the source element 154 (which includes source lines 150, 152) is disposed between the upper surface 156 of the substrate 102 and the lower surface 158 of the channel element 140 (including channel lines 142, 144, 146, 148). between. The bit lines 134 , 136 , 138 are disposed on the upper surface 160 of the channel element 140 . The source element 154 is separated from the substrate 102 by a dielectric element 120 . The substrate 102 can be used as a bottom gate to reduce the resistance of the source element 154 . For example, the source lines 152 of the source element 154 located on the same side of the stack structure 110 and below the channel lines 144 , 146 , 148 separated from each other extend singly or continuously. For example, the source lines 150 and 152 below the channel lines 142 and 144 on opposite sides of the stack structure 110 are separated from each other. The long sides of the channel lines 142 , 144 , 146 , 148 (extending in the Y direction) are perpendicular to the long sides of the source lines 150 , 152 (extending in the Z direction).

19, in an embodiment, the string selection line 112, the word line 114 and the ground selection line 116 have a first conductivity type (for example, P type); the bit lines 134, 136, 138, source elements 154 (including source Pole lines 150 , 152 ) and channel elements 140 (including, for example, channel lines 142 , 144 , 146 , 148 ) have a second conductivity type (eg, N-type) opposite to the first conductivity type. In an embodiment, the doping concentration of the channel element 140 is less than the doping concentration of the source element 154 . The doping concentration of the channel element 140 may also be less than the doping concentration of the bitlines 134 , 136 , 138 . In some embodiments, the bit lines 134 , 136 , 138 and the channel element 140 have opposite first and second conductivity types respectively, forming a PN diode.

Please refer to FIG. 19 , in an embodiment, the string selection line 112 , the word line 114 , and the ground selection line 116 are all P+ type. The string selection line 112, the word line 114, and the ground selection line 116 can all be N-type. In another embodiment, both the string selection line 112 and the word line 114 are N-type, and the ground selection line 116 is N+ type. In other embodiments, the string selection line 112 is P type, the ground selection line 116 is N+ type, one of the word lines 114 adjacent to the string selection line 112 is N type, and the one adjacent to the ground selection line 116 is P type. .

Please refer to FIG. 19 , in an embodiment, the serial selection line 112 and the ground selection line 116 have a large thickness T1, T2 (that is, the length of the corresponding channel), which is equal to, and usually greater than, the thickness T3 of the word line 114, This helps to obtain excellent switching efficiency, low leakage current and high tunneling capability. In the embodiment, the thickness T1, T2 is , the thickness T3 is . The thickness T4 of the bottommost one of the insulated wires 118 may be , the other thickness T5 can be

Referring to FIG. 19 , the storage device is a three-dimensional vertical gate memory device (3D vertical gate memory device), such as a NAND flash memory or an antifuse memory, and the like. The size of the structure (half pitch) of the memory device in the X direction and the Z direction can be shrunk to less than 30nm, so it has a very high device density.

FIG. 20 is a perspective view of a storage device in an embodiment. FIG. 20 does not illustrate the part where the insulating line 217 is interposed between the channel lines 219, 221, and 223. 220 and is continuous with ground select line 222. Please refer to FIG. 20 , for example, in an embodiment, the string selection lines 224, 226, 228, 230, the word lines 218, 220 and the ground selection line 222 have P+ conductivity; the source element 238 and the bit line 240 have N+ conductivity type; channel lines 219 , 221 , 223 , 232 , 234 , 236 have N conductivity type. The method of operating the memory device includes applying bias voltages to the word lines 218 , 220 and the ground select line 222 of the stack structures 208 , 210 , 212 , 214 , 216 through the shared contact structures 202 , 204 , 206 . For example, word line 218 is biased at _VPGM or V _READ , word line 220 is biased at V _PASS , and ground select line 222 is biased at 0 volts (when writing) or ground (when reading) Select line 222 is biased at V _cc . Decoding the word lines 218, 220 is thus easy. In an embodiment, the string select lines 224, 226, 228, 230 are decoded separately. The selected channel line 232 is turned on by applying a positive bias (+V _cc , eg, +3.3V) to the string select lines 226 , 228 of the stack structures 210 , 212 on opposite sides. To avoid disturbing other unselected adjacent channel lines 234, 236, the tandem select lines 224, 230 of the stack structures 208, 214 on the sides of the unselected channel lines 234, 236 may be negatively biased. voltage (-V _cc , eg -3.3V) to turn off the adjacent string select line transistors. The far side string select line 231 can simply be applied with 0 volts or ground. A positive bias (eg, +V _cc , eg, +5V) can be applied to the substrate 237 as the bottom gate during reading to reduce the resistance of the source element 238 .

FIG. 21 is a perspective view of a storage device in an embodiment. The conductivity type of the memory device element in FIG. 21 is similar to that of the memory device element in FIG. 20 , so details will not be described here. Referring to FIG. 21 , the method for operating the memory device includes applying bias voltages to the word lines 314 , 316 and the ground selection line 318 of the stack structures 308 , 310 , 312 through the common contact structures 302 , 304 , 306 . For example, word line 314 is biased at _VPGM or V _READ , word line 136 is biased at V _PASS , and ground select line 318 is biased at 0 volts (when writing) or ground (when reading) Select line 318 is biased at V _cc . The selected channel line 336 is turned on by applying a positive bias (eg, +3.3V) to the string select lines 320 , 322 of the stack structures 308 , 310 on opposite sides 340 , 342 by the contact structure 326 . String select lines 322 , 324 of stack structures 310 , 312 on opposite sides 344 , 346 of channel line 338 that are not selected to be turned off apply 0 volts or ground. The positive bias for turning on and the zero bias for turning off are respectively applied to, for example, the portion of the single string select line 322 adjacent to the turned-on channel line 336 and the turned-off channel line 338 .

FIG. 22 is a perspective view of a storage device in an embodiment. The conductivity type of the memory device element in FIG. 22 is similar to the conductivity type of the memory device element in FIG. 20 , so details will not be described here. Referring to FIG. 22 , the method for operating the memory device includes applying a bias voltage to the ground selection line 414 of the stack structures 404 , 406 , 408 , 410 , 412 through the common contact structure 402 . In an embodiment, the word lines 426 , 428 , 430 , 432 are divided into a group of word lines 428 , 432 of odd columns and a group of word lines 426 , 430 of even columns, and the combinations of different columns are individually applied voltages. For example, the word lines 428 and 432 of the odd columns are applied with the write voltage _VPGM or the read voltage V _READ , and the word lines 426 and 430 of the even columns are applied with 0V or ground. In an embodiment, the ground select line 414 is positively biased (eg, +3.3V). The selected channel line 446 is turned on by applying a positive bias (eg, +3.3V) to the string select lines 418 , 420 of the stack structures 406 , 408 on opposite sides 450 , 452 . The word line 428 of the stack structure 406 is applied with the write voltage _VPGM or the read voltage V _READ , and the word line 430 of the stack structure 408 is applied with 0V. Therefore only select ONONO structures on side 450 are programmed or read. Therefore, a physically two-bit/cell can be achieved. The string select lines 416 , 422 of the stack structures 404 , 410 on the sides of the unselected channel lines 444 , 448 may be negatively biased (eg, -3.3V). The far side string select line 424 can be applied with 0 volts or ground.

FIG. 23 is a perspective view of a storage device in an embodiment. The conductivity type of the memory device element of FIG. 23 is similar to that of the memory device of FIG. 20 except that the bit line 502 has a P+ conductivity type. The bit line 502 and the channel line 512 (or channel line 514 ) (N conductivity type) form a diode. In an embodiment, the string select line 504 is positively biased (eg, +3.3V). Word line 506 is biased at _VPGM or V _READ , word line 508 is biased at V _PASS , (when writing) ground select line 510 is biased at 0 volts, or (when reading) ground select line 510 is biased A bias voltage V _cc is applied. In an embodiment, the source element 516 below the selected channel line 512 is applied with zero volts or ground during readout. The source element 518 below the channel line 514 that is not selected to be turned off, for example, is floating or positively biased (eg, +V _cc ). Since the diode formed by bit line 502 and channel line 512 (or channel line 514 ) does not allow reverse current flow, unselected source elements 518 cannot be read. Figure 24 shows waveforms suggested for decoding in some embodiments. Please refer to FIG. 24 , during T1, source line self-boosting is performed through GSL and Vcc on the unselected SL (unselected SL). Vch is raised in memory cells (cells) C and D. During T2, bit line bootstrapping is performed via SSL with Vcc on unselected BLs. Vch is raised at memory cell B. Due to the PN diode at BL, the Vch raised by memory cell C is not leaked. During T3, programming memory cell A is initiated. The inversion channel has been formed during T1 and T2, and it is still programmable even if SSL/GSL is turned off. In addition, the memory cell E is disturbed by Vpass, and if Vpass is less than 10V, it will not cause serious impact.

Fig. 25 shows the configuration of the storage device in the embodiment. The bottom diffused source line must be periodically connected to the metal source line to reduce the source resistance. The source lines can be fan-out as suggested layout. Alternatively, the source lines can be divided into even/odd pairs to allow flexible selectivity of the array. The source line contact (contact) can promote the sidewall ONONO self-aligned contact (self-aligned contact; SAC). The diffused bit lines are periodically connected to the metal bit lines to reduce resistance. The word lines of each level can be shared or divided into even/odd arrays and connected to word line decoders. The top SSL gate is connected to the SSL decoder.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (10)

1. a storage device, comprising:

Substrate;

A plurality of stacked structures, are disposed in this substrate, and wherein the plurality of stacked structure respectively comprises tandem selection line, word line, ground connection selection line and insulated wire, and this tandem selects line, this word line and this ground connection to select line separated from each other by this insulated wire;

Channel element, is disposed between the plurality of stacked structure;

Dielectric element, is disposed between this channel element and this stacked structure;

Source elements, is disposed between the upper surface of this substrate and the lower surface of this channel element, and this source elements and this substrate are separated from each other by this dielectric element; And

Bit line, is disposed on the upper surface of this channel element.

2. storage device as claimed in claim 1, wherein this tandem selects line, this word line and this ground connection to select line to have the first conductivity type, this source elements, this channel element and this bit line have the second conductivity type, this first conductivity type is contrary with this second conductivity type, and the doping content of this channel element is less than the doping content of this source elements and this bit line.

3. storage device as claimed in claim 1, wherein this bit line, this tandem select line, this word line and this ground connection to select line to have the first conductivity type, this source elements and this channel element have the second conductivity type, this first conductivity type is contrary with this second conductivity type, and the doping content of this channel element is less than the doping content of this source elements.

4. storage device as claimed in claim 1, wherein this channel element comprises many channel wire, this source elements comprises many source electrode lines,

One that in the plurality of source electrode line, is positioned at this many channel wire below on the same side of this stacked structure is extension continuously,

The plurality of source electrode line that is positioned at these many channel wire belows on this stacked structure relative side is separated from each other.

5. a manufacture method for storage device, comprising:

In substrate, configure a plurality of stacked structures, wherein the plurality of stacked structure respectively comprises tandem selection line, word line, ground connection selection line and insulated wire, and this tandem selects line, this word line and this ground connection to select line separated from each other by this insulated wire;

Configuration channel element is between the plurality of stacked structure;

Configuration dielectric element is between this channel element and this stacked structure;

Configuration source elements between the upper surface of this substrate and the lower surface of this channel element, and this source elements and this substrate to pass through this dielectric element separated from each other; And

Configuration bit line is on the upper surface of this channel element.

6. the manufacture method of storage device as claimed in claim 5, wherein has gap between the plurality of stacked structure, and this source elements comprises source electrode line, and the manufacture method of this storage device comprises:

On this substrate of exposing in this gap and the plurality of stacked structure, form this dielectric element;

With electric conducting material, fill this gap; And

Remove this electric conducting material of part to form this source electrode line and this channel element, wherein this source electrode line and this channel element are disposed in this gap, and this source electrode line and this substrate are separated from each other by this dielectric element.

7. the manufacture method of storage device as claimed in claim 5, wherein this source elements comprises source layer, covers this substrate, the manufacture method of this storage device comprises:

A plurality of sacrifice layers and a plurality of insulating barrier are staggeredly stacked on this source layer;

In the plurality of sacrifice layer being staggeredly stacked and the plurality of insulating barrier, form the first opening;

On this source layer exposing in this first opening, extension forms this channel element;

In the plurality of sacrifice layer being staggeredly stacked and the plurality of insulating barrier, form the second opening;

Remove this sacrifice layer that this second opening exposes to form the slit that exposes this channel element;

On this channel element exposing in this slit, form this dielectric element; And

In this slit, filled conductive material selects line, this word line and this ground connection to select line to form this tandem.

8. a method of operation for storage device, comprising:

Storage device is provided, comprises:

Substrate;

A plurality of stacked structures, are disposed in this substrate, and the plurality of stacked structure respectively comprises tandem selection line, word line, ground connection selection line and insulated wire, and this tandem selects line, this word line and this ground connection to select line separated from each other by this insulated wire;

Channel element, comprises many channel wire, and these many channel wire are disposed between the plurality of stacked structure and are separated from each other;

Dielectric element, is disposed between these many channel wire and the plurality of stacked structure;

Source elements, is disposed between the upper surface of this substrate and the lower surface of these many channel wire; And

Bit line, is disposed on the upper surface of these many channel wire; And

Select these many channel wire one of at least to open.

9. the method for operation of storage device as claimed in claim 8, wherein this tandem selects line, this word line and this ground connection to select line to have the first conductivity type, this source elements, this channel wire and this bit line have the second conductivity type, and this first conductivity type is contrary with this second conductivity type

The method of opening this channel wire comprises:

Apply the first the plurality of tandem that is biased in the plurality of stacked structure on the relative dual-side of this channel wire of selection and select line.

10. the method for operation of storage device as claimed in claim 9, also comprise that applying second this tandem that is biased in this stacked structure on the side of selected and this channel wire that close selects line, wherein, this channel wire of closing and this channel wire of unlatching share this tandem selection line that is applied in this first bias voltage, and this first bias voltage is positive and negative contrary with this second bias voltage.