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CN102655096A - Chip packaging method - Google Patents

Chip packaging method Download PDF

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Publication number
CN102655096A
CN102655096A CN201110056829XA CN201110056829A CN102655096A CN 102655096 A CN102655096 A CN 102655096A CN 201110056829X A CN201110056829X A CN 201110056829XA CN 201110056829 A CN201110056829 A CN 201110056829A CN 102655096 A CN102655096 A CN 102655096A
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China
Prior art keywords
chip
packaging method
carrying unit
ground ring
electrically connected
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Pending
Application number
CN201110056829XA
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Chinese (zh)
Inventor
林昌志
徐守谦
叶国裕
苏峻兴
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Powertech Technology Inc
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Powertech Technology Inc
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Priority to CN201110056829XA priority Critical patent/CN102655096A/en
Publication of CN102655096A publication Critical patent/CN102655096A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention relates to a chip packaging method, which is characterized in that a grounding ring is directly or indirectly exposed out of a packaging material, and then a conductive film electrically connected with the grounding ring is formed to form electromagnetic wave shielding, so that the external electromagnetic interference is reduced. In addition, the invention can form a large amount of conductive films of the packaging structure, thereby reducing the complexity and cost of the manufacturing process.

Description

芯片封装方法Chip Packaging Method

技术领域 technical field

本发明是关于一种芯片封装方法，尤其是关于一种形成与接地环电性连接的导电薄膜的芯片封装方法。The invention relates to a chip packaging method, in particular to a chip packaging method for forming a conductive film electrically connected to a grounding ring.

背景技术 Background technique

目前随着电子系统变得越来越小，以及系统内电子构件的密度越来越大，因此容易产生系统内的电磁干扰(electromagnetic interference，EMI)。此外，已知部分封装结构，例如射频芯片(radio frequency，RF)封装结构容易受电磁干扰影响。因此需要发展可减少电磁干扰的影响的方法及设备，以减少高密度电子系统的电磁干扰加乘效应并避免系统的效能下降或是产生错误。Currently, as the electronic system becomes smaller and the density of the electronic components in the system is higher and higher, it is easy to generate electromagnetic interference (EMI) in the system. In addition, it is known that some packaging structures, such as radio frequency (RF) chip packaging structures, are easily affected by electromagnetic interference. Therefore, it is necessary to develop methods and devices capable of reducing the influence of electromagnetic interference, so as to reduce the additive effect of electromagnetic interference in high-density electronic systems and avoid system performance degradation or errors.

目前已有设计可遮蔽电磁的外罩式阻绝结构，以减少电磁干扰。然而额外设置外罩式阻绝结构不仅增加成本，也增加制造工艺的复杂度。At present, there is an outer shield structure designed to shield electromagnetic waves to reduce electromagnetic interference. However, additionally providing an outer shield structure not only increases the cost, but also increases the complexity of the manufacturing process.

综合上述，目前仍需要发展一种新的减少电磁干扰的影响的芯片封装方法。Based on the above, it is still necessary to develop a new chip packaging method that reduces the influence of electromagnetic interference.

发明内容 Contents of the invention

本发明的目的是提供一种芯片封装方法，采用该方法可减少电磁干扰的影响并降低制造工艺的复杂度和成本。The object of the present invention is to provide a chip packaging method, which can reduce the influence of electromagnetic interference and reduce the complexity and cost of the manufacturing process.

依据本发明的一实施例，一种芯片封装方法，包括下列步骤：提供一芯片承载装置，其具有多个芯片承载单元阵列设置于其上，其中芯片承载单元具有一接地环，其设置于芯片承载单元的一上表面；分别设置一芯片于每一芯片承载单元之上表面并与其电性连接；以一封装材料覆盖每一芯片承载单元的接地环及芯片；移除一部分的封装材料以露出接地环的一部分；形成一导电薄膜，以覆盖封装材料及露出的接地环；以及切单芯片承载装置，以得到独立分隔的每一芯片承载单元。According to an embodiment of the present invention, a chip packaging method includes the following steps: providing a chip carrying device, which has a plurality of chip carrying unit arrays disposed thereon, wherein the chip carrying unit has a grounding ring, which is disposed on the chip An upper surface of the carrying unit; respectively arrange a chip on the upper surface of each chip carrying unit and electrically connect it; cover the ground ring and chip of each chip carrying unit with a packaging material; remove a part of the packaging material to expose A part of the grounding ring; forming a conductive film to cover the packaging material and the exposed grounding ring; and cutting the chip carrier device into individual chips to obtain each chip carrier unit independently.

依据本发明的另一实施例，一种芯片封装方法，包括下列步骤：提供一芯片承载装置，其具有多个芯片承载单元阵列设置于其上，其中一芯片承载单元具有一接地环，其设置于芯片承载单元的一上表面，每一芯片承载单元的接地环之间通过一导线彼此电性连结；分别设置一芯片于每一芯片承载单元之上表面并与其电性连接；以一封装材料覆盖每一芯片承载单元的接地环、导线及芯片；切单芯片承载装置，以得到独立分隔的每一芯片承载单元，并露出导线的一部分；以及形成一导电薄膜，以覆盖封装材料及露出的导线。According to another embodiment of the present invention, a chip packaging method includes the following steps: providing a chip carrying device, which has a plurality of chip carrying unit arrays arranged thereon, wherein a chip carrying unit has a grounding ring, which is set On an upper surface of the chip carrying unit, the grounding rings of each chip carrying unit are electrically connected to each other through a wire; a chip is respectively arranged on the upper surface of each chip carrying unit and electrically connected to it; a packaging material Covering the grounding ring, wires and chips of each chip carrier unit; dicing the chip carrier device to obtain each chip carrier unit independently and exposing a part of the wire; and forming a conductive film to cover the packaging material and the exposed wire.

本发明的有益效果是：本发明通过形成与接地环电性连接的导电薄膜以形成电磁波屏蔽，可减少外部的电磁干扰；本发明可大量形成封装结构的导电薄膜，因此可减少制造工艺的复杂度及成本。The beneficial effects of the present invention are: the present invention can reduce external electromagnetic interference by forming a conductive film electrically connected to the grounding ring to form electromagnetic wave shielding; the present invention can form a large number of conductive films of packaging structure, so the complexity of the manufacturing process can be reduced degree and cost.

本发明上述及其它态样、特点及优点可由附图及实施例的说明而获得更清楚的了解。The above and other aspects, features and advantages of the present invention can be clearly understood from the accompanying drawings and descriptions of the embodiments.

附图说明 Description of drawings

图1a至图1d为显示依据本发明一实施例的芯片封装方法的侧视图。1a to 1d are side views showing a chip packaging method according to an embodiment of the present invention.

图2a至图2c为显示依据本发明另一实施例的芯片封装方法的侧视图。2a to 2c are side views showing a chip packaging method according to another embodiment of the present invention.

具体实施方式 Detailed ways

请参照图1a至图1d，其为侧视图显示依据本发明一实施例的芯片封装方法。首先提供一芯片承载装置1，其具有多个芯片承载单元2阵列设置于其上。举例而言，芯片承载装置1可为一封装基板、一软性基板或一导线架。每一芯片承载单元2具有一接地环21(ground ring)，其设置于芯片承载单元2的一上表面。分别将一芯片3设置于每一芯片承载单元2的上表面并与其电性连接。芯片3与芯片承载单元2可包括打线接合或覆晶接合。Please refer to FIG. 1a to FIG. 1d , which are side views showing a chip packaging method according to an embodiment of the present invention. Firstly, a chip carrying device 1 is provided, which has a plurality of chip carrying units 2 arrayed thereon. For example, the chip carrier device 1 can be a packaging substrate, a flexible substrate or a lead frame. Each chip carrying unit 2 has a ground ring 21 (ground ring), which is disposed on an upper surface of the chip carrying unit 2 . A chip 3 is disposed on the upper surface of each chip carrying unit 2 and electrically connected thereto. The chip 3 and the chip carrying unit 2 may include wire bonding or flip chip bonding.

在一实施例中，接地环21环设于芯片3的外围，并电性连接至芯片3的接地垫(ground pad，图中未示)以使芯片3达到接地的作用。其中，接地环21的形状可为连续或不连续。其中，不连续的接地环21指的是利用绿漆或是阻隔物质隔绝接地环21，藉以增加芯片3的接合面积以及接合强度。芯片3可以接地垫与接地环21电性连接，因此部分遮蔽接地环21，或者芯片3可以通过打线与接地环21电性连接，因此未遮蔽接地环21。In one embodiment, the ground ring 21 is disposed around the periphery of the chip 3 and is electrically connected to a ground pad (not shown in the figure) of the chip 3 so that the chip 3 can be grounded. Wherein, the shape of the grounding ring 21 can be continuous or discontinuous. Wherein, the discontinuous grounding ring 21 refers to isolating the grounding ring 21 with green paint or a barrier substance, so as to increase the bonding area and bonding strength of the chip 3 . The chip 3 may be electrically connected to the ground pad and the ground ring 21 , thus partially covering the ground ring 21 , or the chip 3 may be electrically connected to the ground ring 21 through wire bonding, thus not shielding the ground ring 21 .

如图1a所示，每一芯片承载单元2的接地环21及芯片3由一封装材料4覆盖。封装材料4可为一般常用于封装的材料，例如环氧树脂，并加热使其固化。As shown in FIG. 1 a , the ground ring 21 and the chip 3 of each chip carrying unit 2 are covered by a packaging material 4 . The encapsulation material 4 can be a material commonly used in encapsulation, such as epoxy resin, which is cured by heating.

每一芯片承载单元2还包含多个焊球22，其可通过植球方法设置于芯片承载单元2的一下表面。接地环21与焊球22电性连接。其中，接地环21与焊球22是通过一通孔与焊球22电性连接；或者，接地环21与焊球22可通过一盲孔以及芯片承载单元2内部的接地层(图中未示)电性连接。Each chip carrying unit 2 further includes a plurality of solder balls 22 , which can be disposed on the lower surface of the chip carrying unit 2 by a ball planting method. The ground ring 21 is electrically connected to the solder ball 22 . Wherein, the ground ring 21 and the solder ball 22 are electrically connected to the solder ball 22 through a through hole; or, the ground ring 21 and the solder ball 22 can pass through a blind hole and the ground layer inside the chip carrying unit 2 (not shown in the figure) electrical connection.

请参照图1b，将一部分的封装材料4移除以露出接地环21的一部分。移除封装材料4的方法可包括但不限于研磨、切割或切锯。Referring to FIG. 1 b , a part of the packaging material 4 is removed to expose a part of the ground ring 21 . Methods of removing encapsulation material 4 may include, but are not limited to, grinding, cutting or sawing.

请参照图1c，接着形成一导电薄膜5，以覆盖封装材料4及露出的接地环21。所形成的导电薄膜5与接地环21电性连接，因此可以与外部的电磁辐射进行接地处理，进而减少外部的电磁干扰。其中，形成导电薄膜5的方法包括但不限于溅镀法、蒸镀法、无电解电镀法、电镀法或涂布法。如图所示，进行溅镀或其它形成导电薄膜5的过程中，可通过真空吸引平台6及吸盘61固定芯片承载装置1。Referring to FIG. 1 c , a conductive film 5 is then formed to cover the packaging material 4 and the exposed ground ring 21 . The formed conductive film 5 is electrically connected to the grounding ring 21 , so it can be grounded with external electromagnetic radiation, thereby reducing external electromagnetic interference. Wherein, the method for forming the conductive thin film 5 includes but not limited to sputtering method, vapor deposition method, electroless plating method, electroplating method or coating method. As shown in the figure, during sputtering or other processes of forming the conductive film 5 , the chip carrier 1 can be fixed by the vacuum suction platform 6 and the suction cup 61 .

导电薄膜5的厚度应足以避免芯片3受外部的电磁干扰，并取决于其材料、电阻以及所要达到的遮蔽效果。在一实施例中，导电薄膜5的材质为金属，例如但不限于铜、银、镍、金或其它组合。此外，在另一实施例中，导电薄膜5可为透明，其材质包括但不限于铟锡氧化物。The thickness of the conductive film 5 should be sufficient to prevent the chip 3 from external electromagnetic interference, and depends on its material, resistance and the desired shielding effect. In one embodiment, the conductive film 5 is made of metal, such as but not limited to copper, silver, nickel, gold or other combinations. In addition, in another embodiment, the conductive film 5 can be transparent, and its material includes but not limited to indium tin oxide.

请参照图1d，接着切单芯片承载装置1，以得到独立分隔的每一芯片承载单元2，并进行封装后段工序，例如检测作业等。Referring to FIG. 1d , the chip carrier device 1 is then singulated to obtain each chip carrier unit 2 that is independently separated, and the post-package process, such as inspection work, is performed.

其中，应注明的是芯片承载装置1的切单与形成导电薄膜5的步骤可互为先后。具体说，在一实施例的中，可以先形成导电薄膜5，再进行芯片承载装置1的切单；在另一实施例的中，可以先进行芯片承载装置1的切单，再形成导电薄膜5。Wherein, it should be noted that the steps of singulating the chip carrier device 1 and forming the conductive film 5 may be performed sequentially. Specifically, in one embodiment, the conductive film 5 can be formed first, and then the chip carrier device 1 can be singulated; in another embodiment, the chip carrier device 1 can be singulated first, and then the conductive film can be formed. 5.

请继续参照图2a至2c，其为侧视图显示依据本发明另一实施例的芯片封装方法。在另一实施例的中，提供一芯片承载装置1。分别将一芯片3设置于每一芯片承载单元2的上表面并与其电性连接。封装材料4覆盖每一芯片承载单元2的接地环21、导线7及芯片3。Please continue to refer to FIGS. 2 a to 2 c , which are side views showing a chip packaging method according to another embodiment of the present invention. In another embodiment, a chip carrier device 1 is provided. A chip 3 is disposed on the upper surface of each chip carrying unit 2 and electrically connected thereto. The packaging material 4 covers the ground ring 21 , the wire 7 and the chip 3 of each chip carrying unit 2 .

其中，相较于图1a，任两相邻的芯片承载单元2的接地环21之间可通过导线7电性连接彼此电性连结。其中导线7可以弧型的打线方式电性连接(如图所示)，或者导线7可以设置于芯片承载单元2的上表面或是内部(本图未示)以达成与接地环21的电性连接。Wherein, compared to FIG. 1 a , the grounding rings 21 of any two adjacent chip carrying units 2 can be electrically connected to each other through wires 7 . Wherein the wire 7 can be electrically connected in an arc-shaped wiring manner (as shown in the figure), or the wire 7 can be arranged on the upper surface or inside of the chip carrying unit 2 (not shown in this figure) to achieve electrical connection with the grounding ring 21. sexual connection.

请参照图2b，对芯片承载装置1进行切单，以得到独立分隔的每一芯片承载单元2，并露出导线7的一部分；并且在图2c，形成一导电薄膜5，以覆盖封装材料4及露出的导线7。其中，此实施例的实施方式与前述实施例相同，因此不再赘述。Please refer to FIG. 2 b, the chip carrier device 1 is singulated to obtain each chip carrier unit 2 that is independently separated, and a part of the wire 7 is exposed; and in FIG. 2 c, a conductive film 5 is formed to cover the packaging material 4 and The exposed wire 7. Wherein, the implementation manner of this embodiment is the same as that of the foregoing embodiments, so details are not repeated here.

综合上述，本发明通过使接地环直接或间接露出于封装材料，再形成与接地环电性连接的导电薄膜，藉以与外部的电磁辐射进行接地处理以形成电磁波屏蔽，进而减少外部的电磁干扰。此外，本发明可大量形成封装结构的导电薄膜，因此可减少制造工艺的复杂度及成本。To sum up the above, the present invention exposes the grounding ring directly or indirectly to the packaging material, and then forms a conductive film electrically connected to the grounding ring, so as to perform grounding treatment with external electromagnetic radiation to form electromagnetic wave shielding, thereby reducing external electromagnetic interference. In addition, the present invention can form a large number of conductive thin films of the encapsulation structure, so the complexity and cost of the manufacturing process can be reduced.

以上所述的实施例仅是为说明本发明的技术思想及特点，其目的在使熟悉本技术的人员能够了解本发明的内容并据以实施，当不能以其限定本发明的专利范围，即凡是根据本发明所揭示的精神所作的均等变化或修饰，仍应涵盖在本发明的专利范围内。The above-described embodiments are only for illustrating the technical idea and characteristics of the present invention, and its purpose is to enable those familiar with the art to understand the content of the present invention and implement it accordingly. When it cannot limit the patent scope of the present invention, that is, All equivalent changes or modifications made according to the spirit disclosed in the present invention shall still fall within the patent scope of the present invention.

Claims (16)

1.一种芯片封装方法，其特征在于，包含下列步骤：1. A chip packaging method, characterized in that, comprising the following steps: 提供一芯片承载装置，其具有多个芯片承载单元阵列设置于其上，其中该芯片承载单元具有一接地环，其设置于该芯片承载单元的一上表面；A chip carrying device is provided, which has a plurality of chip carrying unit arrays arranged thereon, wherein the chip carrying unit has a grounding ring, which is arranged on an upper surface of the chip carrying unit; 分别设置一芯片于这些芯片承载单元的每一个的该上表面并与其电性连接；A chip is respectively arranged on the upper surface of each of the chip carrying units and electrically connected thereto; 以一封装材料覆盖这些芯片承载单元的每一个的该接地环及该芯片；covering the ground ring and the chip of each of the chip carriers with an encapsulation material; 移除一部分的该封装材料以露出该接地环的一部分；removing a portion of the packaging material to expose a portion of the ground ring; 形成一导电薄膜，以覆盖该封装材料及露出的该接地环；以及forming a conductive film to cover the packaging material and the exposed ground ring; and 切单该芯片承载装置，以得到独立分隔的这些芯片承载单元的每一个。The chip carrier is singulated to obtain each of the chip carrier units which are individually separated. 2.根据权利要求1所述的芯片封装方法，其特征在于，该芯片与该芯片所设置的该芯片承载单元的电性连接方式包括打线接合或覆晶接合。2 . The chip packaging method according to claim 1 , wherein the electrical connection between the chip and the chip carrying unit provided with the chip includes wire bonding or flip chip bonding. 3 . 3.根据权利要求1所述的芯片封装方法，其特征在于，该芯片承载装置包括一封装基板、一软性基板或一导线架。3. The chip packaging method according to claim 1, wherein the chip carrying device comprises a packaging substrate, a flexible substrate or a lead frame. 4.根据权利要求1所述的芯片封装方法，其特征在于，形成该导电薄膜的方法包括溅镀法、蒸镀法、无电解电镀法、电镀法或涂布法。4 . The chip packaging method according to claim 1 , wherein the method for forming the conductive film comprises sputtering, vapor deposition, electroless plating, electroplating or coating. 5.根据权利要求1所述的芯片封装方法，其特征在于，该芯片部分遮蔽该接地环。5. The chip packaging method according to claim 1, wherein the chip partially shields the ground ring. 6.根据权利要求1所述的芯片封装方法，其特征在于，这些芯片承载单元的每一个还包含多个焊球，其设置于该芯片承载单元的一下表面。6. The chip packaging method according to claim 1, wherein each of the chip carrying units further comprises a plurality of solder balls disposed on a lower surface of the chip carrying unit. 7.根据权利要求6所述的芯片封装方法，其特征在于，该接地环与这些焊球是通过一通孔或一盲孔电性连结。7. The chip packaging method according to claim 6, wherein the ground ring is electrically connected to the solder balls through a through hole or a blind hole. 8.一种芯片封装方法，其特征在于，包含下列步骤：8. A chip packaging method, characterized in that, comprising the following steps: 提供一芯片承载装置，其具有多个芯片承载单元阵列设置于其上，其中每一该芯片承载单元具有一接地环，其设置于该芯片承载单元的一上表面，任两相邻的该芯片承载单元的该接地环之间通过一导线彼此电性连结；A chip carrying device is provided, which has a plurality of chip carrying unit arrays arranged thereon, wherein each of the chip carrying units has a ground ring, which is arranged on an upper surface of the chip carrying unit, and any two adjacent chips The grounding rings of the carrying unit are electrically connected to each other through a wire; 分别设置一芯片于这些芯片承载单元的每一个的该上表面并与其电性连接；A chip is respectively arranged on the upper surface of each of the chip carrying units and electrically connected thereto; 以一封装材料覆盖这些芯片承载单元的每一个的该接地环、该导线及该芯片；covering the ground ring, the wire and the chip of each of the chip carrying units with an encapsulation material; 切单该芯片承载装置，以得到独立分隔的这些芯片承载单元的每一个，并露出该导线的一部分；以及singulating the chip carrier to obtain each of the chip carrier units that are independently separated, and exposing a portion of the wire; and 形成一导电薄膜，以覆盖该封装材料及露出的该导线。A conductive film is formed to cover the encapsulation material and the exposed wires. 9.根据权利要求8所述的芯片封装方法，其特征在于，该芯片与该芯片所设置的该芯片承载单元的电性连接方式包括打线接合或覆晶接合。9 . The chip packaging method according to claim 8 , wherein the electrical connection between the chip and the chip carrying unit provided with the chip includes wire bonding or flip chip bonding. 10 . 10.根据权利要求8所述的芯片封装方法，其特征在于，该芯片承载装置包括一封装基板、一软性基板或一导线架。10. The chip packaging method according to claim 8, wherein the chip carrying device comprises a packaging substrate, a flexible substrate or a lead frame. 11.根据权利要求8所述的芯片封装方法，其特征在于，形成该导电薄膜的方法包括溅镀法、蒸镀法、无电解电镀法、电镀法或涂布法。11 . The chip packaging method according to claim 8 , wherein the method for forming the conductive film comprises sputtering, vapor deposition, electroless plating, electroplating or coating. 12.根据权利要求8所述的芯片封装方法，其特征在于，该芯片部分遮蔽该接地环。12. The chip packaging method according to claim 8, wherein the chip partially shields the ground ring. 13.根据权利要求8所述的芯片封装方法，其特征在于，这些芯片承载单元的每一个还包含多个焊球，其设置于该芯片承载单元的一下表面。13. The chip packaging method according to claim 8, wherein each of the chip carrying units further comprises a plurality of solder balls disposed on a lower surface of the chip carrying unit. 14.根据权利要求13所述的芯片封装方法，其特征在于，该接地环与这些焊球是通过一通孔或一盲孔电性连结。14. The chip packaging method according to claim 13, wherein the ground ring is electrically connected to the solder balls through a through hole or a blind hole. 15.根据权利要求8所述的芯片封装方法，其特征在于，该导线是以弧型打线方式电性连接这些芯片承载单元的每一个的该接地环。15. The chip packaging method according to claim 8, wherein the wire is electrically connected to the ground ring of each of the chip carrying units in an arc-shaped bonding manner. 16.根据权利要求8所述的芯片封装方法，其特征在于，该导线是设置于该芯片承载单元的该上表面或内部。16. The chip packaging method according to claim 8, wherein the wire is disposed on the upper surface or inside of the chip carrying unit.
CN201110056829XA 2011-03-03 2011-03-03 Chip packaging method Pending CN102655096A (en)

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Application publication date: 20120905