CN102646709A - A Fast Superjunction Vertical Double-diffused Metal Oxide Semiconductor Transistor - Google Patents

Abstract

The invention relates to a rapid super junction vertical double-diffused metal-oxide semiconductor field-effect transistor, which comprises an N-type doped silicon substrate which is also used as a drain region, an N-type doped silicon epitaxial layer and a super junction structure. The N-type doped silicon epitaxial layer is arranged on the N-type doped silicon substrate. The super junction structure is arranged in an N-type silicon doped semiconductor region. The super junction structure consists of P-type pillars and N-type pillars which are arranged at intervals. A first P-type doped semiconductor region is formed on each P-type pillar and is arranged in the N-type doped silicon epitaxial layer. A second P-type highly-doped semiconductor contact region and an N-type highly-doped semiconductor source region are arranged in the first P-type doped semiconductor region. The rapid super junction vertical double-diffused metal-oxide semiconductor field-effect transistor is characterized in that a source buried layer is arranged on the surface of each N-type pillar, the source buried layer comprises a thin oxidation layer and polycrystalline silicon on the thin oxidation layer and a polycrystalline silicon gate is connected with source metal.

Description

A Fast Superjunction Vertical Double-diffused Metal Oxide Semiconductor Transistor

technical field

The invention belongs to the technical field of semiconductor power devices, and relates to a fast-switching high-voltage power device made of silicon, especially suitable for superjunction vertical double-diffused metal oxide field-effect transistors made of silicon (Superjunction VDMOS, that is, super junction VDMOS, all of which are abbreviated as super junction VDMOS. ), more specifically, relates to a fast-switching, ultra-low-loss silicon superjunction VDMOS structure.

Background technique

At present, power devices are more and more widely used in daily life, production and other fields, especially power metal-oxide-semiconductor field-effect transistors, because they have faster switching speeds, smaller drive currents, and wider safe operating areas. , so it has been favored by many researchers. Nowadays, power devices are developing towards higher working voltage, higher working current, lower on-resistance, faster switching speed and integration. Among many power MOSFET devices, especially in vertical power MOSFETs, the invention of super junction semiconductor power devices overcomes the on-resistance of traditional power MOSFETs The contradiction between the breakdown voltage and the breakdown voltage has changed the structure of traditional power devices relying on the drift layer withstand voltage, but adopted a "super junction structure" - P-type, N-type silicon semiconductor materials are arranged alternately in the drift region form. This structure improves the situation that the breakdown voltage and on-resistance are not easy to be considered at the same time. In the off state, due to the mutual compensation effect of the depletion region electric field in the P-type column and the N-type column, the P-type column and the N-type column The doping concentration can be made very high without causing a drop in the breakdown voltage of the device. When turned on, the on-resistance of such high-concentration doped devices is significantly reduced. Due to the unique device structure of the superjunction vertical double-diffused metal oxide semiconductor field effect transistor, its electrical performance is significantly better than that of the traditional power metal oxide semiconductor field effect transistor, so this technology is called power metal oxide semiconductor field effect transistor. A milestone in semiconductor field effect transistor technology.

Power devices are not only favored in the cutting-edge technology fields such as national defense, aerospace, and aviation, but also in the fields of industry and civilian household appliances. With the increasing development of power devices, their reliability has become the focus of people's general attention. Power devices provide the required form of power supply for electronic equipment and drive for electrical equipment. Almost all electronic equipment and electrical equipment require power devices, so the research on device reliability is of great significance.

The definition of reliability is the ability of the product to complete the specified functions under specified conditions and within a specified time. The so-called prescribed conditions mainly refer to the conditions of use and environmental conditions. Service conditions refer to those stress conditions that will enter into the product or material, such as electrical stress, chemical stress and physical stress. The scope of reliability test is very wide, and its purpose is to assess various complex mechanical and environmental conditions that electronic products such as electronic components may encounter during storage, transportation and work.

However, in the traditional super-junction vertical double-diffused metal-oxide-semiconductor transistor, because the concentration of the drift region is much higher than that of the vertical double-diffused metal-oxide-semiconductor field-effect transistor, the gate parasitic capacitance is very high. During the switching process of the device, Affects switching speed and switching losses.

In addition, in the traditional vertical double-diffused metal oxide semiconductor field effect transistor, due to the fast switching speed, the voltage at both ends of the drain source of the device changes rapidly, and the drain source capacitance generates a large drift current, which flows through the P-type doped region. As a result, the parasitic triode of the device is turned on, and the device fails.

Contents of the invention

The invention provides a fast superjunction vertical double-diffused metal oxide semiconductor tube, the structure involved can reduce the parasitic capacitance of the gate, accelerate the switching speed of the device, reduce the loss in the switching process of the device, and can suppress the parasitic in the device The opening of the triode improves the reliability of the device.

The present invention provides following technical scheme:

A fast superjunction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type doped silicon substrate serving as a drain region, an N-type doped silicon epitaxial layer, and a superjunction structure, and the N-type doped silicon epitaxial The layer is set on the N-type doped silicon substrate, and the super-junction structure is set on the N-type silicon-doped semiconductor region. The super-junction structure is composed of P-type pillars and N-type pillars arranged at intervals, and on the P-type pillars There is a first P-type doped semiconductor region, and the first P-type doped semiconductor region is located in the N-type doped epitaxial layer, and a second P-type heavily doped semiconductor contact region is provided in the first P-type doped semiconductor region and an N-type heavily doped semiconductor source region, a gate oxide layer is provided above the N-type column, a polysilicon gate is provided above the gate oxide layer, a first-type oxide layer is provided on the polysilicon gate, and a second P-type heavily doped The heterosemiconductor contact region and the N-type heavily doped semiconductor source region are connected with a source metal, and there is a source buried layer on the surface of the N-type column. The source buried layer includes a thin oxide layer and polysilicon on the thin oxide layer, and the polysilicon gate and source metal connection.

Compared with prior art, the present invention has following advantage:

1. The structure of the present invention is provided with a buried source layer on the surface of the N-type pillar of the traditional super-junction structure. The buried source layer is located below the gate oxide layer. The oxide layer of the buried source layer isolates the polysilicon in it from the N-type pillar. The polysilicon in the source buried layer is connected to the source metal. The structure of the source buried layer can reduce the parasitic capacitance of the gate, accelerate the switching speed of the device, and reduce the switching loss of the device.

2. The structure of the present invention provides a current path for charging the parasitic capacitance in the device. During the turn-off process, part of the displacement current caused by the change of the drain and source voltage will flow through the source buried layer, thereby reducing the current flow. The current passing through the P-type doped region makes it more difficult to turn on the parasitic triode in the device, which enhances the reliability of the device.

Description of drawings

FIG. 1 is a schematic structural diagram of a fast superjunction vertical double-diffused metal oxide semiconductor transistor involved in the present invention.

FIG. 2 is a schematic structural diagram of a conventional superjunction vertical double-diffused metal oxide semiconductor transistor.

FIG. 3 is a schematic diagram of a displacement current path of a fast superjunction vertical double-diffused metal-oxide-semiconductor transistor involved in the present invention.

FIG. 4 is a schematic diagram of a displacement current path of a conventional superjunction vertical double-diffused metal oxide semiconductor.

Detailed ways

A fast superjunction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type doped silicon substrate 1 serving as a drain region, an N-type doped silicon epitaxial layer 2, and a superjunction structure 3. The N-type doped The heterosilicon epitaxial layer 2 is arranged on the N-type doped silicon substrate 1, and the superjunction structure 3 is arranged on the N-type silicon-doped semiconductor region 2, and the superjunction structure 3 is composed of P-type pillars 4 and N There is a first P-type doped semiconductor region 6 on the P-type pillar, and the first P-type doped semiconductor region 6 is located in the N-type doped epitaxial layer 2, and in the first P-type doped semiconductor region 6 is provided with a second P-type heavily doped semiconductor contact region 8 and an N-type heavily doped semiconductor source region 7, a gate oxide layer 9 is provided above the N-type column 5, and a polysilicon gate 10 is provided above the gate oxide layer 9. A first-type oxide layer 11 is provided on the polysilicon gate 10, a source metal 12 is connected to the second P-type heavily doped semiconductor contact region 8 and the N-type heavily doped semiconductor source region 7, and the surface of the N-type column There is a buried source layer 13 , the buried source layer 13 includes a thin oxide layer 14 and polysilicon 15 on the thin oxide layer, and the polysilicon gate 15 is connected to the source metal 12 .

The width of the source buried layer can be large or small, depending on the size of the drain-source capacitance and gate-drain capacitance, the thickness of the thin oxide layer can be adjusted, depending on the size of the drain-source capacitance, the thickness of the gate oxide layer on polysilicon can be adjusted , depending on the size of the gate-source capacitance, in this embodiment, the width of the source buried layer is 10 nanometers to 50 microns, the thickness of the thin oxide layer 14 is 1 nanometer to 5 microns, and the thickness of the gate oxide layer on the polysilicon The width of the gate oxide layer on the polysilicon is 10 nanometers to 50 micrometers.

Below with reference to accompanying drawing, specific embodiment of the present invention is described in more detail:

FIG. 1 is a schematic structural diagram of a fast superjunction vertical double-diffused metal-oxide-semiconductor transistor according to the present invention, wherein the source buried layer is arranged in the N-type epitaxial layer below the gate.

Fig. 3 is a flow direction of displacement current when a fast superjunction vertical double-diffused metal-oxide-semiconductor transistor structure involved in the present invention is turned off. It can be seen that a part of the current flows to the source buried layer, thereby reducing the current flowing to the parasitic triode , preventing the parasitic transistor from turning on.

Referring to FIG. 4 , when the conventional superjunction vertical double-diffused metal-oxide-semiconductor junction is turned off, all the displacement current flows through the base region of the parasitic triode, and the risk of turning on the parasitic triode is relatively high.

Claims (5)

1. A fast superjunction vertical double-diffused metal oxide semiconductor tube, comprising: an N-type doped silicon substrate (1), an N-type doped silicon epitaxial layer (2), a superjunction structure (3) used as a drain region ), the N-type doped silicon epitaxial layer (2) is arranged on the N-type doped silicon substrate (1), and the superjunction structure (3) is arranged on the N-type silicon-doped semiconductor region (2), so The super junction structure (3) is composed of P-type pillars (4) and N-type pillars (5) arranged at intervals, and there is a first P-type doped semiconductor region (6) on the P-type pillars, and the first P-type The doped semiconductor region (6) is located in the N-type doped epitaxial layer (2), and a second P-type heavily doped semiconductor contact region (8) and an N-type semiconductor contact region (8) are provided in the first P-type doped semiconductor region (6). A heavily doped semiconductor source region (7), a gate oxide layer (9) is provided above the N-type column (5), a polysilicon gate (10) is provided above the gate oxide layer (9), and a polysilicon gate (10) is provided on the polysilicon gate (10) A first-type oxide layer (11) is provided, and a source metal (12) is connected to the second P-type heavily doped semiconductor contact region (8) and the N-type heavily doped semiconductor source region (7), which is characterized in that , there is a source buried layer (13) on the surface of the N-type column, the source buried layer (13) includes a thin oxide layer (14) and polysilicon (15) on the thin oxide layer, polysilicon gate (15) and source metal ( 12) Connected. 2. The fast superjunction vertical double-diffused metal oxide semiconductor transistor according to claim 1, characterized in that the buried source layer (10) has a width of 10 nanometers to 50 micrometers. 3. The fast superjunction vertical double-diffused metal oxide semiconductor tube according to claim 1, characterized in that the thin oxide layer (14) has a thickness of 1 nanometer to 5 micrometers. 4. The fast superjunction vertical double-diffused metal oxide semiconductor transistor according to claim 1, characterized in that the gate oxide layer on the polysilicon (15) has a thickness of 1 nanometer to 5 micrometers. 5. The fast superjunction vertical double-diffused metal oxide semiconductor transistor according to claim 1, characterized in that the gate oxide layer on the polysilicon (15) has a width of 10 nanometers to 50 micrometers.

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