CN102624207B - Implementation method and system of half-bridge circuit ZCS (zero current switching) - Google Patents
Implementation method and system of half-bridge circuit ZCS (zero current switching) Download PDFInfo
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Abstract
The invention discloses an implementation method and system of half-bridge circuit ZCS (zero current switching), wherein a dual-way PWM (pulse width modulation) signal is directly output to a driving device of a high-power half-bridge inverter for the implementation system of the half-bridge circuit ZCS, the duty ratio regulation power of the PWM signal is regulated dynamically by use of software, and the dead zone time is regulated by regulating the phase difference of the dual-way PWM signal by use of the software, thus the triggering of the power device in current zero-crossing is realized, the switching loss of the power device is lowered to minimum, the power output range is expanded, and simultaneously the system stability is reinforced.
Description
Technical Field
The invention relates to application of a half-bridge circuit, in particular to a method and a system for realizing zero-voltage triggering of the half-bridge circuit.
Background
For semiconductor switches, the power loss is mainly due to conduction loss (conduction loss) and switching loss (switching loss). When the switches of the half-bridge circuit are switched, the current flowing through the whole power assembly at that time must be interrupted, especially when the upper and lower bridge arms are turned off at the same time, so that high switching stress is generated, and even the switching loss proportional to the switching frequency is generated. This loss is even more serious in the current trend of pursuing a light and thin high-efficiency power supply.
At present, the half-bridge inverter technology has many applications in switching power supplies, electric welding machines, electromagnetic heating and heat treatment. The circuit is rectified into half-wave direct current by single-phase alternating current when in low-power application, and then is switched into high-frequency alternating current for output through an inductor and a half-bridge switching circuit, but when in low-power application, because the load is small, zero current triggering is rarely considered, the loss of a switching device during switching is caused, and the efficiency and the power factors of an inverter device are not facilitated; in high-power application, three-phase alternating current is generally rectified into direct current, and then the direct current is switched into high-frequency alternating current for output through an inductor (a switching transformer) and a half-bridge switching circuit, but the high-power circuit is triggered by synchronous zero current in a hardware mode at present, but a hardware circuit is additionally arranged, so that the design cost is improved.
The Chinese patent with the patent application number of '201110252347.1' and the application name of 'a full-bridge soft switch direct current converter' discloses a direct current conversion circuit for realizing soft switching, which comprises an input voltage, a first switch tube, a second switch tube, an isolation transformer primary winding, two half-bridge circuits formed by the first switch tube, the second switch tube and a clamping switch tube, wherein the first switch tube, the second switch tube and the clamping switch tube are sequentially connected in series between two bridge arms of the half-bridge circuits. By adopting the mode, the collected leakage inductance energy of the primary transformer can be released in the dead time, and the ZCS soft switching of the main switching tube of the full-bridge converter is realized. Although the design can solve the problem of zero voltage triggering of the switch circuit, the circuit is complex, and only the collected leakage inductance energy can be released, and dynamic adjustment can not be performed according to the output voltage of the circuit.
Disclosure of Invention
The invention mainly solves the technical problem of providing a half-bridge circuit ZCS implementation method and a half-bridge circuit ZCS implementation system, and solves the problems that a switch circuit in the prior art is complex and cannot be dynamically adjusted.
In order to solve the technical problems, the invention adopts a technical scheme that: there is provided a method for implementing a half-bridge circuit ZCS, comprising the steps of,
step 1: generating initial values of a low-end driving voltage and a high-end driving voltage to control upper and lower bridge arms of a half-bridge circuit;
step 2: performing AND operation on the low-end driving voltage and the alternating voltage output by the half-bridge circuit, and outputting the operation result as reference voltage;
and step 3: judging whether the reference voltage is a high pulse signal or not, if so, turning to the step 4; if not, go to step 5;
and 4, step 4: increasing the dead time of the low-end driving voltage and the high-end driving voltage, and returning to the step 2;
and 5: and reducing the dead time of the low-end driving voltage and the high-end driving voltage, and returning to the step 2.
Wherein, the dead time for increasing the low-side driving voltage and the high-side driving voltage in the step 4 is specifically: the pulse width of the reference voltage is acquired, the phase lead angle of the alternating current voltage output by the half-bridge circuit corresponding to the low-end driving voltage is acquired, and the phase difference of the alternating current voltage output by the half-bridge circuit corresponding to the low-end driving voltage is increased according to the phase lead angle, so that the dead time of the low-end driving voltage and the high-end driving voltage is increased.
Wherein, the reducing the dead time of the low-side driving voltage and the high-side driving voltage in the step 5 specifically comprises: the pulse width of the reference voltage is obtained, the phase delay angle of the alternating voltage output by the half-bridge circuit corresponding to the low-side driving voltage is obtained, and the phase difference of the alternating voltage output by the half-bridge circuit corresponding to the low-side driving voltage is reduced according to the phase delay angle, so that the dead time of the low-side driving voltage and the high-side driving voltage is reduced.
In order to solve the above technical problem, the present invention further provides a half-bridge circuit ZCS implementation system, including an arithmetic unit, a half-bridge circuit and a central processing unit connected to the half-bridge circuit, where the arithmetic unit includes a first input terminal, a second input terminal and a first output terminal, and the half-bridge circuit outputs an ac voltage to the first input terminal of the arithmetic unit; the central processing unit outputs a low-end driving voltage and a high-end driving voltage for driving bridge arms of the half-bridge circuit, the low-end driving voltage and the high-end driving voltage are output to the two bridge arms of the half-bridge circuit, and the low-end driving voltage is output to a second input end of the arithmetic unit; the arithmetic unit is used for performing AND operation on the alternating-current voltage and the low-end driving voltage, taking an operation result as a reference voltage, and outputting the reference voltage to a central processing unit through a first output end of the arithmetic unit; and the central processor dynamically adjusts the dead time of the low-end driving voltage and the high-end driving voltage according to the output voltage, and changes the trigger phase of the half-bridge circuit.
Wherein the central processing unit comprises a central processing unit,
the first module is used for generating initial values of low-end driving voltage and high-end driving voltage and controlling upper and lower bridge arms of the half-bridge circuit;
the second module is used for performing AND operation on the low-end driving voltage and the alternating-current voltage output by the half-bridge circuit, and outputting the operation result as reference voltage; judging whether the reference voltage is a high pulse signal or not, and controlling a third module according to a judgment result;
and the third module is used for increasing or decreasing the dead time of the low-end driving voltage and the high-end driving voltage and turning to the first module.
The second module is specifically configured to determine whether the reference voltage is a high pulse signal, and if so, output a command to increase a dead time to the third module; if not, outputting a dead time reducing instruction to the third module.
The third module is specifically configured to obtain an increase dead time instruction or a decrease dead time instruction from the second module; when the dead time increasing command is obtained, obtaining a phase lead angle of an alternating voltage output by a half-bridge circuit corresponding to a low-end driving voltage, and increasing a phase difference of the high-end driving voltage corresponding to the low-end driving voltage according to the phase lead angle, so that the dead time of the low-end driving voltage and the high-end driving voltage is increased; or when the dead time reduction command is obtained, obtaining a pulse width of a reference voltage from a third module, obtaining a phase lag angle of a low-side driving voltage corresponding to a high-side driving voltage, and reducing a phase difference of the low-side driving voltage corresponding to the high-side driving voltage according to the phase lag angle, thereby reducing the dead time of the low-side driving voltage and the high-side driving voltage.
The invention has the beneficial effects that: the invention provides a method for realizing a half-bridge circuit ZCS, which utilizes two paths of PWM signals (low-end driving voltage and high-end driving voltage) to be directly output to the half-bridge circuit, and carries out AND operation on the low-end driving voltage and the output voltage of the half-bridge circuit, the phase condition of the low-end driving voltage and the output voltage of the half-bridge circuit can be obtained by judging whether the operation result is a high pulse signal, the dead time is adjusted by dynamically adjusting the phase difference of two paths of PWM signals according to the phase delay or advance condition, the dynamic method finally achieves balance, so that two paths of PWM signals gradually achieve the effect of zero voltage triggering of upper and lower bridge arms of a half-bridge circuit, the switching loss of a power device is reduced to the minimum, the output range of power is expanded, and simultaneously, the balance time for adjusting the half-bridge circuit can be controlled by the central processing unit, so that the stability of the system is enhanced.
Drawings
Fig. 1 is a block diagram of a half-bridge circuit ZCS implementation system provided by the present invention;
FIG. 2 is a flow chart of a method for implementing a half-bridge circuit ZCS according to the present invention;
fig. 3 is a flowchart of a specific implementation of the method for implementing the half-bridge circuit ZCS according to the present invention.
Detailed Description
In order to explain technical contents, structural features, and objects and effects of the present invention in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.
Referring to fig. 1 and fig. 2, the present invention provides a half-bridge circuit ZCS implementation system, including an operator, a half-bridge circuit and a cpu connected to the half-bridge circuit ZCS implementation system, where the operator includes a first input terminal, a second input terminal and a first output terminal, and the half-bridge circuit outputs an ac voltage to the first input terminal of the operator; the central processing unit outputs a low-end driving voltage and a high-end driving voltage for driving a bridge arm of the half-bridge circuit, the low-end driving voltage and the high-end driving voltage are connected with the half-bridge circuit, and the low-end driving voltage is also connected with a second input end of the arithmetic unit; the arithmetic unit is used for performing AND operation on the alternating-current voltage and the low-end driving voltage, taking an operation result as a reference voltage, and outputting the reference voltage to the central processing unit through a first output end of the arithmetic unit; and the central processor dynamically adjusts the dead time of the low-end driving voltage and the high-end driving voltage according to the output voltage, and changes the trigger phase of the half-bridge circuit.
The central processing unit is internally provided with a plurality of modules which specifically comprise,
the first module is used for generating initial values of low-end driving voltage and high-end driving voltage and controlling upper and lower bridge arms of a half-bridge circuit, the low-end driving voltage and the high-end driving voltage are PWM output signals of the half-bridge circuit, and the soft switching function of the half-bridge circuit can be effectively realized by controlling dead time of two paths of signals, namely the simultaneous turn-off time of the upper and lower bridge arms. The specific principle is as follows: the dead time is a protection period set for preventing the upper and lower tubes of the H-bridge or half H-bridge from being simultaneously conducted due to the problem of switching speed when PWM is output. Because power devices such as an IGBT (insulated gate power transistor) have a certain junction capacitance, a delay phenomenon of turn-on and turn-off of the devices may be caused. Generally, this effect is reduced as much as possible when designing a circuit, for example, the gate driving voltage and current are increased as much as possible, and a junction capacitance release circuit is provided. In order to ensure reliable operation of igbt and avoid direct connection of upper and lower bridge arms caused by turn-off delay effect, it is necessary to set a dead time to effectively avoid incomplete turn-off of one bridge arm caused by delay effect and direct connection and explosion of modules because the other bridge arm is in a conducting state.
The second module is used for performing AND operation on the low-end driving voltage and the alternating-current voltage output by the half-bridge circuit, and outputting the operation result as reference voltage; judging whether the reference voltage is a high pulse signal or not, and controlling a third module according to a judgment result; judging whether the reference voltage is a high pulse signal or not, and if so, outputting a command of increasing the dead time to a third module; if not, outputting a dead time reducing instruction to the third module. This is because, when the low-side driving voltage leads the ac voltage in phase, the sum of the two will generate a high pulse signal; if the low-side driving voltage is delayed in phase and the alternating voltage is applied, the high pulse signal does not appear after the two are AND operation. Therefore, the phase conditions of the low-side driving voltage and the alternating-current voltage can be known only by judging whether the operation result is a high pulse signal, and if the operation result is advanced, the phase difference between the low-side driving voltage and the high-side driving voltage needs to be increased; otherwise, the dead time is reduced.
And the third module is used for increasing or decreasing the dead time of the low-end driving voltage and the high-end driving voltage and turning to the first module. The specific implementation mode is that when the instruction of increasing the dead time is obtained, the pulse width of the reference voltage from the second module is obtained, so as to obtain a phase advance angle, and the phase difference of the low-end driving voltage and the high-end driving voltage is increased according to the phase advance angle, so as to increase the dead time of the low-end driving voltage and the high-end driving voltage; or,
when the dead time reducing command is obtained, obtaining the pulse width of the reference voltage from the second module, obtaining the phase delay angle of the alternating voltage output by the half-bridge circuit corresponding to the low-side driving voltage, and reducing the phase difference of the high-side driving voltage corresponding to the low-side driving voltage according to the phase delay angle, so that the dead time of the low-side driving voltage and the high-side driving voltage is reduced.
Referring to fig. 2, the present invention provides a method for implementing a half-bridge circuit ZCS, comprising the following steps,
step 1: generating initial values of a low-end driving voltage and a high-end driving voltage to control upper and lower bridge arms of a half-bridge circuit;
step 2: performing AND operation on the low-end driving voltage and the alternating voltage output by the half-bridge circuit, and outputting the operation result as reference voltage;
and step 3: judging whether the reference voltage is a high pulse signal or not, if so, turning to the step 4; if not, go to step 5;
and 4, step 4: specifically, a phase lead angle of the low-end driving voltage corresponding to the high-end driving voltage is obtained by obtaining a pulse width of a reference voltage, and a phase difference of an alternating current voltage output by a half-bridge circuit corresponding to the low-end driving voltage is increased according to the phase lead angle, so that the dead time of the low-end driving voltage and the dead time of the high-end driving voltage are increased. Returning to the step 2;
and 5: the dead time of the low-end driving voltage and the high-end driving voltage is reduced, the pulse width of the reference voltage is obtained, the phase delay angle of the high-end driving voltage corresponding to the low-end driving voltage is obtained, and the phase difference of the alternating current voltage output by the half-bridge circuit corresponding to the low-end driving voltage is reduced according to the phase delay angle, so that the dead time of the low-end driving voltage and the dead time of the high-end driving voltage are reduced. And returning to the step 2.
Based on the above system and method for implementing the half-bridge circuit ZCS, the present invention provides an embodiment, as shown in fig. 3, including the following steps,
step 1: the CPU generates a low-side driving voltage VPLAnd a high side driving voltage VPHThe initial value of (2) is used for controlling upper and lower bridge arms of the half-bridge circuit;
step 2: current signal I in a half-bridge circuitc0Converted into a voltage signal and shaped into a square wave signal ICThe rising edge and the falling edge of the square wave signal correspond to the zero crossing point of the current, and then the square wave signal I is processedcAnd V driving one of the legs of the half-bridge circuitPLAnd calculating to obtain a signal V1, and obtaining the AC voltage V output by the low-end driving power supply and the half-bridge circuit by the arithmetic unitCPerforming AND operation and outputting a reference voltage V1To the central processing unit, if VPLPhase lead V ofCThen V is1Is a high pulse signal, otherwise V1Then no high pulse signal will occur;
and step 3: the second module of the CPU judges the reference voltage V1If the signal is a high pulse signal, turning to the step 4 if the signal is the high pulse signal; if not, go to step 5;
and 4, step 4: the third module of the CPU obtains the pulse width of the reference voltage and the low-end driving voltage V according to the instruction of the second modulePLCorresponding high-end driving voltage VPHPhase lead angle ofIncreasing the low side driving voltage V according to the phase lead anglePLCorresponding high-end driving voltage VPHThereby increasing the low side driving voltage VPLAnd a high side driving voltage VPHReturning to the step 2;
and 5: the third module of the central processing unit obtains the reference voltage V according to the instruction of the second module1Obtaining the low-side driving voltage VPLCorresponding high-end driving voltage VPHAccording to the phase lag angle, the low-side driving voltage V is reducedPLCorresponding high-end driving voltage VPHThereby reducing the low side driving voltage VPLAnd a high side driving voltage VPHAnd (3) returning to the step 2.
Therefore, the invention utilizes the two-way PWM signal to gradually achieve the effect of zero-voltage triggering of the upper and lower bridge arms of the half-bridge circuit, so that the switching loss of the power device is reduced to the minimum, the output range of the power is expanded, meanwhile, the balance time of adjusting the half-bridge circuit can be controlled by the central processing unit, and the stability of the system is enhanced.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications of equivalent structures and equivalent processes performed by the present specification and drawings, or directly or indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (3)
1. A method for realizing a half-bridge circuit ZCS is characterized by comprising the following steps,
step 1: generating initial values of a low-end driving voltage and a high-end driving voltage to control upper and lower bridge arms of a half-bridge circuit;
step 2: performing AND operation on the low-end driving voltage and the alternating voltage output by the half-bridge circuit, and outputting the operation result as reference voltage;
and step 3: judging whether the reference voltage is a high pulse signal or not, if so, turning to the step 4; if not, go to step 5;
and 4, step 4: increasing dead time of a low-side driving voltage and a high-side driving voltage, returning to step 2, wherein the increasing of the dead time of the low-side driving voltage and the high-side driving voltage specifically includes acquiring pulse width of a reference voltage, acquiring phase advance of the low-side driving voltage corresponding to the high-side driving voltage, and increasing phase difference of the low-side driving voltage corresponding to the high-side driving voltage according to the phase advance angle, so as to increase the dead time of the low-side driving voltage and the high-side driving voltage;
and 5: reducing the dead time of the low-side driving voltage and the high-side driving voltage, and returning to step 2, wherein the reducing the dead time of the low-side driving voltage and the high-side driving voltage specifically comprises acquiring the pulse width of the reference voltage, acquiring the phase lag angle of the alternating voltage output by the half-bridge circuit corresponding to the low-side driving voltage, and reducing the phase difference of the alternating voltage output by the half-bridge circuit corresponding to the low-side driving voltage according to the phase lag angle, so as to reduce the dead time of the low-side driving voltage and the high-side driving voltage.
2. A half-bridge circuit ZCS realizing system is characterized by comprising an arithmetic unit, a half-bridge circuit and a central processing unit connected with the half-bridge circuit, wherein the arithmetic unit comprises a first input end, a second input end and a first output end,
the half-bridge circuit outputs alternating voltage to a first input end of the arithmetic unit;
the central processing unit outputs a low-end driving voltage and a high-end driving voltage for driving bridge arms of a half-bridge circuit, the low-end driving voltage and the high-end driving voltage are output to two bridge arms of the half-bridge circuit, and the low-end driving voltage is output to a second input end of the arithmetic unit, wherein the central processing unit comprises a first module for generating initial values of the low-end driving voltage and the high-end driving voltage and controlling upper and lower bridge arms of the half-bridge circuit; the second module is used for performing AND operation on the low-end driving voltage and the alternating-current voltage output by the half-bridge circuit, and outputting the operation result as reference voltage; judging whether the reference voltage is a high pulse signal or not, and controlling a third module according to a judgment result; a third module for obtaining a dead time increase or dead time decrease command and a dead time increase or dead time decrease of the low-side driving voltage and the high-side driving voltage from the second module and forwarding to the first module; obtaining the increase dead time instruction or the decrease dead time instruction from the second module specifically includes: when the command of increasing the dead time is obtained, calculating the pulse width of the reference voltage to obtain a phase lead angle, and increasing the phase difference of the low-end driving voltage and the high-end driving voltage according to the phase lead angle so as to increase the dead time of the low-end driving voltage and the high-end driving voltage; or when the dead time reduction command is obtained, calculating the pulse width of the reference voltage to obtain a phase delay angle, and reducing the phase difference between the low-side driving voltage and the high-side driving voltage according to the phase delay angle, so as to reduce the dead time of the low-side driving voltage and the high-side driving voltage;
the arithmetic unit is used for performing AND operation on the alternating-current voltage and the low-end driving voltage, taking an operation result as a reference voltage, and outputting the reference voltage to the central processing unit through a first output end of the arithmetic unit;
the central processing unit dynamically adjusts the dead time of the low-end driving voltage and the high-end driving voltage according to the output voltage, and changes the trigger phase of the half-bridge circuit.
3. The half-bridge ZCS implementation system of claim 2 wherein the second module is specifically configured to determine whether the reference voltage is a high pulse signal, and if so, output an increase dead time command to the third module; if not, outputting a dead time reducing instruction to the third module.
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| US5870291A (en) * | 1997-09-25 | 1999-02-09 | Lucent Technologies Inc. | Asymmetrical half-bridge converter having adjustable parasitic resistances to offset output voltage DC bias |
| CN101478256A (en) * | 2008-09-17 | 2009-07-08 | 清华大学 | Soft switch welding inverter, phase-shifting control method and soft switching method |
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