[go: up one dir, main page]

CN102623439B - 电容耦合器封装结构 - Google Patents

电容耦合器封装结构 Download PDF

Info

Publication number
CN102623439B
CN102623439B CN201210019307.7A CN201210019307A CN102623439B CN 102623439 B CN102623439 B CN 102623439B CN 201210019307 A CN201210019307 A CN 201210019307A CN 102623439 B CN102623439 B CN 102623439B
Authority
CN
China
Prior art keywords
electrode layer
capacitive coupler
capacitor
receiver
transmitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201210019307.7A
Other languages
English (en)
Other versions
CN102623439A (zh
Inventor
姚皓然
刘建宏
温英男
李士仪
杨惟中
楼百尧
李宏仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
XinTec Inc
Original Assignee
XinTec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by XinTec Inc filed Critical XinTec Inc
Publication of CN102623439A publication Critical patent/CN102623439A/zh
Application granted granted Critical
Publication of CN102623439B publication Critical patent/CN102623439B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Near-Field Transmission Systems (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开一种电容耦合器封装结构，其包括：一基材，其上具有至少一电容器及一接收器，此电容器至少包含一第一电极层及一第二电极层，以及一电容介电层设置于其间，其中此第一电极层以一焊球与此接收器电连接；以及一传送器，与此第二电极层电连接。

Description

电容耦合器封装结构
技术领域
本发明涉及封装技术，且特别是涉及电容耦合器的封装技术。
背景技术
电容耦合器为一种常用的隔离技术，其可在不通过任何电流的情况下进行信号交换，减少由接地电位差所导致的杂讯及损害。
传统的电容耦合器中，由于电容器与接收器及传送器均是以导线连接。因此，有较高的电阻电容延迟(RC delay)，导致电容耦合器的整体效能不佳。
系统单芯片型(system on chip)的电容耦合器可提供较快的资讯传输速度、较低的功率损耗及较高的电磁抗扰性，其为将电容器及接收器设置于同一基材上，以降低电容器及电阻器之间的阻抗。参见图1，电容器120直接设置在接收器芯片130上，且电容器120以焊线190与传送器芯片140电连接。
然而，为了使系统单芯片型的电容耦合器具有高崩溃电压(例如大于5kV)例如，需使用较厚的电容介电层(例如1.2μm)，因而易造成晶片翘曲的问题。US 2008/0277761发表了一种系统单芯片型的电容耦合器，其中的电容器使用多种介电材料的堆叠层以降低电容介电层的厚度。然而，这也造成系统单芯片型的电容耦合器制造成本高昂。
因此，业界需要的是一种能够同时具有较低的电阻电容延迟及低制造成本的电容耦合器。
发明内容
本发明的目的在于提供一种电容耦合器封装结构，以解决上述问题。
为达上述目的，本发明的实施例提供一种电容耦合器封装结构，包括：一基材，其上具有至少一电容器及一接收器，此电容器包含一第一电极层及一第二电极层，以及一电容介电层设置于其间，其中此第一电极层以一焊球与此接收器电连接；以及一传送器，与此第二电极层电连接。
本发明的实施例也提供一种电容耦合器封装结构，包括：一基材，具有一上表面及一下表面，至少一电容器，设置于此基材的上表面，此电容器至少包含一第一导电层及一第二导电层，以及一电容介电层设置于其间；一接收器，位于此基材的下表面；以及一传递器，位于此基材的下表面，且与此接收器间隔设置，其中此第一导电层及此第二导电层各自沿着此基材的两侧延伸至此接收器及此传送器作电连接。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合所附附图，作详细说明如下：
附图说明
图1为传统系统单芯片型的电容耦合器封装结构的上视图；
图2及图3为本发明一实施例的电容耦合器封装结构的上视图及剖视图；
图4至图7为本发明多个替代实施例的电容耦合器封装结构的多种变化的剖视图；
图8及图9各自为本发明另一实施例的电容耦合器封装结构的上视图及剖视图。
主要元件符号说明
120～电容器             130～接收器
140～传送器             190～焊线
210～绝缘基材           210a～绝缘基材上表面
210b～绝缘基材下表面    220～电容器
230～接收器             240～传送器
250～焊球               260～第一金属层
270～第二金属层         280～电容介电层
290～焊线               300～连接垫
310～焊球               320～焊球
330～焊球
具体实施方式
以下将详细说明本发明实施例的制作与使用方式。然应注意的是，本发明提供许多可供应用的发明概念，其可以多种特定型式实施。文中所举例讨论的特定实施例仅为制造与使用本发明的特定方式，非用以限制本发明的范围。此外，在不同实施例中可能使用重复的标号或标示。这些重复仅为了简单清楚地叙述本发明，不代表所讨论的不同实施例及/或结构之间必然具有任何关连性。再者，当述及一第一材料层位于一第二材料层上或之上时，包括第一材料层与第二材料层直接接触或间隔有一或更多其他材料层的情形。
本发明的实施例关于一种电容耦合器的封装结构。图2及图3各自绘示本发明一实施例的电容耦合器封装结构的上视图及剖视图。图4至图7绘示本发明多个实施例的电容耦合器封装结构的多种变化的剖视图。图8及图9各自绘示本发明另一实施例的电容耦合器封装结构的上视图及剖视图。
参见图2，其显示为电容耦合器封装结构的上视图。在此实施例中，在一绝缘基材210上，具有一对电容器220，其一端直接以焊球250与接收器230电连接，而此对电容器220的另一端则以焊线290与传送器240电连接，形成一电容耦合器封装结构。电容耦合器封装结构的水平长度(传送器240的外侧至接收器230的外侧，外侧为相对于电容器较远的一侧)较佳不小于约9mm，以避免空气放电(air discharge)的产生。
图3显示为图2所示的电容耦合器封装结构沿着线段AA’的剖视图。在图3中，电容耦合器封装结构包括绝缘基材210、电容器220、接收器230及传送器240，其中绝缘基材210的材质可例如为玻璃。
电容器220及接收器230位于绝缘基材210上。电容器220包含第一电极层260、第二电极层270设于多层介电层之间，其中介电层包含设于第一电极层260及第二电极层280之间的电容介电层280，电性隔离第一电极层260及第二电极层280。在一实施例中，第一电极层260及第二电极层270可包含任意的导电材料，例如铜、铝、银及/或前述的合金。电容介电层280的材质例如为环氧树脂或其他适合的绝缘物质，例如无机材料的氧化硅层、氮化硅层、氮氧化硅层、金属氧化物或其组合；或有机高分子材料的聚酰亚胺树脂(polyimide)、苯环丁烯(butylcyclobutene：BCB，道氏化学公司)、聚对二甲苯(parylene)、萘聚合物(polynaphthalenes)、氟碳化物(fluorocarbons)、丙烯酸酯(accrylates)等。电容介电层280的厚度为5～30μm。需注意的是，接收器230及传送器240上设置有多个连接垫，此处为简化图示并未显示。
在此实施例中，第一电极层260为上电极层，第二电极层270为下电极层。值得注意的是，在本发明说明书中所述的下电极层意指为相对靠近绝缘基材210的电极层，上电极层意指为相对远离绝缘基材210的电极层。在此实施例中，第一电极层260在超过第二电极层270的一末端的位置还包含一侧向延伸部分260a，且一部分的该接收器230位于该侧向延伸部分260a上。如图2所示，第一电极层260的侧向延伸部分260a包含一垂直延伸部分260a’及一水平延伸部分260a”。水平延伸部分260a”作为电容器220与接收器230连接的连接垫。焊球250设置于此水平延伸部分260a”上，以使电容器220的第一电极层260直接通过焊球250与接收器230电连接。
第二电极层270也具有超过第一电极层260的一末端的水平部分，用以作为与传送器连接的连接垫。在此实施例中，第二电极层270与传送器240以焊线290连接。由于电容器220及接收器230直接以焊球电连接，减少了接收器230及传送器240之间的电阻电容延迟(RC delay)，增进电容耦合器封装结构的整体效能。
在此绝缘基材210上，尚具有一提供接收器230信号的输出垫300，其与接收器230以一焊球310电连接。在一实施例中，焊球250及310的高度介于约250至300μm之间。焊球可包含无铅焊料，例如SnAg、SnAgCu及其介金属化合物。
图4显示本发明的另一实施例的电容耦合器封装结构的剖视图。此实施例大致上与图3所示的实施例相同，但其中电容器220、接收器230及传送器240皆设置于同一半导体基材210上，且一部分的传送器240设置在电容器220的第二金属层270上，以使传送器240与电容器220是直接通过焊球320电连接，以进一步降低电阻电容延迟。在此实施例中，电容耦合器封装结构的水平长度(传送器240的外侧至接收器230的外侧，外侧为相对于电容器较远的一侧)较佳不小于约9mm，以避免有空气放电(air discharge)产生。由于电容器220与接收器230及传送器240均是直接以焊球250、320作电连接，因而可完全避免使用焊线，大幅减少电容耦合器封装结构的电阻电容延迟(RC delay)。
图5显示本发明的又一实施例的电容耦合器封装结构的剖视图。此实施例大致上与图3所示的实施例相同，但上下电极层的配置相反。例如，在此实施例中，第一电极层260为下电极层，第二电极层270为上电极层。此外，第二电极层270具有侧向延伸部分270a，且一部分的该传送器230位于该侧向延伸部分270a上。如图5所示，第二电极层270的侧向延伸部分270a包含一垂直延伸部分270a’及一水平延伸部分270a”。水平延伸部分270a”可作为电容器220的用以与传送器240连接的连接垫，以焊线290与传送器240电连接。第一电极层260具有超过第二电极层270及电容介电层280的水平部分，用以作为与接收器230电连接的连接垫。焊球250设置于第一电极层260上并与其接触，以使电容器220的第一电极层260通过焊球250与接收器230电连接。
图6显示本发明的再一实施例的电容耦合器封装结构的剖视图。此实施例大致上与图5所示的实施例相同，但其中电容器220、接收器230及传送器240皆设置于同一半导体基材210上。在此实施例中，电容耦合器封装结构的水平长度(传送器240的外侧至接收器230的外侧，外侧为相对于电容器较远的一侧)较佳不小于约9mm，以避免有空气放电(air discharge)产生。在此实施例中，一部分的传送器240设置在电容器220的第二金属层270上，以使传送器240与电容器是直接通过焊球320电连接。由于电容器220与接收器230及传送器240均是直接以焊球250、320作电连接，因而可完全避免使用焊线，大幅减少电容耦合器封装结构的电阻电容延迟(RC delay)。
图7显示本发明的一变化实施例的电容耦合器封装结构的剖视图。在此实施例中，接收器230直接设置于电容器220上。例如，电容器220可设置于第一电极层260上，并通过焊球250与第一电极层260电连接。亦即，第一电极层260可作为与接收器230连接的连接垫。第二电极层270具有超过第一电极层260的一末端及电容介电层280的部分，用以作为与传送器240连接的连接垫。在此实施例中，第二电极层270以焊线290与传送器270电连接。然而，在另一实施例中，也可将传送器240与电容器220设置于同一半导体基材210上，以使第二电极层270与传送器240能直接以焊球电连接(未显示)。
图8显示本发明另一变化实施例的电容耦合器封装结构的上视图，其中两个电容器220的两端各自具有延伸至绝缘基材210下表面的电极层260、270。亦即，在绝缘基材210的上表面上仅具有电容器220，而接收器230及传送器240(未显示)均可视设计需求设置在绝缘基材210的下表面上。
图9显示图8所示的电容耦合器封装结构沿AA’线段的剖视图。在图9中，电容耦合器封装结构包括绝缘基材210、电容器220、接收器230及传送器240，其中绝缘基材210的材质为例如玻璃。绝缘基材210具有一上表面210a及一下表面210b，其中电容器220位于绝缘基材210的上表面上，接收器230及传递器240分隔设置于绝缘基材210的下表面上，且接收器230的外侧至传递器240的外侧较佳不小于约9mm，以避免有空气放电(airdischarge)产生。
电容器220包含第一电极层260、第二电极层270，以及一电容介电层280设置于其间，电性隔离第一电极层260及第二电极层270。在此实施例所述的电容器220可使用与图1所述的实施例相同或类似的材料。
在一实施例中，如图9所示，第一电极层260及第二电极层270各自沿着绝缘基材210的两侧壁延伸至该接收器230及该传送器240以作电连接。例如，第一电极层260沿着绝缘基材210的侧壁延伸至绝缘基材210下表面上，并在此延伸部分上设置焊球330，以使接收器230通过焊球330与电容器220的第一电极层260电连接。同样地，第二电极层270沿着绝缘基材210的另一侧壁延伸至绝缘基材210的下表面上，并在其上设置焊球330，通过焊球330与传送器240电连接。在一实施例中，电容器的水平长度可大体上等同于绝缘基材的水平长度，例如电容器的水平长度约9～15mm。在另一实施例中，电容器的水平尺寸可小于半导体基材，例如电容器的水平长度约5～11mm。值得注意的是，上、下电极层可互换，只要其各自连接到接收器230及传送器240即可。焊球可包含无铅焊料，例如SnAg、SnAgCu及其介金属化合物。
本发明的实施例提供了多种电容耦合器封装结构。在这些电容耦合器封装结构中，电容器以焊球直接与接收器电连接，有效减少因焊线所导致的电阻电容延迟(RC delay)，且也可选择性地使用焊球或焊线与传送器作电连接，或可选择接受器及传送器位于绝缘基材的上表面或下表面上，提供电路设计有极大的弹性。再者，本发明的电容耦合器封装结构中，电容器可为一般常用的电容器，与传统的系统单芯片型电容耦合器所需的电容器相较，无需较厚或特定材料的电容介电层，也解决晶片翘曲或制造成本高昂的问题。
虽然结合以上数个较佳实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作任意的更动与润饰，因此本发明的保护范围应以附上的权利要求所界定的为准。

Claims (20)

1.一种电容耦合器封装结构，包括：
基材，其上具有至少一电容器及一接收器，该电容器至少包含一第一电极层及一第二电极层，以及一电容介电层设置于其间，其中该第一电极层在该电容器的一端以一第一焊球直接与该接收器电连接；以及
传送器，在该电容器的另一端与该第二电极层电连接。
2.如权利要求1所述的电容耦合器封装结构，其中该第一电极层为上电极层，该第二电极层为下电极层。
3.如权利要求2所述的电容耦合器封装结构，其中该第一电极层还包含一侧向延伸部分，且一部分的该接收器位于该侧向延伸部分上。
4.如权利要求3所述的电容耦合器封装结构，其中该侧向延伸部分包含垂直延伸部分及水平延伸部分，且一部分的该接收器位于该水平延伸部分上。
5.如权利要求1所述的电容耦合器封装结构，其中该第一电极层为下电极层，该第二电极层为上电极层。
6.如权利要求5所述的电容耦合器封装结构，其中该第二电极层还包含侧向延伸部分，且一部分的该传送器位于该侧向延伸部分上。
7.如权利要求1所述的电容耦合器封装结构，其中该第二电极层以一第二焊球与该传送器电连接。
8.如权利要求7所述的电容耦合器封装结构，其中该传送器设置于该基材上。
9.如权利要求1所述的电容耦合器封装结构，其中该第二电极层以焊线与该传送器电连接。
10.如权利要求1所述的电容耦合器封装结构，其中该接收器设置于该电容器上。
11.如权利要求1所述的电容耦合器封装结构，其中该电容介电层的厚度为5～30μm。
12.如权利要求1所述的电容耦合器封装结构，其中该基材上还包含连接垫，且该连接垫以一第三焊球与该接收器电连接。
13.如权利要求1所述的电容耦合器封装结构，其中该接收器外侧至该传送器外侧的距离大于9mm。
14.如权利要求1所述的电容耦合器封装结构，其中该基材为绝缘基材。
15.一种电容耦合器封装结构，包括：
基材，具有上表面及下表面，
至少一电容器，设置于该基材的上表面，该电容器至少包含一第一导电层及一第二导电层，以及一电容介电层设置于其间；
接收器，位于该基材的下表面；以及
传送器，位于该基材的下表面，且与该接收器间隔设置，
其中该第一导电层及该第二导电层各自沿着该基材的两侧延伸至该接收器及该传送器作电连接。
16.如权利要求15所述的电容耦合器封装结构，其中该第一导电层为上电极层，该第二导电层为下电极层。
17.如权利要求15所述的电容耦合器封装结构，其中该第一导电层为下电极层，该第二导电层为上电极层。
18.如权利要求15所述的电容耦合器封装结构，其中该电容器具有与该基材相同的水平长度。
19.如权利要求15所述的电容耦合器封装结构，其中该接收器外侧至该传送器外侧的距离大于9mm。
20.如权利要求15所述的电容耦合器封装结构，其中该基材为绝缘基材。
CN201210019307.7A 2011-01-28 2012-01-20 电容耦合器封装结构 Expired - Fee Related CN102623439B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161437490P 2011-01-28 2011-01-28
US61/437,490 2011-01-28

Publications (2)

Publication Number Publication Date
CN102623439A CN102623439A (zh) 2012-08-01
CN102623439B true CN102623439B (zh) 2015-09-09

Family

ID=46563263

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210019307.7A Expired - Fee Related CN102623439B (zh) 2011-01-28 2012-01-20 电容耦合器封装结构

Country Status (3)

Country Link
US (1) US8791768B2 (zh)
CN (1) CN102623439B (zh)
TW (1) TWI463639B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8921988B2 (en) * 2012-12-28 2014-12-30 NeoEnergy Microelectronics, Inc. Galvanically-isolated device and method for fabricating the same
TWI532351B (zh) * 2013-11-07 2016-05-01 國立交通大學 寬頻連接結構及其連接方法、傳輸裝置及傳輸寬頻訊號的方法
TWI582677B (zh) * 2014-12-15 2017-05-11 精材科技股份有限公司 晶片封裝體及其製造方法
US10217810B2 (en) * 2015-12-07 2019-02-26 Microchip Technology Incorporated Capacitor formed on heavily doped substrate
CN110098156B (zh) * 2018-01-29 2023-04-18 光宝新加坡有限公司 用于电容耦合隔离器的电容耦合封装结构
US10916493B2 (en) * 2018-11-27 2021-02-09 International Business Machines Corporation Direct current blocking capacitors
TWI843323B (zh) * 2022-12-09 2024-05-21 新加坡商光寶科技新加坡私人有限公司 電容耦合封裝結構

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
US7227736B2 (en) * 2002-08-19 2007-06-05 Fujitsu Limited Capacitor device and method of manufacturing the same
US20070141800A1 (en) * 2005-12-20 2007-06-21 Fujitsu Limited Thin-film capacitor and method for fabricating the same, electronic device and circuit board
US7301751B2 (en) * 2004-11-11 2007-11-27 Samsung Electronics Co., Ltd. Embedded capacitor
CN101351924A (zh) * 2006-01-19 2009-01-21 株式会社村田制作所 无线ic器件以及无线ic器件用零件

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3652281B2 (ja) * 2000-06-30 2005-05-25 京セラ株式会社 薄膜電子部品および基板
US6975517B1 (en) * 2003-05-30 2005-12-13 Nortel Networks Limited Embedded preemphasis and deemphasis circuits
US8441325B2 (en) * 2004-06-03 2013-05-14 Silicon Laboratories Inc. Isolator with complementary configurable memory
US8198951B2 (en) * 2004-06-03 2012-06-12 Silicon Laboratories Inc. Capacitive isolation circuitry
US7535105B2 (en) * 2005-08-02 2009-05-19 International Business Machines Corporation Inter-chip ESD protection structure for high speed and high frequency devices
US7262974B2 (en) * 2005-10-28 2007-08-28 Cisco Technology, Inc. Techniques for alleviating the need for DC blocking capacitors in high-speed differential signal pairs
CN101889341B (zh) * 2008-10-08 2012-12-26 松下电器产业株式会社 中介层基板以及半导体装置
US20110298139A1 (en) * 2010-06-04 2011-12-08 Yi-Shao Lai Semiconductor Package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227736B2 (en) * 2002-08-19 2007-06-05 Fujitsu Limited Capacitor device and method of manufacturing the same
US7301751B2 (en) * 2004-11-11 2007-11-27 Samsung Electronics Co., Ltd. Embedded capacitor
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
US20070141800A1 (en) * 2005-12-20 2007-06-21 Fujitsu Limited Thin-film capacitor and method for fabricating the same, electronic device and circuit board
CN101351924A (zh) * 2006-01-19 2009-01-21 株式会社村田制作所 无线ic器件以及无线ic器件用零件

Also Published As

Publication number Publication date
TW201310612A (zh) 2013-03-01
CN102623439A (zh) 2012-08-01
US20120194301A1 (en) 2012-08-02
US8791768B2 (en) 2014-07-29
TWI463639B (zh) 2014-12-01

Similar Documents

Publication Publication Date Title
CN102623439B (zh) 电容耦合器封装结构
US9847299B2 (en) Semiconductor package and mounting structure thereof
CN107134445A (zh) 3dic结构及其形成方法
US10930619B2 (en) Multi-wafer bonding structure and bonding method
US9871036B2 (en) Semiconductor device
KR101428754B1 (ko) 방열 특성이 개선된 반도체 장치
US10403572B2 (en) Semiconductor device and semiconductor package including the same
JP2019057528A (ja) 半導体装置
CN103021989B (zh) 一种多组件的芯片封装结构
TW201423953A (zh) 多組件的晶片封裝結構
US20130069235A1 (en) Bonding pad structure for semiconductor devices
TWI718250B (zh) 封裝結構
TWI517354B (zh) 內藏去耦合電容之半導體封裝構造
JP6822254B2 (ja) 半導体装置
CN104851875A (zh) 具有硅通孔的半导体结构及其制作方法和测试方法
CN104051450B (zh) 半导体封装
US9142529B2 (en) Chip package with improved heat dissipation and manufacturing method thereof
US9337126B2 (en) Integrated circuit and fabricating method thereof
CN204230230U (zh) 一种焊垫结构
CN103456724A (zh) 半导体器件的封装结构
KR101392888B1 (ko) ３차원 반도체의 전원전압 공급 장치
CN100508179C (zh) 内连线结构
JP5562459B2 (ja) 半導体装置
JP6081961B2 (ja) 半導体装置
US8624365B1 (en) Interposer based capacitors for semiconductor packaging

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20150909

Termination date: 20210120

CF01 Termination of patent right due to non-payment of annual fee