CN102622984B - Display device and driving method thereof - Google Patents

Abstract

Liquid crystal display comprises: many door lines, for transmitting the gate signal having enabling voltage and close gate voltage; A plurality of data lines, for transmitting data voltage; Many storage electrode lines, for transmitting storage signal; Multiple pixel, wherein, each pixel of multiple pixel comprises the holding capacitor be connected with a storage electrode line in on-off element and many storage electrode lines; Gate driver, for generating gate signal; And multiple signal generating circuit, for generating storage signal according at least one control signal and at least one gate signal.The storage signal applied on each pixel has the voltage level changed after data voltage is charged to liquid crystal capacitor and holding capacitor.

Description

Display device and driving method thereof

This case is a divisional application of an invention patent application with an application date of October 24, 2007, an application number of 200710167150.1, and an invention title of “Display Device and Its Driving Method”.

Cross Reference Related Applications

This application claims the benefit of Korean Patent Application No. 10-2006-0103375 filed on October 24, 2006 and Korean Patent Application No. 10-2007-0041300 filed on April 27, 2007, which are hereby incorporated by reference in their entirety for all purposes refer to.

technical field

The present invention relates to a display device and a driving method thereof, in particular to a display device with increased brightness and reduced power consumption and a driving method thereof.

Background technique

In general, a liquid crystal display ("LCD") includes a first display panel including pixel electrodes, a second display panel including common electrodes, and a liquid crystal layer including an anisotropic dielectric material therebetween. The pixel electrodes are arranged in an approximate matrix pattern and connected with switching elements such as thin film transistors (“TFTs”) to sequentially receive data voltages. The common electrode is formed on the entire surface of the second display panel and may receive a common voltage. A liquid crystal capacitor is formed by each pixel electrode, a common electrode, and a liquid crystal layer therebetween. A liquid crystal capacitor and a switching element connected to the liquid crystal capacitor form a pixel unit.

In an LCD, a voltage is applied to a pixel electrode and a common electrode, forming an electric field between them, for example in a liquid crystal layer. The strength of the electric field determines the transmittance of light passing through the liquid crystal layer, and is controlled by the voltage applied to the pixel electrode and the common electrode to form a desired image. When an electric field is applied across the liquid crystal layer in only one direction (e.g. polarity), the LCD may deteriorate. To prevent degradation, the polarity of the data voltage with respect to the common voltage polarity may be reversed for each frame, row or pixel, for example.

However, the range of the data voltage for displaying an image using row inversion (for example, an inversion method in which the polarity of the data voltage is reversed per row of pixels) is smaller than that for displaying an image using dot inversion (for example, inverting the data voltage for each pixel). polarity inversion method) to display the range of image data voltage. Therefore, if the threshold voltage for driving liquid crystal in the liquid crystal layer is high as in vertical alignment ("VA") mode LCD, the low voltage of the data voltage range represented by the gray scale voltage for image display becomes as low as the threshold voltage. Therefore, it is difficult to accurately represent brightness.

In addition, small LCDs like those used in, for example, mobile phones perform row inversion that inverts the polarity of data voltages by rows of pixels to reduce power consumption, but since high resolution is required for small LCDs, performance is improved. consumption.

Contents of the invention

A display device according to an exemplary embodiment includes: a plurality of gate lines for transmitting a gate signal having a gate opening voltage and a gate closing voltage; a plurality of data lines for transmitting a data voltage; a plurality of storage electrode lines for transmitting a storage signal ; A plurality of pixels arranged in an approximate matrix pattern, wherein each pixel of the plurality of pixels includes a switching element connected to a gate line in a plurality of gate lines and a data line in a plurality of data lines, and a switch element and a plurality of data lines a common voltage-connected liquid crystal capacitor and a storage capacitor connected to the switching element and one of the plurality of storage electrode lines; a gate driver for generating a gate signal along the first scanning direction or the second scanning direction; and a plurality of A signal generation circuit for generating a storage signal according to at least one control signal and at least one gate signal.

The storage signal applied to at least one of the plurality of pixels has a voltage level that changes after the charging data voltage is charged to the liquid crystal capacitor and the storage capacitor, and an output sequence of the storage signal from the plurality of signal generation circuits follows scanning of the gate driver. direction changes.

When the charging data voltage has a positive polarity, the storage signal may change from a low level to a high level, and when the charging data voltage has a negative polarity, the storage signal may change from a high level to a low level.

The storage signal applied to a given storage electrode line of the plurality of storage electrode lines may be inverted every successive frame.

The utility voltage may be a fixed voltage.

The plurality of pixels may include a first pixel supplied with the first gate signal, a second pixel adjacent to the first pixel supplied with the second gate signal, and a third pixel adjacent to the first pixel supplied with the third gate signal .

The plurality of signal generation circuits may include a first signal generation circuit that transmits the first storage signal to the storage electrode line of the first pixel, a second signal generation circuit that transmits the second storage signal to the storage electrode line of the second pixel, and The third storage signal is transmitted to the third signal generating circuit of the storage electrode line of the third pixel.

In an alternative exemplary embodiment of the present invention, the first gate signal or the third gate signal is supplied to the second signal generation circuit, or the second gate signal may be supplied to the second signal generation circuit.

The at least one control signal may include a first control signal, a second control signal and a third control signal. At least one signal generation circuit of the plurality of signal generation circuits may include a signal input unit receiving at least one gate signal and outputting a drive control signal according to the at least one gate signal, receiving a first control signal and transmitting a second drive control signal according to the drive control signal from the signal input unit. a control signal as a storage signal applying unit for the storage signal, a control unit for receiving the second control signal and the third control signal and changing the operation state of the control unit according to the driving control signal, and the second control signal applied according to the operation state of the control unit and a third control signal, a signal holding unit that holds the storage signal from the storage signal applying unit.

The signal input unit may further receive the first direction signal and the second direction signal each having a signal state based on a scanning direction of the gate driver. The first direction signal and the second direction signal may have substantially opposite phases.

At least one gate signal may include a first gate signal and a second gate signal, and a time difference between the gate opening voltage application time of the first gate signal and the gate opening voltage application time of the second gate signal is approximately two horizontal periods ("2H" ).

The signal input unit may select one of the first gate signal and the second gate signal according to the first direction signal and the second direction signal, and output a driving control signal according to the selected first gate signal or the second gate signal.

Each of the first direction signal and the second direction signal may maintain a substantially uniform level.

The first direction signal and the second direction signal may have a first level voltage and a second level voltage, respectively, and the first direction signal and the second direction signal may be between the first level voltage and the second level every successive predetermined periods. Alternate between voltages. The predetermined period may be approximately one horizontal period (“1H”).

The phase of the first direction signal applied to the first signal generation circuit of the plurality of signal generation circuits and the second direction signal applied to the second signal generation circuit of the plurality of signal generation circuits adjacent to the first signal generation circuit The phases of can be practically reversed.

The signal input unit may include a first transistor including a control terminal connected to the first direction signal, an input terminal connected to the first gate signal, and an output terminal connected to the driving control signal. The signal input unit may further include a second transistor including a control terminal connected to the second direction signal, an input terminal connected to the second gate signal, and an output terminal connected to the driving control signal.

The at least one gate signal may include a first gate signal and a second gate signal, and a time difference between the gate opening voltage application time of the first gate signal and the gate opening voltage application time of the second gate signal is approximately four horizontal periods ("4H" ).

The signal input unit may select one of the first direction signal and the second direction signal according to the first gate signal and the second gate signal, and output a driving control signal according to the selected direction signal.

Each of the first direction signal and the second direction signal may maintain a consistent level.

A clock signal having a first level voltage and a second level voltage different from the first level voltage may be further supplied to the signal input unit, and the clock signal may switch between the first level voltage and the second level voltage every successive predetermined periods. Alternate between flat voltages. The predetermined period may be approximately two horizontal periods (“2H”).

A phase of a clock signal applied to a first signal generating circuit of the plurality of signal generating circuits and a phase of a clock signal applied to a second adjacent signal generating circuit of the plurality of signal generating circuits are substantially opposite.

The signal input unit may operate the signal holding unit by changing a state of the driving control signal based on the first direction signal or the second direction signal according to the clock signal.

In an alternative exemplary embodiment, the signal input unit may include: a first transistor having an input terminal connected to the first direction signal, a control terminal connected to the first gate signal, and an output terminal connected to the driving control signal; The input end connected with the second direction signal, the control end connected with the second gate signal and the second transistor with the output end connected with the driving control signal; and the input end connected with the closing gate voltage, the control end connected with the clock signal and the A third transistor that drives the output of the control signal connection.

A voltage level of a storage signal applied to a first storage electrode line of the plurality of storage electrode lines is substantially the same as a voltage level of a storage signal applied to a second adjacent storage electrode line of the plurality of storage electrode lines. The voltage level of the first control signal, the voltage level of the second control signal and the voltage level of the third control signal are substantially identical within a given frame and inverted every successive frame.

A gate clock signal and a voltage having a first level voltage and a second level voltage different from the first level voltage may be supplied to the signal input unit, and the clock signal may be switched between the first level voltage and the second level voltage every successive predetermined periods. Alternate between flat voltages. The predetermined period may be approximately two horizontal periods (“2H”).

A phase of a clock signal applied to a first signal generating circuit of the plurality of signal generating circuits and a phase of a clock signal applied to a second adjacent signal generating circuit of the plurality of signal generating circuits are substantially opposite.

In an alternative exemplary embodiment, the signal input unit may operate the signal holding unit by changing a state of the driving clock signal based on the at least one gate signal according to the clock signal. Also, the signal input unit may include a first transistor including a control terminal and an input terminal each connected to a gate signal and an output terminal connected to a drive control signal; and a control terminal connected to a clock signal and an input terminal connected to a gate signal. terminal and a second transistor at the output terminal connected to the drive control signal.

The storage signal applying unit may include a first transistor including a control terminal connected to the output terminal of the signal input unit, an input terminal connected to the first control signal, and an output terminal connected to the storage electrode line.

The control unit may include a second transistor having a control terminal connected to the output terminal of the signal input unit and an input terminal connected to the second control signal, and a second transistor comprising a control terminal connected to the output terminal of the signal input unit and a control terminal connected to the third control signal. The third transistor at the input.

The signal holding unit may include a fourth transistor including a control terminal connected to the output terminal of the third transistor, an input terminal connected to the first driving voltage, and an output terminal connected to the storage electrode line, and a fourth transistor connected to the output terminal of the second transistor. A fifth transistor having a control terminal, an input terminal connected to the second driving voltage, and an output terminal connected to the storage electrode line. The signal holding unit may further include a first capacitor connected between the input terminal and the control terminal of the fourth transistor and a second capacitor connected between the input terminal and the control terminal of the fifth transistor.

A voltage level of a storage signal applied to a first storage electrode line of the plurality of storage electrode lines is different from a voltage level of a storage signal applied to a second adjacent storage electrode line of the plurality of storage electrode lines.

Each of the first control signal, the second control signal and the third control signal may have a first level voltage and a second level voltage, and the respective levels of the first control signal, the second control signal and the third control signal are at Alternating between the first level voltage and the second level voltage may occur every successive period within a given frame. And, respective levels of the first control signal, the second control signal, and the third control signal may be inverted every other frame.

The display device according to an exemplary embodiment of the present invention may further include at least one additional gate line transmitting a gate signal to one signal generating circuit of the plurality of signal generating circuits.

A gate opening voltage of a first gate signal transmitted to a first gate line of the plurality of gate lines and a gate opening voltage of a second gate signal transmitted to an adjacent second gate line of the plurality of gate lines within at least a portion of a predetermined time period overlap each other.

The interval of the predetermined time period may be about one horizontal period ("1H").

Still another exemplary embodiment of the present invention provides a driving method of a liquid crystal display. The liquid crystal display includes a plurality of gate lines for transmitting gate signals with a gate opening voltage; a plurality of data lines for transmitting data voltages; a plurality of storage electrode lines for transmitting storage signals; a plurality of switching elements, a plurality of switches Each switching element of the element is connected to one gate line among the plurality of gate lines and one data line among the plurality of data lines; a plurality of pixels, each pixel of the plurality of pixels includes a switching element connected to one of the plurality of switching elements a storage capacitor connected to one of the plurality of storage electrode lines; a gate driver for generating gate signals along the first or second scanning direction; and a plurality of signal generating circuits for generating storage signals.

The driving method includes applying a first gate signal to a first gate line of a plurality of gate lines connected to a first pixel of a plurality of pixels, and applying a first data voltage to a plurality of data lines connected to a first pixel. Applying a second gate signal to a second gate line of the plurality of gate lines connected to a second pixel of the plurality of pixels on the first data line, and outputting a storage signal to the first pixel according to the second gate signal. The output order of the storage signals varies with the first scanning direction or the second scanning direction of the gate driver.

The application time of the gate opening voltage of the first gate signal and the application time of the gate opening voltage of the second gate signal are separated by approximately two horizontal periods (“2H”), or in an alternative exemplary embodiment, approximately four horizontal periods apart. ("4H").

In yet another exemplary embodiment, a driving method of a liquid crystal display is provided. The liquid crystal display includes a plurality of gate lines for transmitting gate signals with a gate opening voltage; a plurality of data lines for transmitting data voltages; a plurality of storage electrode lines for transmitting storage signals; a plurality of switching elements, a plurality of switches Each switching element of the element is connected to one gate line among the plurality of gate lines and one data line among the plurality of data lines; a plurality of pixels, each pixel of the plurality of pixels includes a switching element connected to one of the plurality of switching elements a storage capacitor connected to one of the plurality of storage electrode lines; a gate driver for generating gate signals along the first or second scanning direction; and a plurality of signal generating circuits for generating storage signals.

The driving method includes applying a gate signal to one of the plurality of gate lines connected to one of the plurality of pixels, applying a data voltage to one of the plurality of data lines connected to the pixel, And output the storage signal to the pixel according to the gate signal. The output order of the storage signals varies with the first scanning direction or the second scanning direction of the gate driver.

Description of drawings

The above and other aspects, features and advantages of the present invention will become more apparent by describing in further detail exemplary embodiments of the present invention in conjunction with the accompanying drawings, in which:

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention;

2 is an equivalent circuit diagram of a pixel of a liquid crystal display according to an exemplary embodiment of the present invention;

3 is a schematic circuit diagram of a signal generating circuit according to an exemplary embodiment of the present invention;

FIG. 4 is a signal timing diagram of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 3;

5 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention;

6 is a schematic circuit diagram of a signal generating circuit of a storage signal generating circuit according to an exemplary embodiment of the present invention in FIG. 5;

7A and 7B are signal timing diagrams of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 6;

8A and 8B are signal timing diagrams of a signal generating circuit according to an alternative exemplary embodiment of the present invention;

9 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention;

FIG. 10 is a schematic circuit diagram of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 9;

FIG. 11 is a plan layout diagram of a signal generation circuit according to an exemplary embodiment of the present invention in FIG. 10;

12 is a signal timing diagram illustrating the relationship between a gate clock signal applied to a gate driver and a storage clock signal applied to a storage signal generator according to an embodiment of the present invention;

13A and 13B are signal timing diagrams of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 10;

14 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention;

FIG. 15 is a schematic circuit diagram of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 14;

FIG. 16 is a plan layout diagram of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 15;

17A is a signal timing diagram of a signal generation circuit according to the exemplary embodiment of the present invention in FIG. 15 using row inversion; and

FIG. 17B is a signal timing diagram of the signal generation circuit according to the exemplary embodiment of the present invention in FIG. 15 using frame inversion.

Detailed description of the invention

Now, the present invention will be described more fully hereinafter with reference to the accompanying drawings that illustrate exemplary embodiments of the invention. However, this invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals denote like elements throughout.

It will be understood that when an element is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present therebetween. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprising" or "comprising", when used in this specification, specifies the presence of said features, regions, integers, steps, operations, elements and/or components, but does not exclude the presence or addition of one or more Other features, regions, integers, steps, operations, elements, parts and/or groups thereof.

Also, relative terms like "lower" or "bottom" and "upper" or "top" may be used herein to describe one element's relationship to other elements as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, depending on the particular orientation of the view, the exemplary term "below" can encompass both "lower" and "upper" orientations. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It should also be understood that terms such as those defined in commonly used dictionaries should be interpreted to have meanings consistent with their meanings in the relevant technical context, and should not be idealized or overly formal unless explicitly so defined herein. explain.

Exemplary embodiments of the present invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments of the present invention. As such, shapes other than those illustrated may be expected due to reasons such as manufacturing techniques and/or tolerances. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, a region illustrated or described as flat, often will have rough and/or non-linear features. Additionally, the illustrated sharp corners may be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the exact shape of a region and are not intended to limit the scope of the invention.

The present invention will now be described in further detail with reference to the accompanying drawings.

FIG. 1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of a pixel PX of the liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a liquid crystal display ("LCD") according to an exemplary embodiment of the present invention includes, for example, a liquid crystal panel assembly 300, a gate driver 400, a data driver 500, a grayscale voltage generator 800 connected to the data driver 500, The signal generator 700 and the signal controller 600 controlling the above elements are stored, but not limited thereto.

The liquid crystal panel assembly 300 includes multiple signal lines (G ₁ -G _2n , G _d , D ₁ -D _m and S ₁ -S _2n ) and multiple signal lines (G ₁ -G _2n , G _d , D ₁ - D _m and S ₁ -S _2n ) are connected and arranged into a plurality of pixels PX in an approximate matrix pattern.

Referring to FIG. 2 , the liquid crystal panel assembly 300 includes a lower panel 100 and an upper panel 200 facing each other and a liquid crystal layer 3 between the lower panel 100 and the upper panel 200 .

Referring to Figure 1, multiple signal lines (G ₁ -G _2n , G _d , D ₁ -D _m and S ₁ -S _2n ) include multiple gate lines G ₁ -G _2n and G _d , multiple data lines D ₁ -D _m and a plurality of storage electrode lines S ₁ -S _2n .

The plurality of gate lines G ₁ -G _2n and G _d includes a plurality of normal gate lines G ₁ -G _2n and additional gate lines G _d that transmit gate signals (hereinafter collectively referred to as "scanning signals"). Multiple storage electrode lines S ₁ -S _2n are connected with multiple normal gate lines G ₁ -G _2n to transmit storage signals. The plurality of data lines D ₁ -D _m transmit data voltages.

A plurality of gate lines G ₁ -G _2n , G _d and a plurality of storage electrode lines S ₁ -S _2n extend along a first approximate (substantially) row direction and are actually (substantially) parallel to each other, while a plurality of data lines D ₁ - D _m extend along a second approximate column direction perpendicular to the first direction and substantially parallel to each other.

Referring to FIG. 2 again, each pixel PX (for example, with the i-th normal gate line G _i (i=1, 2, ..., 2n), the i-th normal storage signal line S _i (i=1, 2, . .., 2n) and the j-th data line _Dj (j=1, 2, ..., m) connected to the pixel PX) includes a switching element Q connected to the signal line G _i and D _j and a switching element Q and The storage signal line S _i is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

In an exemplary embodiment, the switching element Q may be implemented as, for example, a three-terminal element like a thin film transistor (“TFT”) mounted on the lower panel 100 , but is not limited thereto. As shown in FIG. 2, the three-terminal element has a control terminal connected to the normal gate line _Gi , an input terminal connected to the data line _Dj , and an output terminal connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200 are the first end and the second end of the liquid crystal capacitor Clc, respectively. The liquid crystal layer 3 between the pixel electrode 191 and the common electrode 270 functions as a dielectric material. The pixel electrode 191 is connected to the switching element Q. The common electrode 270 is located on the entire upper panel 200 and receives a common voltage Vcom (not shown). Alternatively, the common electrode 270 may be formed on the lower panel 100, and in this case, at least one of the pixel electrode 191 and the common electrode 270 may have an approximately linear shape.

In alternative exemplary embodiments of the present invention, the common voltage Vcom may include, for example, a direct current (“DC”) voltage having a predetermined value, but is not limited thereto.

The storage capacitor Cst assists the liquid crystal capacitor Clc by forming the pixel electrode 191 intersecting the storage electrode line S _i with an insulator in between.

For a color display, each pixel PX may represent one primary color, eg an apatial division, or alternatively each pixel PX may represent a different primary color depending on a given time, eg a time division. Either way, the desired color is displayed by the spatial or temporal sum of the primary colors, eg, red, green, and blue.

Figure 2 shows an exemplary embodiment of the invention utilizing air separation. As shown, each pixel PX includes a color filter 230 representing one of three primary colors, for example, one of red, green and blue, on a region of the upper panel 200 corresponding to the pixel electrode 191 . In an alternative exemplary embodiment of the present invention, the color filter 230 may be formed under or over the pixel electrode 191 of the lower panel 100 .

A polarizer (not shown) for polarizing light is attached to the liquid crystal panel assembly 300 .

Referring back to FIG. 1 , the gray voltage generator 800 may generate all gray voltages or a limited number of gray voltages (hereinafter referred to as 'reference gray voltages') related to the required transmittance of the pixel PX. Some (reference) grayscale voltages have positive polarity with respect to the common voltage Vcom, while other (reference) grayscale voltages have negative polarity with respect to the common voltage Vcom.

The gate driver 400 includes, for example, a first gate driving circuit 400a and a second gate driving circuit 400a located on opposite sides of the liquid crystal panel assembly 300 like left and right sides, but is not limited thereto.

The first gate driving circuit 400a is connected to one end of the odd-numbered normal gate lines _G1 , G3, ..., and _{G2n -1 of} the plurality of gate lines _G1 - _G2n and Gd and the additional gate line _Gd . The second gate driving circuit 400b is connected to one end of even-numbered normal gate lines G ₂ , G ₄ , . . . , and G _2n of the plurality of gate lines G ₁ -G _2n and G _d . Alternatively, the second gate drive circuit _400b can be connected to odd-numbered normal gate lines G ₁ , G ₃ , . . . , and G _{2n -1 and} additional gate lines G _d , and the first gate drive circuit 400a can be connected to one end of the even-numbered normal gate lines G ₂ , G ₄ , . . . , and G _2n of the multiple gate lines G ₁ -G _2n and G _d .

Each of the first gate driving circuit 400a and the second gate driving circuit 400b uses a gate-on voltage (gate-on voltage) Von and a gate-off voltage (gate-off voltage) Voff to generate voltages applied to a plurality of gate lines G ₁ -G _2n and G Gate signal on _d .

In an exemplary embodiment of the present invention, the gate driver 400 is integrated into the liquid crystal panel assembly 300 together with a plurality of signal lines G ₁ -G _2n , G _d , D ₁ -D _m and S ₁ -S _2n and switching elements Q middle. In an alternative exemplary embodiment, the gate driver 400 may include a flexible printed circuit (“FPC”) mounted on the liquid crystal panel assembly 300 , or mounted in a thin film package (“TCP”) attached to the liquid crystal panel assembly 300 At least one integrated circuit ("IC") chip on the film. Alternatively, the gate driver 400 may be mounted on a separate printed circuit board (not shown).

For example, the storage signal generator 700 includes a first storage signal generating circuit 700a and a second storage signal generating circuit 700b arranged on opposite sides of the liquid crystal panel assembly 300 and adjacent to the first gate driving circuit 400a and the second gate driving circuit 400b , but not limited to this.

The first storage signal generating circuit 700a is connected to odd-numbered storage electrode lines S ₁ , S ₃ , ..., S _2n-1 and even-numbered normal gate lines G ₂ , G ₄ , ..., G _2n , and will have A plurality of storage signals of high-level voltage and low-level voltage are applied to storage electrode lines S ₁ , S ₃ , . . . , S _2n-1 .

The second storage signal generating circuit 700b is connected to the even-numbered storage electrode lines S ₂ , S ₄ , ..., S and the odd-numbered normal gate lines G ₃ , G ₅ , ... except for the first normal gate line G ₁ , G _2n-1 is connected to the additional gate line _Gd , and a plurality of storage signals with high-level voltage and low-level voltage are applied to the storage electrode lines S ₂ , S ₄ , . . . , S _2n .

In an alternative exemplary embodiment of the present invention, the signal from the additional gate line _Gd connected to the gate driver 400 may not be supplied to the storage signal generator 700 . More precisely, the storage signal generator 700 may be supplied with signals from, for example, a discrete unit like the signal controller 600 or a discrete signal generator (not shown), but is not limited thereto. In this case, as described above, the additional gate line G _d may not be formed on the liquid crystal panel assembly 300 .

In an exemplary embodiment of the present invention, the storage signal generator 700 is integrated into the liquid crystal panel together with a plurality of signal lines G ₁ -G _2n , G _d , D ₁ -D _m and S ₁ -S _2n and switching elements Q Component 300. In an alternative exemplary embodiment, the memory signal generator 700 may include at least one IC chip mounted on the liquid crystal panel assembly 300 , or mounted on an FPC film in TCP attached to the liquid crystal panel assembly 300 . Alternatively, the memory signal generator 700 may be mounted on a separate printed circuit board (not shown).

The data driver 500 is connected to the plurality of data lines D1 _{- Dm} of the panel assembly 300, and applies a data voltage selected from gray voltages supplied from the gray voltage generator 800 to the plurality of data lines D1 _{- Dm} . However, when the gray voltage generator 800 generates only some but not all of the gray voltages, the data driver 500 may divide the reference gray voltages to generate data voltages from the gray voltages.

The signal controller 600 controls the gate driver 400 , the data driver 500 and the storage signal generator 700 .

In an exemplary embodiment, the data driver 500, the signal controller 600, and the grayscale voltage generator 800 may include an FPC film installed on the liquid crystal panel assembly 300 or a TCP attached to the liquid crystal panel assembly 300. At least one IC chip. Alternatively, at least one of the data driver 500, the signal controller 600, and the grayscale voltage generator 800 may communicate with a plurality of signal lines G ₁ -G _2n , G _d , D ₁ -D _m , and S ₁ -S _2n and switches The elements Q are integrated into the liquid crystal panel assembly 300 together. In yet another alternative exemplary embodiment, each of the data driver 500, the signal controller 600 and the gray voltage generator 800 may be integrated into a single IC chip, but the data driver 500, the signal controller 600 and the gray voltage At least one of the generator 800, or at least one circuit element of at least one of the data driver 500, the signal controller 600, and the gray voltage generator 800 may be located outside a single IC chip.

Still referring to FIGS. 1 and 2, the operation of the liquid crystal display will now be described in further detail.

The signal controller 600 receives input image signals R, G, and B and a plurality of input control signals controlling the input image signals R, G, and B from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of the pixel PX, and the luminance has a predetermined number of grayscale values, for example, 1024 (=2 ¹⁰ ), 256 (=2 ⁸ ) or 64 (=2 ⁶ ) grayscales degree values, but are not limited to these.

For example, the plurality of input control signals include a vertical sync signal Vsync, a horizontal sync signal Hsync, a master clock signal MCLK, and a data enable signal DE, but are not limited thereto.

The signal controller 600 processes the input image signals R, G, and B according to an input control signal (not shown) and the input image signals R, G, and B, and, according to the operating conditions of the liquid crystal panel assembly 300, generates a gate control signal CONT1, data The control signal CONT2 and the storage control signal CONT3 apply the gate control signal CONT1 to the gate driver 400, apply the data control signal CONT2 and the digital image signal DAT to the data driver 500, and apply the storage control signal CONT3 to the storage signal generator 700 superior.

The gate control signal CONT1 includes a first scan start signal STV1 (not shown) and a second scan start signal STV2 (not shown) that determine the start of the gate open voltage Von and at least one clock signal (not shown) that controls the output period of the gate open voltage Von. Shows). In an exemplary embodiment, the first scan start signal STV1 is applied to the first gate driving circuit 400a, and the second scan start signal STV2 is applied to the second gate driving circuit 400b. In an alternative exemplary embodiment of the present invention, the first scan start signal STV1 may be applied to the second gate driving circuit 400b, and the second scan start signal STV2 may be applied to the first gate driving circuit 400a.

The gate control signal CONT1 may further include an output enable signal OE (not shown) limiting a time period of the gate opening voltage Von.

The data control signal CONT2 includes a horizontal synchronization start signal STH (not shown) for determining the start of data transfer of each row of pixels PX, a load signal LOAD (not shown) for applying data voltages to a plurality of data lines D1 _{- Dm} ) and data clock signal HCLK (not shown). The data control signal CONT2 may further include an inversion signal RVS (not shown) that inverts the polarity of the data voltage with respect to the common voltage Vcom.

In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT of each row of the pixels PX from the signal controller 600, converts the digital image signal DAT into a block data voltage selected from grayscale voltages, and The module data voltage is applied to multiple data lines D ₁ -D _m .

The gate driver 400 responds to the gate control signal CONT1 from the signal controller 600, and applies the gate-opening voltage Von to the current row of gate lines, for example, the corresponding normal gate lines of the i-th row, thereby turning on the respective normal gate lines of the i-th row. The associated switching elements Q are connected by wires. Therefore, the analog data voltage is applied to the data lines D1 _{- Dm} , and then supplied to each pixel PX in the i-th row by turning on the switching transistor Q, so that the liquid crystal capacitor Clc in the pixel PX in the i-th row is charged by the analog data voltage. and the storage capacitor Cst is charged.

In an exemplary embodiment, the additional gate line _Gd is not connected to the switching element Q. Referring to FIG.

The difference between the analog data voltage applied to each pixel PX and the common voltage Vcom is expressed as a voltage difference across the liquid crystal capacitor Clc of the pixel PX, which is referred to as a pixel voltage. The liquid crystal molecules in the liquid crystal capacitor Clc are oriented according to the magnitude of the pixel voltage, and the orientation of the liquid crystal molecules determines the polarity of light passing through the liquid crystal layer 3 . A polarizer (not shown) converts light polarization into light transmittance so that a given pixel PX has a brightness proportional to the level of an analog data voltage, eg, pixel voltage, applied to the pixel PX.

After a horizontal period (“1H”) equal to one period of the horizontal synchronization signal Hsync and the data enable signal DE, the data driver 500 applies the data voltage to the pixel PX of the (i+1)th row, for example, the subsequent row, And the gate driver 400 applies the gate closing signal Voff to the ith row and applies the gate opening signal Von to the (i+1)th row of pixels. As a result, the switching element Q in the i-th row is turned off, and the pixel electrode 191 in the i-th row is floated.

The storage signal generator 700 changes the voltage level of the storage signal applied to the i-th storage electrode line S _i according to the storage control signal CONT3 and the voltage change of the gate signal applied to the (i+1)th gate line G _i+1 . flat. Therefore, the voltage of the pixel electrode 191 connected to one end of the storage capacitor Cst varies with the voltage of the storage electrode line S _i connected to the other end of the storage capacitor Cst.

By repeating the process described above for all subsequent rows of pixels, the LCD will display a single frame of image. When the subsequent frame starts, an inversion signal RVS (not shown) applied to the data driver 500 is controlled so as to invert the polarity of the analog data voltage. In other words, the polarity of the data voltages for a given frame is the same, but reversed with respect to the data voltages of the previous frame, referred to as "frame inversion".

In addition, the polarities of the data voltages applied to the pixels PX of one row may be approximately the same, while the polarities of the data voltages applied to the pixels PX of the previous and subsequent adjacent rows are reversed (for example, the row invert).

In an exemplary embodiment of the present invention performing frame inversion and/or row inversion, the polarities of all data voltages applied to pixels PX of one row alternate positive and negative with each successive row. Also, when the pixel electrode 191 is charged by the positive data voltage, the storage signal applied to the plurality of storage electrode lines S ₁ -S _2n changes from a low-level voltage to a high-level voltage. On the contrary, when the pixel electrode 191 is charged by the data voltage of negative polarity, the storage signal is changed from a high-level voltage to a low-level voltage. As a result, when the pixel electrode 191 is charged with a positive data voltage of positive polarity, the voltage of the pixel electrode 191 increases, and when the pixel electrode 191 is charged with a negative data voltage, the voltage of the pixel electrode 191 decreases. As a result, the range of the voltage level of the pixel electrode 191 is increased to be larger than the range of the gray voltage on which the data voltage is based. As a result, the luminance range can be increased without increasing the range of gray scale voltages.

The first storage signal generation circuit 700 a and the second storage signal generation circuit 700 b include a plurality of signal generation circuits 710 ( FIG. 3 ) connected to a plurality of storage electrode lines S ₁ -S 2 _n . An example of the signal generating circuit 710 is now described in further detail with reference to FIGS. 3 and 4 .

FIG. 3 is a schematic circuit diagram of a signal generating circuit according to an exemplary embodiment of the present invention, and FIG. 4 is a signal timing diagram of the signal generating circuit according to the exemplary embodiment of the present invention in FIG. 3 .

Referring to FIG. 3 , the signal generating circuit 710 includes an input terminal IP and an output terminal OP. In the i-th signal generation circuit 710, for example, the input terminal IP and the (i+1)th gate line G _i+1 supplying the (i+1)th gate signal g _i+1 (hereinafter referred to as "input signal") is connected (FIG. 1), and the output terminal OP is connected to the i-th storage electrode line S _i that outputs the i-th storage signal V _sl . Similarly, in the (i+1)th signal generating circuit 710, for example, the input terminal IP is connected to the (i+2)th gate signal g _i+2 (not shown) supplied as the input signal. The gate line G _i+2 is connected, and the output terminal OP is connected to the (i+1)th storage electrode line S _i+1 outputting the (i+1)th storage signal V _sl+1 (not shown).

The first clock signal CK1, the second clock signal CK1B, and the third clock signal CK2 of the storage control signal CONT3 from the signal controller 600 (FIG. 1) are supplied to the signal generation circuit 710, and the signal controller 600 or an external device High voltage AVDD and low voltage AVSS (not shown) are supplied to the signal generation circuit 710 .

As shown in FIG. 4 , the periods of the first clock signal CK1 , the second clock signal CK1B and the third clock signal CK2 may be about 2H, and their duty ratios may be about 50%, but not limited thereto. The first clock signal CK1 and the second clock signal ^CK1B have a phase difference of about 180° and are mutually inverse. In contrast, the second clock signal CK1B and the third clock signal CK2 have substantially the same phase. In addition, as shown in FIG. 4, each phase of the first clock signal CK1, the second clock signal CK1B, and the third clock signal CK2 is inverted in each respective subsequent frame.

The first clock signal CK1 and the second clock signal CK1B may have a first high-level voltage Vh1 of, for example, about 15V, and a first low-level voltage Vl1 of, for example, about 0V. The third clock signal CK2 may have a second high-level voltage Vh2 of, for example, about 5V, and a second low-level voltage Vl2 of, for example, about 0V. The high voltage AVDD may be, for example, about 5V, and may be about equal to the second high level voltage Vh2 of the third clock signal CK2. The low voltage AVSS may be, for example, about 0V, and may be about equal to the second low level voltage V12 of the third clock signal CK2.

The signal generation circuit 710 includes first to fifth transistors Tr1 - Tr5 including a control terminal, an input terminal and an output terminal, respectively, and first and second capacitors C1 and C2 .

The control terminal of the first transistor Tr1 is connected to the input terminal IP, the input terminal of the transistor Tr1 is connected to the third clock signal CK2 , and the output terminal of the transistor Tr1 is connected to the output terminal OP.

The control terminals of the second transistor Tr2 and the third transistor Tr3 are connected to the input terminal IP, and the input terminals of the second transistor Tr2 and the third transistor Tr3 are respectively connected to the first clock signal CK1 and the second clock signal CK1B.

The control terminals of the fourth transistor Tr4 and the fifth transistor Tr5 are connected to the output terminals of the second transistor Tr2 and the third transistor Tr3 respectively, and the input terminals of the fourth transistor Tr4 and the fifth transistor Tr5 are respectively connected to the low voltage AVSS and the high voltage AVDD.

The first capacitor C1 and the second capacitor C2 are respectively connected between the control terminals of the fourth transistor Tr4 and the fifth transistor Tr5 and the low voltage AVSS and the high voltage AVDD.

In one exemplary embodiment, the first to fifth transistors Tr1 - Tr5 are formed of amorphous silicon ("a-Si") or polysilicon ("p-Si") TFTs, respectively.

The operation of the signal generating circuit 710 is now described in further detail.

Referring again to FIG. 4 , in general, the gate-on voltage Von is applied to each of two adjacent gate lines within a predetermined overlapping time period of, for example, about 1H (but not limited thereto). As a result, an image is displayed by charging all the pixels PX of a given row with the data voltage applied to the pixels of the previous row for about 1H, and then with the data voltage for the remaining 1H.

Now, the i-th signal generating circuit 710 is further described with reference to FIGS. 3 and 4 .

When the input signal (for example, the gate signal g _i+1 applied to the (i+1)th gate line G _i+ 1 ) changes to the gate-opening voltage Von, the first, second and third transistors Tr1-Tr3 are turned on respectively. Pass. The turned-on first transistor Tr1 transmits the third clock signal CK2 to the output terminal OP. As a result, the _i -th storage signal Vsi is at the second low-level voltage V12 of the third clock signal CK2. The turned-on second transistor Tr2 transmits the first clock signal CK1 to the control terminal of the fourth transistor Tr4, and the turned-on third transistor Tr3 transmits the second clock signal CK1B to the control terminal of the fifth transistor Tr5.

Since the first and second clock signals CK1 and CK1B have an inversion relationship, the fourth transistor Tr4 and the fifth transistor Tr5 are reverse-biased at a given time. For example, when the fourth transistor Tr4 is turned on, the fifth transistor Tr5 is turned off, and conversely, when the fourth transistor Tr4 is turned off, the fifth transistor Tr5 is turned on. And, when the fourth transistor Tr4 is turned on and the fifth transistor Tr5 is turned off, the low voltage AVSS is transmitted to the output terminal OP, and when the fourth transistor Tr4 is turned off and the fifth transistor Tr5 is turned on, the high voltage AVDD is transmitted to the output terminal OP .

As shown in FIG. 4, the gate signal gi ₊₁ is at the gate-on voltage Von for an interval of, for example, about 2H. And, a first period of about 1H is represented by a first period T1, and a second period of about 1H is represented by a subsequent period T2.

The first clock signal CK1 is at the first high-level voltage Vh1 in the first period T1, and the second clock signal and the third clock signal CK1B and CK2 are at the first and second low-level voltages Vl1 and vl2 respectively. , and supply the low voltage AVSS to the output terminal OP of the second low level voltage Vl2 transmitted to the third clock signal CK2 through the transistor Tr1. As a result, the storage signal _Vsi maintains the low-level storage signal voltage V- having a magnitude equal to the magnitude of the second low-level voltage V12 and the low voltage AVSS. During the first period T1, the voltage difference between the first high-level voltage Vh1 of the first clock signal CK1 and the low voltage AVSS is charged to the capacitor C1, and the first low-level voltage Vl1 of the second clock signal CK1B and The voltage difference between high voltage AVDD charges capacitor C2.

During the period T2, the first clock signal CK1 is kept at the first low-level voltage Vl1, and the second and third clock signals CK1B and CK2 are kept at the first and second high-level voltages Vh1 and Vh2, respectively, thereby The fifth transistor Tr5 is turned on and the fourth transistor Tr4 is turned off.

As a result, the second high-level voltage Vh2 of the third clock signal CK2 transmitted through the turned-on first transistor Tr1 is supplied to the output terminal OP, and the state of the storage signal V _si is stored from the low-level storage signal voltage V- Changes to the high-level storage signal voltage V+ having a magnitude equal to that of the second high-level voltage Vh2. In addition, a high voltage AVDD having an amplitude equal to the amplitude of the high-level storage signal voltage V+ applied by turning on the fifth transistor Tr5 is supplied to the output terminal OP.

Since the voltage charged to the capacitor C1 is approximately the same as the voltage difference between the first low-level voltage Vl1 of the first clock signal CK1 and the low voltage AVSS, when the first low-level voltage Vl1 of the first clock signal CK1 and the low voltage AVSS become into approximately the same, capacitor C1 discharges. Since the voltage charged to the capacitor C2 is based on the voltage difference between the first high-level voltage Vh1 of the second clock signal CK1B and the high voltage AVDD, when the first high-level voltage Vh1 and the high voltage AVDD are different from each other as described above, the charging The voltage to the capacitor C2 is not equal to 0V, where the first high level voltage Vh1 of the second clock signal CK1B is about 15V and the high voltage AVDD is about 5V. Therefore, the voltage charged to the capacitor C2 is about 10V.

When the i+1th stage of the gate signal g _i+1 changes from the gate-on voltage Von to the gate-off voltage Voff after a period T2 as shown in the figure, the first to third transistors Tr1-Tr3 are respectively turned off. As a result, the electrical connection between the first transistor Tr1 and the output terminal OP is separated, and the electrical connections between the control terminals of the fourth and fifth transistors Tr4 and Tr5 and the output terminal OP are also separated, respectively.

Since the capacitor C1 is not charged, the fourth transistor Tr4 remains in an off state. However, the voltage between the first high level voltage Vh1 of the second clock signal CK1B and the high voltage AVDD has been charged to the capacitor C2. Therefore, when the charging voltage of the capacitor C2 is greater than the threshold voltage of the fifth transistor Tr5, the transistor Tr5 is kept in the on state. As a result, the high voltage _AVDD is supplied to the output terminal OP as the storage signal Vsi. Thus, the storage signal V _si maintains the high-level storage signal voltage V+.

Next, the operation of the (i+1)th signal generation circuit 710 is described in further detail with reference to FIG. 4 .

When the (i+2)th gate signal g _i+2 having the gate opening voltage Von is applied to the (i+1)th signal generating circuit 710 (not shown), the (i+1)th signal generating circuit 710 starts to work .

As shown in Figure 4, when the (i+2)th gate signal g _i+2 is switched to the gate-on voltage Von, the states of the first, second and third clock signals CK1, CK1B and CK2 are reversed respectively, and the ( i+1) The gate signal g _i+1 is at the gate opening voltage Von.

The operation of the first gate-opening voltage period T1 of the (i+2)th gate signal g _i+2 is approximately the same as the operation of the next gate-opening voltage period T2 of the (i+1)th gate signal g _i+1 , so that the first, The third and fifth transistors Tr1, Tr3 and Tr5 are respectively turned on. Then, the second high level voltage Vh2 of the third clock signal CK2 and the high voltage AVDD are applied to the output terminal OP. As a result, the storage signal V _si+1 is at the high level storage signal voltage V+.

Similarly, the operation of the gate opening voltage period T2 of the (i+2)th gate signal g _i+2 is approximately the same as the operation of the previous gate opening voltage period T1 of the (i+1)th gate signal g _i + ₁ , causing the first , the second and fourth transistors Tr1, Tr2 and Tr4 are turned on respectively. Then, the second low level voltage V12 and the low voltage AVSS of the third clock signal CK2 are applied to the output terminal OP. As a result, the storage signal V _si+1 changes from the high-level storage signal voltage V+ to the low-level storage signal voltage V-.

As described above, the first transistor Tr1 can apply the third clock signal CK2 as a storage signal while the input signal maintains the gate-on voltage Von, and when the output terminal OP is separated from the output terminal of the first transistor Tr1 by the gate-off voltage Voff, using The first and second capacitors C1 and C2 respectively maintain the second to fifth transistors Tr2-Tr5 in a state of storing signals until the next frame. Also, the first transistor Tr1 may apply a storage signal to a corresponding storage electrode line, and the second to fifth transistors Tr2-Tr5 maintain the storage signal, respectively.

In one exemplary embodiment, the size of the first transistor Tr1 is much larger than the sizes of the second to fifth transistors Tr2-Tr5, respectively. As given by Equation 1, the pixel electrode voltage Vp changes in response to the voltage change of the storage signal _Vs.

Vp＝V _D +/-Δ＝V _D +/-C _st /(C _st +C _lc )*[(V+)-(V-)] (equation 1)

Among them: V _D is the data voltage; Δ is the amount of voltage change; C _lc and C _st represent the capacitance of the storage and liquid crystal capacitors, respectively; V+ represents the high-level storage signal voltage of the storage signal V _s ; and V- represents the storage signal V _s The low level storage signal voltage.

By adding the voltage variation Δ of the storage signal V _s to the data voltage V _D or subtracting the voltage variation Δ of the storage signal V _s from the data voltage V _D , when the pixel is charged with the positive data voltage, the pixel electrode The voltage Vp increases the voltage variation Δ, and conversely, when the pixel is charged with the data voltage of negative polarity, the pixel electrode voltage Vp decreases the voltage variation Δ. As a result, the pixel voltage voltage variation Δ increases or decreases the pixel electrode voltage Vp, so that the pixel voltage becomes larger than the range of the grayscale voltage, so that the range of the represented luminance is also increased.

Also, as described above, since the common voltage is fixed at a predetermined value, power consumption is effectively reduced compared to the related art LCD in which the common voltage alternates between a high value and a low value.

Therefore, according to an exemplary embodiment of the present invention, the common voltage is fixed at a predetermined value, and a storage signal whose level changes periodically is applied to the storage electrode line, so that the range of the pixel electrode voltage is increased. Accordingly, the range of voltages representing gray scale voltages increases, thereby improving the image quality of the LCD.

Also, as described above, power consumption is reduced due to the constant utility voltage.

Hereinafter, another exemplary embodiment of the present invention will be further described with reference to FIGS. 5-8B .

5 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention, and FIG. 6 is a schematic circuit diagram of a signal generating circuit of a storage signal generating circuit according to an exemplary embodiment of the present invention in FIG. 5 . 7A and 7B are signal timing diagrams of the signal generating circuit according to the exemplary embodiment of the present invention in FIG. 6 . More specifically, FIG. 7A is an example in the case where the scanning direction of the gate driver is the forward direction, and FIG. 7B is an example in the case where the scanning direction of the gate driver is the backward direction. 8A and 8B are signal timing diagrams of a signal generating circuit according to an alternative exemplary embodiment of the present invention. More specifically, FIG. BA is an example illustrating signal timing in the case where the scanning direction of the gate driver is the forward direction, and FIG. 8B is an example illustrating signal timing in the case where the scanning direction of the gate driver is the backward direction.

The LCD according to the exemplary embodiment of the present invention as shown in FIGS. 5 to 8B is approximately the same as the LCD shown in FIGS. 1 to 3 except for different parts described in further detail below. Therefore, elements performing the same or similar operations are marked with the same reference numerals, and any repeated description thereof will be omitted below.

The liquid crystal display according to the exemplary embodiment of the present invention as shown in FIG. controller 601 .

However, unlike the exemplary embodiment of the present invention shown in FIG. 1 , the gate driver 401 is a plurality of normal gate lines G ₁ -G _2n in which the scanning direction follows a selection signal (not shown) from an external device (not shown). ) and change the bidirectional gate driver. More specifically, depending on the state of the selection signal, the gate driver 401 moves along, for example, a forward direction from the first normal gate line _G1 to the last normal gate line _G2n , or vice versa, along a direction such as from the last normal gate line _G2n . To the backward direction of the first normal gate line _G1 , the gate-on voltage Von is sequentially transmitted. In the bidirectional driving of the gate driver 401, the liquid crystal display may further include a selection switch (not shown), which outputs a selection signal having a state that changes, for example, with a user's selection input to the signal controller 601, and, in addition to the above As described in more detail, the signal controller 601 can also control the The signal CONT1a outputs additional third and fourth scanning start signals STV3 and STV4 (not shown), respectively. Therefore, when the gate driver 410 scans in the forward direction, the first and second scan start signals STV1 and STV2 can be applied to the first and second gate driver circuits 401a and 401b, respectively, and when the gate driver 410 scans in the backward direction When scanning in the direction, the third and fourth scan start signals STV3 and STV4 may be applied to the first and second gate driving circuits 401a and 401b, respectively.

Each of the first and second storage signal generation circuits 701a and 701b of the storage signal generator 701 of the liquid crystal display according to an exemplary embodiment includes a plurality of signals for transmitting a storage signal to a plurality of storage electrode lines S ₁ -S _2n Generate circuit 710a. As shown in FIG. 6, each signal generating circuit 710a of a plurality of signal generating circuits 710a is similar to the signal generating circuit 710 shown in FIG. 3, for example, the signal generating circuit 710a includes an output terminal OP, first to fifth transistors Tr1-Tr5 and the first capacitor C1 and the second capacitor C2.

However, the signal generation circuit 710a of the exemplary embodiment in FIG. 6 further includes a first input terminal IP11 and a second input terminal IP12 and a first direction control terminal IP13 and a second direction control terminal IP14. In the i-th signal generating circuit 710a, the first input terminal IP11 is connected to the (i+1)th gate line G _i that supplies the (i+1)th gate signal g _i+1 (hereinafter referred to as "the first input signal") ₊₁ connection, and the second input terminal IP12 is connected to the (i-1)th gate line G _i-1 supplying the (i-1)th gate signal g _i-1 (hereinafter referred to as "second input signal"). Similarly, in the (i+1)th signal generating circuit 710a, the first input terminal IP11 is connected to the (i+2)th gate line G that supplies the (i+2)th gate signal g _i+2 as the first input signal _i+2 is connected, and the second input terminal IP12 is connected to the i-th gate line G _i supplying the i-th gate signal g _i as the second input signal.

Like the signal generating circuit 710 shown in FIG. 3, the first, second, and third clock signals CK1, CK1B, and CK2 of the memory control signal CONT3a from the signal controller 601 are supplied to the signal generating circuit 710a, respectively, and the High voltage AVDD and low voltage AVSS from the signal controller 601 or an external device (not shown) are supplied to the signal generating circuit 710a. The first direction signal DIR or DIRa and the second direction signal DIRB or DIRBa of the storage control signal CONT3a from the signal controller 610 are further supplied to the signal generating circuit 710a through the first direction control terminal IP13 and the second direction control terminal IP14, respectively. .

The signal generating circuit 710a further includes a sixth transistor Tr6 and a seventh transistor Tr7 each having a control terminal, an input terminal, and an output terminal.

As shown in Figure 6, the control terminal of the sixth transistor Tr6 is connected with the first direction control terminal IP13, the input terminal of the sixth transistor Tr6 is connected with the first input terminal IP11, and the output terminal of the sixth transistor Tr6 is respectively connected with the first to the first direction control terminal IP11. The control terminals of the third transistors Tr1-Tr3 are connected.

And, the control terminal of the seventh transistor Tr7 is connected with the second direction control terminal IP14, the input terminal of the seventh transistor Tr7 is connected with the second input terminal IP12, and the output terminal of the seventh transistor Tr7 is respectively connected with the first to the third transistor Tr1 - Tr3 control port connection.

In addition to the additional gate line _Gd , the liquid crystal display further includes a second additional gate line _Gda . The second additional gate line G _da is connected to one end of the second gate driving circuit 401b to transmit the gate-on voltage Von to the first storage signal generating circuit 701a after transmitting the gate signal _g1 .

In an exemplary embodiment, both the additional gate line G _da and the additional gate line G _d are not connected to the switching element Q. Referring to FIG.

An example of the operation of the signal generating circuit will be described in further detail with reference to FIGS. 7A and 7B.

As shown in Figures 7A and 7B, the first and second direction signals DIR and DIRB applied to the first and second direction control terminals IP13 and IP14 respectively maintain the third high level voltage Vh3 or the third The low-level voltage V13' and the first and second direction signals DIR and DIRB have phases opposite to each other, respectively. More specifically, when the first direction signal DIR has a third high-level voltage Vh3, the second direction signal DIRB has a third low-level voltage Vl3, and when the first direction signal DIR has a third low-level voltage Vl3 , the second direction signal DIRB has a third high level voltage Vh3. And, the third high-level voltage Vh3 of the first and second direction signals DIR and DIRB has a magnitude of turning on the sixth and seventh transistors Tr6 and Tr7, the magnitude of the third high-level voltage Vh3 may be, for example, about 15V, But not limited to this. The third low-level voltage V13 of the first and second direction signals DIR and DIRB has a magnitude that turns off the sixth and seventh transistors Tr6 and Tr7, and the magnitude of the third low-level voltage V13 may be, for example, about -10V, but Not limited to this.

Therefore, the sixth and seventh transistors Tr6 and Tr7 have opposite biases to each other at a given time, so that when the sixth transistor Tr6 is in the on state, the seventh transistor Tr7 is in the off state, and when the sixth transistor Tr6 is in the on state, the seventh transistor Tr7 is in the off state, and when the sixth transistor When Tr6 is in the off state, the seventh transistor Tr7 is in the on state.

In an alternative exemplary embodiment of the present invention, for example, the first and second direction signals DIR and DIRB may be output according to a selection signal, or may utilize a control signal controlling a scan direction of the gate driver 40, but are not limited thereto.

The operation of the signal generating circuit 710a is now described in further detail for the case where the scanning direction of the gate driver 401 is the forward direction.

Referring to FIGS. 6 and 7A, the first direction signal DIR is input to the first direction control terminal IP13 at the third high level voltage Vh3, and the second direction signal DIRB is input to the second direction at the third low level voltage Vl3. Control terminal IP14.

Accordingly, the sixth transistor Tr6 is turned on and the seventh transistor Tr7 is turned off, thereby operating the signal generation circuit 710a according to the first input signal applied to the first input terminal IP11, for example, the gate signal g _i+1 . More specifically, when the signal generation circuit 710a is operated like the i-th signal generation circuit 710a, the gate opening by the gate signal g _i+1 applied to the (i+1)th gate line G _i+1 ( FIG. 1 ) The voltage Von operates the i-th signal generating circuit 710a. Therefore, as described above with reference to FIGS. 3 and 4 , the storage signal V _si having a predetermined level is output through operations of the first to fifth transistors Tr1 - Tr5 and the first and second capacitors C1 and C2 .

Similarly, when the scanning direction of the gate driver 401 is the backward direction, as shown in FIG. 7B, the first direction signal DIR is at the third low level voltage V13, and the second direction signal DIRB is at the third high level Voltage Vh3.

Therefore, the sixth transistor Tr6 is turned off and the seventh transistor Tr7 is turned on, thereby operating the signal generation circuit 710a by the second input signal applied to the second input terminal IP12, eg, the gate signal g _i−1 . More specifically, when the signal generation circuit 710a is operated like the i-1th signal generation circuit 710a, by the gate signal g _i-1 applied to the (i-1)th gate line G _i-1 ( FIG. 1 ) The gate opening voltage Von operates the i-th signal generation circuit 710a. Therefore, as described above with reference to FIGS. 3 and 4 , the storage signal V _si having a predetermined level is output through operations of the first to fifth transistors Tr1 - Tr5 and the first and second capacitors C1 and C2 .

Instead of directly supplying the input signal to the signal generating circuit 710 ( FIG. 3 ) through the input terminal IP, the first to third transistors Tr1-Tr3 are respectively turned on. As shown in the figure, when the scanning direction is the forward direction, the sixth transistor T6 supplies the gate signal to the signal generating circuit 710a as input signals respectively applied to the control terminals of the first to third transistors Tr1-Tr3, and when the scanning direction is the backward direction, the gate signal is supplied to The signal generation circuit 710a serves as input signals applied to the control terminals of the first to third transistors Tr1-Tr3, respectively. Operations of the first to fifth transistors Tr1 - Tr5 and the first and second capacitors C1 and C2 are respectively the same as those of the signal generating circuit 710 described in further detail above with reference to FIG. 3 .

The operation of the signal generation circuit 710a according to an alternative exemplary embodiment of the present invention will now be described in further detail with reference to FIGS. 8A and 8B.

As shown in Figures 8A and 8B, the first direction signal DIRa and the second direction signal DIRBa are applied to the first and second direction control terminals IP13 and IP14 respectively, and have a third high level voltage Vh3 and a third low level voltage respectively. Flat voltage Vl3. And, each of the third high-level voltage Vh3 and the third low-level voltage Vl3 remains unchanged for about 1H, and their duty ratios may be about 50%. More specifically, the first direction signal DIRa and the second direction signal DIRBa alternate between the third high-level voltage Vh3 and the third low-level voltage Vl3 every about 1H. Also, the first direction signal DIRa and the second direction signal ^DIRBa have a phase difference of about 180° and are mutually inverse.

As described above, the third high-level voltage Vh3 of the first direction signal DIRa and the second direction signal DIRBa may be, for example, about 15V, and their third low-level voltage Vl3 may be, for example, about -10V.

For each row, the first direction signal DIRa and the second direction signal DIRBa are respectively alternately supplied to the first direction control terminal IP13 and the second direction control terminal IP14 of the signal generating circuit 710a. More specifically, in the signal generation circuit 710a connected to the odd-numbered storage electrode lines S1, S3, ..., S2n _{- 1} , the first direction signal _DIRa is supplied to the first direction control terminal IP13, and The second direction signal DIRBa is supplied to the second direction control terminal IP14. On the contrary, in the signal generating circuit 710a connected to the even _- numbered storage electrode lines S2, S4, ..., S2n, the _second direction signal _DIRBa is supplied to the first direction control terminal IP13, and the first direction signal DIRa is supplied to the second direction control terminal IP14.

Now for the case where the scanning direction of the gate driver 401 is the forward direction, the operation of the signal generation circuit 710a is described in further detail with reference to FIGS. 6 and 8B.

In the odd-numbered signal generation circuit 710a, for example, the i-th signal generation circuit 710a, when the gate-on voltage Von of the (i+1)th gate signal g _i+1 as the first input signal is supplied to the first input terminal IP11, When the gate-off voltage Voff of the (i-1)th gate signal g _i-1 as the second input signal is supplied to the second input terminal IP12, the first direction signal DIRa is supplied as the first direction signal to the first direction control terminal IP13, and supplies the second direction signal DIRBa as the second direction signal to the second direction control terminal IP14.

In the first period T1 of the gate-on voltage Von of the gate signal g _i+1 , the first direction signal DIRa is at the third low level voltage Vl3 and the second direction signal DIRBa is at the third high level voltage Vh3, Thus, the sixth transistor Tr6 is turned off, and the seventh transistor Tr7 is turned on. And, the second input signal is the gate-off voltage Voff, therefore, the first to third transistors Tr1-Tr3 are respectively turned off, so that the storage signal _Vsi is kept at the low-level storage signal voltage V- as shown in FIG. 8A, for example. the previous voltage state.

After about 1H, for example, within the period T2 of the gate-on voltage Von of the gate signal g _i+1 , the first direction signal DIRa changes from the third low-level voltage Vl3 to the third high-level voltage Vh3, while the second direction The signal DIRBa changes from the third high-level voltage Vh3 to the third low-level voltage Vl3.

Therefore, the sixth transistor Tr6 is turned on in the period T2 of the gate-opening voltage Von of the gate signal g _i+1 , and transmits the gate-opening voltage Von to the control terminals of the first to third transistors Tr1-Tr3, turning on the first to the third transistors Tr1-Tr3 Three transistors Tr1-Tr3.

As described above with reference to FIGS. 3 and 4, the first clock signal CK1 is at the first low level voltage Vl1 during the period T2, while the second and third clock signals CK1B and CK2 are at the first high level voltage respectively. Leveling voltages Vh1 and Vh2. Accordingly, the second high level voltage Vh2 of the third clock signal CK2 and the high voltage AVDD are transmitted to the output terminal OP. Accordingly, the storage signal V _si is changed from the low-level storage signal voltage V− to the high-level storage signal voltage V+, and the second capacitor C2 is charged.

When the first direction signal DIRa changes to the third low level voltage V13 after the period T2 elapses, the sixth transistor Tr6 is turned off. However, the transistor Tr5 is kept in the on state by being charged to the voltage of the second capacitor C2, thereby still delivering the high voltage AVDD to the output terminal OP, so that the storage signal _Vsi maintains a high level storage signal voltage V+.

Next, the operation of the even-numbered signal generating circuit 710a, for example, the (i+1)th signal generating circuit 710a is described in further detail.

Still referring to FIGS. 6 and 8A, in the (i+1)th signal generating circuit 710a, when the gate opening voltage Von of the (i+2)th gate signal g _i+2 as the first input signal is supplied to the first input terminal IP11, and when the gate-off voltage Voff of the i-th gate signal g _i as the second input signal is supplied to the second input terminal IP12, the second direction signal DIRBa is supplied to the first direction control terminal IP13 as the first direction signal, and The first direction signal DIRa is supplied to the second direction control terminal IP14 as the second direction signal.

Since the first direction signal DIRBa is at the third low level voltage Vl3 and the second direction signal DIRa is at the third high level voltage Vh3 in the first period T1 of the gate opening voltage Von of the gate signal g _i+1 , the sixth transistor Tr6 is turned off, and the seventh transistor Tr7 is turned on. The second input signal is the off-gate voltage Voff, and the first to third transistors Tr1-Tr3 are respectively turned off, so that the storage signal _Vsi remains in a previous voltage state like, for example, a high-level storage signal voltage V+.

After about 1H, for example, within the period T2 of the gate-on voltage Von of the gate signal g _i+2 , the first direction signal DIRBa changes from the third low-level voltage Vl3 to the third high-level voltage Vh3, and the second direction The signal DIRa changes from the third high-level voltage Vh3 to the third low-level voltage Vl3.

Therefore, the sixth transistor Tr6 is turned on in the period T2 of the gate-opening voltage Von of the gate signal g _i+2 , and transmits the gate-opening voltage Von to the control terminals of the first to third transistors Tr1-Tr3, turning on the first to the third transistors Tr1-Tr3 Three transistors Tr1-Tr3.

As described above with reference to FIGS. 3 and 4, the first clock signal CK1 is at the first high-level voltage Vh1, and the second and third clock signals CK1B and CK2 are respectively at the first low-level voltage Vl1 and Vl2, so that the low level voltage Vl2 and the low voltage AVSS of the third clock signal CK2 are transmitted to the output terminal OP. Accordingly, the storage signal V _si+1 is changed from the high-level storage signal voltage V+ to the low-level storage signal voltage V−, and the first capacitor C1 is charged.

When the first direction signal DIRBa changes to the third low level voltage V13 after the period T2 has elapsed, the sixth transistor Tr6 is turned off. However, the fourth transistor Tr4 is kept in the on state by being charged to the voltage of the first capacitor C1, thereby still delivering the low voltage AVSS to the output terminal OP, and the storage signal V _si+1 is kept at the low level storage signal voltage V- superior.

Hereinafter, the operation of the signal generating circuit 710a will be described in further detail with reference to FIG. 8B in which the scanning direction of the gate driver 401 is the backward direction. In this case, the waveforms of the direction signals DIRa and DIRBa are opposite to those of the forward direction described above with reference to FIG. 8A.

Referring to FIGS. 6 and 8B, in the period 1H of the gate-on voltage Von of the corresponding gate signal applied to the second input terminal IP12 as the second input signal, for example, in the subsequent period T2 of the above-mentioned period T2, the transistor Tr7 is turned on, The first to third transistors Tr1-Tr3 are also turned on respectively. More specifically, the first to fifth transistors Tr1-Tr5 and the first and second capacitors C1 and C2 are operated according to the states of the first to third clock signals CK1, CK1B, and CK2 to transmit storage signals to corresponding storage electrode lines . Operations of the first to fifth transistors Tr1-Tr5 and the first and second capacitors C1 and C2 are approximately the same as in the case where the scanning direction of the gate driver is the forward direction as described above, so their descriptions are omitted here.

As mentioned above, in the exemplary embodiment of the present invention, the first and second direction signals DIRa and DIRBa are applied to the first and second direction control terminals IP13 and IP14, respectively. And, the first and second direction signals DIRa and DIRBa alternate between the third high-level voltage Vh3 and the third low-level voltage Vl3 every 1H. Therefore, the operating characteristics of the transistor will not change due to the long-term application of the direction signals DIRa and DIRBa and the resulting element degradation.

The signals shown in the timing charts of FIGS. 8A and 8B can also be applied to liquid crystal displays including amorphous thin film transistors in addition to polycrystalline thin film transistors.

In one exemplary embodiment, the gate driver 401 is a bidirectional gate driver, and one of the first to fourth scan start signals STV1 and STV4 may be applied to the signal generation circuit 710a supplying the gate signal in a scan direction.

Hereinafter, a liquid crystal display according to an alternative exemplary embodiment of the present invention will be described in further detail with reference to FIGS. 9-13B.

9 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention, FIG. 10 is a schematic circuit diagram of a signal generating circuit according to an exemplary embodiment of the present invention in FIG. 9 , and FIG. A plan layout diagram of a signal generating circuit of an exemplary embodiment of the present invention. 12 is a signal timing diagram illustrating a relationship between a gate clock signal applied to a gate driver and a storage clock signal applied to a storage signal generator according to one embodiment of the present invention. 13A and 13B are signal timing diagrams of the signal generating circuit according to the exemplary embodiment of the present invention in FIG. The scan direction of the driver is an example of signal timing in the backward direction.

The LCD according to the exemplary embodiment of the present invention as shown in FIGS. 9-13B is approximately the same as the LCD shown in FIGS. 1 to 6 except for the different parts described in further detail below. Therefore, elements performing the same or similar operations are denoted by the same reference numerals, and any repeated description thereof will be omitted below.

Referring to FIG. 9 , the LCD includes a liquid crystal panel assembly 300 b , a gate driver 402 , a data driver 500 , a grayscale voltage generator 800 connected to the data driver 500 , a storage signal generator 702 and a signal controller 602 .

As with the LCD described in more detail above and shown in FIG. 5, the gate driver 402 is a bidirectional gate driver.

The first and second storage signal generating circuits 702a and 702b of the storage signal generator 702 may respectively include a plurality of signal generating circuits 710b connected to storage electrode lines S ₁ -S _2n , and each signal generating circuit 710b is connected to The signal generating circuit 710a shown in 6 is similar.

As shown in FIG. 10, the signal generation circuit 710b includes an output terminal OP, first to fifth transistors Tr1-Tr5, and first and second capacitors C1 and C2.

The signal generation circuit 710b further includes an input terminal IP21 and a control terminal OP22. In the i-th signal generating circuit 710b, for example, the input terminal IP21 is connected to the _i -th gate line Gi supplying the i-th gate signal g _i as the first input signal, similarly, the (i+1)th signal generating circuit 710b , the input terminal IP21 is connected to the (i+1)th gate line G _i+1 supplying the (i+1)th gate signal g _i+1 as the first input signal.

The first, second, and third clock signals CK1, CK1B, and CK2 of the storage control signal CONT3 from the signal controller 602 are respectively supplied to the signal generation circuit 710b, and are supplied from the signal controller 602 or an external device (not shown) The high voltage AVDD and low voltage AVSS are supplied to the signal generation circuit 710b.

One of a plurality of storage clock signals CLK_L (eg, as shown in FIG. 10 ), CLK_R, CLKB_L, and CLKB_R from the storage control signal CONT3 of the signal controller 602 is further supplied to the signal generation circuit 710 b through the control terminal IP22 .

As shown in FIGS. 9 and 11, the signal generation circuit 710b of the first storage signal generation circuit 702a is located on the left side of the liquid crystal panel assembly 300b and generates even-numbered storage signals V _s2 , V _s4 , . . _. The memory clock signals CLK_L and CLKB_L of the plurality of memory clock signals CLK_L, CLK_R, CLKB_L, and CLKB_R applied to the left side of the liquid crystal panel assembly 300b are alternately supplied to the signal generating circuit 710b. The signal generation circuit 710b of the second storage signal generation circuit 702b is located on the relative right side of the liquid crystal panel assembly 300b and generates odd-numbered storage signals V _s1 , V _s3 , ..., V _s2n-1 , and will generate The memory clock signals CLKB_R and CLK_L of the plurality of memory clock signals CLK_L, CLK_R, CLKB_L, and CLKB_R applied on the right side are alternately supplied to the signal generation circuit 710b.

In an alternative exemplary embodiment of the present invention, the positions of the first and second storage signal generating circuits 702a and 702b on the liquid crystal panel assembly 300b, the positions of the first and second storage signal generating circuits 702a and 702b and the storage electrodes can be changed. The connection relationship between the lines and the operational relationship of the first and second storage signal generating circuits 702a and 702b and the plurality of storage clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R.

Also, in an alternative exemplary embodiment, the plurality of storage clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R may be related to the gate control signal CONT1 that generates the gate signal, and may be based on the gate clock applied to the gate driving circuits 402a and 402b Signal generation.

An example of a gate clock signal and a store clock signal according to an exemplary embodiment of the present invention is shown in FIG. 12 .

FIG. 12 shows that when the scanning direction of the gate driver 402 is the forward direction, when the gate clock signals GCK_L, GCK_R, GCKB_L and GCKB_R are applied to generate the i-th, (i+1), (i+2) and When the (i+3)th gate signals g _i , g _i+1 , g _i+2 and g _i+3 are the first and second gate drive circuits 402a and 402b, a plurality of storage clock signals CLK_L, CLKB_R, CLKB_L and _{CLK_R} is _{applied on} the _first and storage clock signals CLK_L, CLKB_R, CLKB_L and CLK_R on the second storage signal generating circuits 702a and 702b.

However, when the scanning direction of the gate driver 402 is the backward direction, the gate clock signals GCK_L, GCK_R, GCKB_L and GCKB_R in FIG. 12 can generate the (i+3), (i+2), (i +1) and i-th gate signals g _i+3 , g _i+2 , g _i+1 and g _i signals, and storage clock signals CLK_L, CLKB_R, CLKB_L and CLK_R can be applied to the first and second storage signal generation On the circuits 702a and 702b, respectively generate the (i+3), (i+2), (i+1) and i-th storage signals S _i+3 , S _i+2 , S _i+1 and S _i .

The pulse widths of the storage clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R may be about 2H, and their duty ratios may be about 50%. The memory clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R oscillate every approximately 2H. As shown in FIG. 12 , each of the two corresponding memory clock signals CLK_R and CLKB_R or CLK_L and CLKB_L has a waveform of opposite phase. There is a predetermined time delay between each of the corresponding memory clock signals CLK_R and CLKB_R and the memory clock signals CLK_L and CLKB_L corresponding to the memory clock signals CLK_R and CLKB_R. In an exemplary embodiment, the delay time may be, for example, about 1H, but is not limited thereto. The storage clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R have a fourth high-level voltage Vh4 and a fourth low-level voltage Vl4 ( FIG. 13A ). For example, the high-level voltage Vh4 may be about 15V, and the low-level voltage V14 may be about -1V, but not limited thereto.

The signal generation circuit 710b further includes an alternative sixth transistor Tr61 and an alternative seventh transistor Tr71 each having a control terminal, an input terminal and an output terminal.

The input and control terminals of the alternative sixth transistor Tr61 are connected to the input terminal IP21, and the output terminals of the alternative sixth transistor Tr61 are connected to the control terminals of the first to third transistors Tr1-Tr3, so that the alternative sixth transistor Tr61 Effectively acts as a diode.

The control terminal of the seventh transistor Tr71 can be replaced with the control terminal IP22, the input terminal of the seventh transistor Tr71 can be replaced with the input terminal IP21, and the output terminal of the seventh transistor Tr71 can be replaced with the first to third transistors Tr1-Tr3 control terminal connection.

The signal generating circuit 710b will now be described in further detail with reference to FIG. 13A, wherein the scanning direction of the gate driver 402 is the forward direction.

When the gate-on voltage Von of the _i -th gate signal gi is supplied to the signal generating circuit 710b, for example, the input terminal IP21 of the i-th signal generating circuit 710b connected to the even-numbered storage line, the alternative sixth transistor Tr61 is turned on, and The first to third transistors Tr1-Tr3 are also turned on.

Therefore, for the application of the gate-on voltage Von of the _i -th gate signal gi, signals having voltage levels based on the respective states of the first to third clock signals CK1, CK1B, and CK2 are transmitted to the output terminal OP and stored as the signal V _si output.

In the first period T1 of the gate-on voltage Von of the gate signal _gi , the first clock signal CK1 is at the first low-level voltage Vl1, and the second and third clock signals CK1B and CK2 are respectively at the first and second A storage signal V _si with a high level storage signal voltage V+ is output from the output terminal OP on two high level voltages Vh1 and Vh2 and through the operations of the first, third and fifth transistors Tr1 , Tr3 and Tr5 .

However, since the first clock signal CK1 changes to the first high-level voltage Vh1 during the period T2 of the gate-on voltage Von of the gate signal _gi , and the second and third clock signals CK1B and CK2 change to the first and second Two low-level voltages Vl1 and Vl2, through the operation of the first, second and fourth transistors Tr1, Tr2 and Tr4, the storage signal V _si with the low-level storage signal voltage V- is transmitted to the output terminal OP, so that the storage The signal _Vsi changes from a high-level storage signal voltage V+ to a low-level storage signal voltage V-.

After the period T2, the gate signal _gi changes to the off-gate voltage Voff, thereby turning off the alternative sixth transistor Tr61 which functions as a diode. As a result, the voltage VNi of the node N (FIG. 10) to which the output terminal of each of the alternative sixth transistor and the alternative seventh transistor Tr61 and _Tr71 is connected maintains the previous high level state, causing the first to third The transistors Tr1 - Tr3 are kept on until the storage clock signal CLK_L applied to the control terminal IP22 changes to the fourth high level voltage Vh4 again. The voltage level of the storage signal Vsi is determined according to the voltage levels of the first to third clock signals CK1, _CK1B , and CK2. More specifically, the first clock signal CK1 is changed to a first low-level voltage Vl1, and the second and third clock signals CK1B and CK2 are changed to first and second high-level voltages Vh1 and Vh2, respectively, thereby according to the first 1. The third and fifth transistors Tr1, Tr3 and Tr5 transmit the high-level storage signal voltage V+ to the output terminal OP according to the operation of the first, second and third clock signals CK1, CK1B and CK2, so that the storage signal V _si changes from a low-level stored signal voltage V- to a high-level stored signal voltage V+, which is output from the output terminal OP.

After the predetermined time has elapsed, when the storage clock signal CLK_L applied to the control terminal IP22 is at the fourth high-level voltage Vh4, it can replace the seventh transistor Tr71 to be turned on, thereby applying the off-gate voltage Voff of the gate signal g _i On the control terminals of the first to third transistors Tr1-Tr3. Therefore, each of the first to third transistors Tr1-Tr3 is turned off. Then, the storage signal V _si maintains the high-level storage signal voltage V+ in the next frame according to the voltage charged to the capacitor C2 and the operation of the fifth transistor Tr5 according to the charging voltage.

Next, the operation of the signal generation circuit 710 b is described for the (i+1)th signal generation circuit 710 b connected to the (i+1)th connection to the odd-numbered storage line.

Still referring to FIGS. 10 and 13A, when the gate opening voltage Von of the (i+1)th gate signal g _i+1 is supplied to the input terminal IP21, the alternative sixth transistor Tr61 is turned on, and the first to third transistors Tr1- Tr3 is also turned on.

Therefore, for the application of the gate-on voltage Von of the (i+1)th gate signal g _i+1 , a signal having a voltage level based on the states of the first to third clock signals CK1, CK1B, and CK2 is transmitted to the output terminal OP and are output as storage signal V _si+1 .

In the first period T1 of the gate-on voltage Von of the gate signal g _i+1 , the first clock signal CK1 is at the first high-level voltage Vh1, and the second and third clock signals CK1B and CK2 are respectively at the first and the second low-level voltage Vl1 and Vl2, and through the operation of the first, second and fourth transistors Tr1, Tr2 and Tr4, the storage signal V _si+ with the low-level storage signal voltage V- is output from the output terminal OP ₂ .

However, within the period T2 of the gate-on voltage Von of the gate signal g _i+1 , the first clock signal CK1 changes to the first low-level voltage Vl1, and the second and third clock signals CK1B and CK2 change to the first and The second high-level voltages Vh1 and Vh2, and the storage signal _Vsi+1 having the high-level storage signal voltage V+ are transmitted to the output terminal OP through operations of the first, second and fourth transistors Tr1, Tr2 and Tr4. Accordingly, the storage signal V _si+1 changes from the low-level storage signal voltage V− to the high-level storage signal voltage V+ and is output from the output terminal OP.

After the period T2, the gate signal g _i+1 changes to the gate-off voltage Voff, but before the storage clock signal CLKB_R applied to the direct control terminal IP22 changes to the fourth high-level voltage Vh4, the voltage VN _i+1 of the node N It does not change to the previous low-level state Vl5, but remains in the high-level state Vh5 through the operation of the alternative sixth transistor Tr61, which acts as a diode, so that the first to third transistors Tr1-Tr3 remain in the on-state . Therefore, since the first clock signal CK1 is at the first high-level voltage Vh1, and the second and third clock signals CK1B and CK2 are at the first and second low-level voltages Vl1 and Vl2 respectively, through the first and second The operation of the second and fourth transistors Tr1 , Tr2 and Tr4 transmits the low-level storage signal voltage V− to the output terminal IP as storage signal V _si+1 . As a result, the storage signal V _si+1 changes again from the high-level storage signal voltage V+ to the low-level storage signal voltage V-.

After the predetermined time has elapsed, when the storage clock signal CLKB_R applied to the control terminal IP22 changes to the fourth high-level voltage Vh4, the alternative seventh transistor Tr71 is turned on, and the gate signal g _i+ of the gate-off voltage Voff is turned on. ₁ is applied to the control terminals of the first to third transistors Tr1-Tr3 to turn off the first to third transistors Tr1-Tr3. Therefore, the storage signal V _si+1 is maintained at the low level storage signal voltage V− until the next frame according to the charging voltage of the capacitor C1 and the operation of the fourth transistor Tr4 .

Hereinafter, the operation of the signal generating circuit 710b will be described in further detail with reference to FIG. 13B, in which the scanning direction of the gate driver 402 is the backward direction.

As shown in FIG. 13B , except for the respective gate signals applied to the input terminal IP21, the operation of the signal generation circuit 710b is approximately the same as that described above with reference to FIG. 13A when the scanning direction of the gate driver 402 is the forward direction. The operation of the circuit 710b is the same, therefore, any repeated description of them will be omitted here.

According to the exemplary embodiment of the present invention as described above, in the time period of about 1H of the first period T1 of the gate-on voltage Von, the corresponding level of the third clock signal CK2 is output as the storage signal, but due to the response of the liquid crystal display The speed is slower than the time period 1H, and the change of the storage signal for about 1H will not cause obvious changes of the pixel electrode lines.

Moreover, the storage clock signals CLK_L, CLKB_L, CLK_R, and CLKB_R applied to the control terminal IP22 of the signal generating circuit 710b shown in FIG. 10 determine the voltage level on the node N according to the gate-off voltage Voff, so that the The voltage level does not change during the time period of about 1H in which the first to third clock signals CK1, CK1B, and CK2 change, thereby maintaining the voltage level of the storage signal with an appropriate amplitude level until the next frame.

Therefore, in the storage signal generator 702 of the LCD according to an exemplary embodiment of the present invention, the gate lines transmitting additional gate signals other than the normal gate lines G ₁ -G _2n are redundant, and the AND gate driver 402 is not required. A discrete direction signal corresponding to the scan direction.

An LCD according to another exemplary embodiment of the present invention will now be described in further detail with reference to FIGS. 14 to 17B.

FIG. 14 is a block diagram of a liquid crystal display according to another exemplary embodiment of the present invention. 15 is a schematic circuit diagram of a signal generating circuit according to the exemplary embodiment of the present invention in FIG. 14, and FIG. 16 is a plan layout view of the signal generating circuit according to the exemplary embodiment of the present invention in FIG. 17A is a signal timing diagram of a signal generating circuit according to the exemplary embodiment of the present invention in FIG. 15 using row inversion, and FIG. 17B is a signal according to the exemplary embodiment of the present invention in FIG. 15 using frame inversion. Generate a signal timing diagram for the circuit.

Except for the different parts described in further detail below, the LCD according to the exemplary embodiment of the present invention as shown in FIGS. 14-17B is approximately the same as the LCD of the exemplary embodiment described in more detail above. Therefore, elements performing the same or similar operations as those in the above-described exemplary embodiments are denoted by the same reference numerals in FIGS. 14 to 17B , and any repeated description thereof will be omitted below.

As shown in FIG. 14, the LCD includes a liquid crystal panel assembly 300c, a gate driver 403, a data driver 500, a grayscale voltage generator 800 connected to the data driver 500, a storage signal generator 703, and a signal controller 603 for controlling the above elements.

As shown in FIG. 9, the gate driver 403 is a bidirectional gate driver.

The storage signal generator 703 includes first and second storage signal generating circuits 703a and 703b. Each of the first and second storage signal generation circuits 703a and 703b includes a plurality of signal generation circuits 710c each connected to a plurality of storage electrode lines S ₁ -S _2n ( FIG. 1 ).

Each signal generating circuit 710c is approximately the same as that shown in FIG. 10, for example, as shown in FIG. One to fifth transistors Tr1-Tr5 and first and second capacitors C1 and C2.

However, each signal generating circuit 710c further includes a first input terminal IP31 and a second input terminal IP32 and a control terminal IP41.

Referring to FIG. 15, in the i-th signal generation circuit 710c, the first input terminal IP31 is connected to the (i+2)th gate line G _i+2 that supplies the (i+2)th gate signal g _i+2 , and the second The input terminal IP32 is connected to the (i-2)th gate line G _i-2 to which the (i-2)th gate signal g _i-2 is supplied.

Similarly, in the (i+1)th signal generating circuit 710c, the first input terminal IP31 is connected to the (i+3)th gate line G _i+3 supplying the (i+3)th gate signal g _i+3 , And the second input terminal IP32 is connected to the (i-1)th gate line G _i-1 supplying the (i-1)th gate signal g _i-1 .

As shown in FIG. 16, the second input terminal IP32 of each first signal generating circuit 710c of the first and second storage signal generating circuits 703a and 703b receives the first scan voltage applied to the adjacent gate driving circuits 403a and 403b respectively. The start signal STV1 and the third scan start signal STV3, and the second scan start signal STV2 and the fourth scan start signal STV4 applied to the adjacent gate drive circuits 403a and 403b are supplied to the first and second storage signal generation circuits 703a and the first input terminal IP31 of the final signal generating circuit 710c of 703b. However, in an alternative exemplary embodiment, for example, separate signals from an external device (not shown) may be supplied to the first and second storage signal generation circuits 703a and 703b through separate signal lines such as dummy signal lines. The first and second input terminals IP31 and IP32 of the first and last signal generating circuit 710c, but not limited thereto.

The first, second, and third clock signals CK1, CK1B, and CK2 of the storage control signal CONT3 from the signal controller 603 are respectively supplied to the signal generating circuit 710c, and are supplied from the signal controller 603 or an external device (not shown) The high voltage AVDD and low voltage AVSS are supplied to the signal generating circuit 710c.

Still referring to FIG. 16 , one of a plurality of gate clock signals GCK_L, GCK_R, GCKB_L, and GCKB_R from the gate control signal ( FIG. 14 ) CONT1 of the signal controller 603 is also supplied to each signal generation circuit 710 c through the control terminal IP41 .

Referring back to FIG. 15, the signal generation circuit 710c further includes eighth to tenth transistors Tr8-Tr10 each having a control terminal, an input terminal, and an output terminal.

The control end of the eighth transistor Tr8 is connected to the first input end IP31, the input end of the eighth transistor Tr8 is connected to the first direction signal DIR of the storage control signal CONT3a, and the output end of the eighth transistor Tr8 is connected to the first to third transistors The control end connection of Tr1-Tr3.

The control terminal of the ninth transistor Tr9 is connected to the second input terminal IP32, the input terminal of the ninth transistor Tr9 is connected to the second direction signal DIRB of the storage control signal CONT3a, and the output terminal of the ninth transistor Tr9 is connected to the first to third transistors The control end connection of Tr1-Tr3.

The control terminal of the tenth transistor Tr10 is connected to the control terminal IP41, the input terminal of the tenth transistor Tr10 is connected to the gate-off voltage Voff, and the output terminal of the tenth transistor Tr10 is connected to the control terminals of the first to third transistors Tr1-Tr3.

The operation of the first and second storage signal generating circuits 703a and 703b each including a signal generating circuit 710c will be described in further detail below. Just for the sake of illustration, the inversion type of the LCD described is row inversion.

The scanning direction of the gate driver 403 is the forward direction, so that the first direction signal DIR has a high-level voltage and the second direction signal DIRB has a low-level voltage, and the operation of the signal generating circuit 710c will be described with reference to FIG. 17A .

Also, the operation of the signal generation circuit 710c, eg, the i-th signal generation circuit connected to the i-th storage electrode line S _i that is an odd-numbered storage electrode line, will be described with reference to FIGS. 15 and 17A.

After the gate-opening voltage Von of the i-th gate signal g _i is applied, the gate-opening voltage Von of the (i+2)th gate signal g _i+2 is applied to the input terminal IP31, thereby turning on the eighth transistor Tr8, therefore, the The third high-level voltage Vh3 of the one-direction signal DIR is applied to the control terminals of the first to third transistors Tr1-Tr3 through the node N1 to turn on the first to third transistors Tr1-Tr3.

Therefore, as shown in FIG. 17A , within about 2H of the gate-on voltage Von of the (i+2)th gate signal g _i+2 being applied, based on the voltage levels of the first to third clock signals CK1 , CK1B, and CK2 The corresponding voltage level is output to the output terminal OP as the storage signal V _si . At this time, since the (i-2)th gate signal g _i-2 maintains the on-off voltage Voff, the ninth transistor Tr9 is turned off, and the second direction signal DIRB does not affect the voltage VN1 of the node N1.

Therefore, in the first period T1 of the opening voltage Von of the (i+2)th gate signal g _i+2 , through the operations of the first, second and fourth transistors Tr1, Tr2 and Tr4, the output from the output terminal OP The storage signal V _si at the low level storage signal voltage V-. In the period T2 of the opening voltage Von of the (i+2)th gate signal g _i+2 , through the operation of the first, third and fifth transistors Tr1, Tr3 and Tr5, the output from the output terminal OP is at a high level Store signal V _si at store signal voltage V+.

Still referring to FIG. 17A, after the period T2 of the opening voltage Von of the (i+2)th gate signal g _i+2 , the gate clock signal GCK_L applied to the control terminal IP41 maintains the fourth high level voltage Vh4 within about 2H .

As a result, the tenth transistor Tr10 turns on and applies the off-gate voltage Voff to the node N1, and turns off the first to third transistors Tr1-Tr3.

Then, due to the voltage charged to the second capacitor C2 and the operation of the fifth transistor Tr5 according to the charging voltage, the storage signal _Vsi is maintained at the high level storage signal voltage V+ until the next frame.

Next, the operation of the signal generating circuit 710C connected to the (i+1)-th storage electrode line S _i+1 which is an even-numbered storage electrode line is described in further detail with reference to FIGS. 15 and 17A .

Like the i-th signal generating circuit 710C, when the gate-on voltage Von of the (i+3)th gate signal g _i+3 is applied to the input terminal IP31, the eighth transistor Tr8 is turned on, and passes the third high-level voltage The first direction signal of Vh3 turns on the first to third transistors Tr1-Tr3. Accordingly, the storage signal V _si+1 of the corresponding level voltage based on the voltage levels of the first, second and third clock signals CK1 , CK1B and CK2 is output to the output terminal OP.

When the state of the (i+3)th gate signal g _i + ₃ changes from the gate-off voltage Voff to the gate-on voltage Von, the gate clock signal GCK_R applied to the control terminal IP41 maintains the fourth high level voltage Vh4 within about 2H.

Accordingly, the tenth transistor Tr10 is turned on, and the first to third transistors Tr1 - Tr3 are turned off by the off-gate voltage Voff transmitted to the node N1. Subsequently, the storage signal V _si+1 maintains the low-level storage signal voltage V− until the next frame according to the voltage charged to the first capacitor C1 and the operation of the fourth transistor Tr4 according to the charging voltage.

In case the scanning direction of the gate driver 403 is the backward direction, the first direction signal DIR has a third low level voltage Vl3 and the second direction signal DIRB has a third high level voltage Vh3. Therefore, unlike the forward scanning direction, when the scanning direction is the backward direction, the first to third transistors Tr1-Tr3 are turned on by the gate signal applied to the second input terminal IP32 and the second direction signal DIRB.

In addition to the above description, the operation of the signal generation circuit 710c is the same as the case where the scanning direction of the gate driver 403 is the forward direction and outputs a storage signal having a level corresponding to the corresponding storage electrode line, so the selection of the channel is omitted here. A repeated description of the operation of the device 710c. And, similar to the case where the scanning direction of the gate driver 403 is the forward direction, the gate signal applied to the first input terminal IP31 outputs the gate-opening signal Von within about 2H, and then outputs the gate-closing signal Voff within one frame, so that the first The eight transistor Tr8 is turned off. Therefore, the first direction signal DIR does not affect the voltage VN1 of the node N1.

Next, the operation of the signal generation circuit 710c is described in further detail with reference to FIGS. 15 and 17B, in this case, the LCD according to the exemplary embodiment of the present invention operates in the frame inversion mode.

The operation of the signal generating circuit 710c is now described in further detail with reference to FIG. 17B. The operation of the signal generating circuit 710c is similar to that of the signal generating circuit 710c described with reference to FIG. 17A.

In FIG. 17, the first, second, and third clock signals CK1, CK1B, and CK2 alternately change every predetermined period (for example, about 1H), but as shown in FIG. 17B, the first, second, and third clock signals CK1 Each of , CK1B, and CK2 maintains a constant voltage within one frame. However, as shown in FIG. 17B, the waveform of each of the first, second, and third clock signals CK1, CK1B, and CK2 is inverted every successive frame.

When the scanning direction of the gate driver 403 is the forward direction, the first direction signal DIR has a third high level voltage Vh3, and the second direction signal DIRB has a third low level voltage Vl3.

First, the operation of the i-th signal generation circuit 710c connected to the i-th storage electrode line S _i with respect to a data voltage having, for example, positive polarity applied to the pixel PX is described.

The first clock signal CK1 maintains a first low-level voltage Vl1, and the second and third clock signals CK1B and CK2 maintain a first high-level voltage Vh1.

After the gate-opening voltage Von of the i-th gate signal g _i is applied, when the gate-opening voltage Von of the (i+2)th gate signal g _i+2 is applied to the first input terminal IP31, the eighth transistor Tr8 is turned on, And the first to third transistors Tr1-Tr3 are turned on by the first direction signal DIR.

Since the third clock signal CK2 maintains the second high-level voltage _Vh2 , the storage signal Vsi maintains the high-level storage signal voltage V+.

When the (i+2)th gate signal g _i+2 is changed to the gate-off voltage Voff, and the first to third transistors Tr1-Tr3 are turned off by a corresponding clock signal applied to the control terminal IP41, such as the gate clock signal GCK_L , the storage signal V _si maintains the high level storage signal voltage V+ until the next frame according to the voltage charged to the second capacitor C2 and the operation of the fifth transistor Tr5 according to the charging voltage.

Next, the operation of the i-th signal generating circuit 710c connected to the i-th storage electrode line S _i when a data voltage having a negative polarity is applied to the pixel PX is described in further detail. In this case, the first clock signal CK1 maintains the first high-level voltage Vh1, and the second and third clock signals CK1B and CK2 maintain the first low-level voltage Vl1.

After applying the gate-opening voltage Von of the i-th gate signal g _i , when the gate-opening voltage Von of the (i+2)th gate signal g _i+2 is applied to the first input terminal IP31, the eighth transistor Tr8 is turned on in response to is turned on, the first to third transistors Tr1-Tr3 are also turned on respectively. Therefore, by the third clock signal CK2 maintaining the second low-level voltage _Vl2 , the storage signal Vsi outputs a low-level storage signal voltage V−.

Subsequently, when the (i+2)th gate signal g _i+2 is changed to the gate-off voltage Voff, and the first to third transistors Tr1-Tr3 are turned off by the gate clock signal GCK_L applied to the control terminal IP41, the storage signal V _si maintains the low-level storage signal voltage V- until the next frame according to the voltage charged to the first capacitor C2 and the operation of the fourth transistor Tr4 according to the charged voltage.

When the scan signal of the gate driver 403 is in the backward direction, the first direction signal DIR has a fifth low level voltage Vl5, and the second direction signal DIRB has a first high level voltage Vh5.

Therefore, when the scanning direction of the gate driver 403 is the backward direction, the first to third transistors Tr1-Tr3 are turned on by the gate signal applied to the second input terminal IP32 and the second direction signal DIRB. Except for the above description, the operation of the signal generation circuit 710c is the same as the case where the scanning direction of the gate driver 403 is the forward direction described in more detail above, so any repeated description of the operation of the signal generation circuit 710c is omitted here.

As described above, when the LCD operates in the frame inversion mode, the first, second and third clock signals CK1, CK1B and CK2 maintain the same voltage level for about one frame.

Then, after the gate signal applied to the corresponding pixel row is changed from the gate-on voltage Von to the gate-off voltage Voff, since the signal generating circuit 710c shown in FIG. Outputting the gate signal Von, which is delayed by about 2H from the previous stage of the first or second gate driver 403a or 403b, operates with frame inversion. Therefore, since the phase difference between the gate-on voltage Von applied to the _i -th gate line Gi and the gate-on voltage Von applied to the i-th storage signal generating circuit 710c is about 2H, the gate-on voltages Von do not overlap. Therefore, after the charging operation of the i-th pixel row is substantially completed, the signal level of the storage signal V _si applied to the i-th storage electrode line S _i changes, thereby changing the i-th storage signal V _si according to the changed signal level of the storage signal V si The charging voltage for the pixel row.

Alternatively, the states of the first, second and third clock signals CK1, CK1B and CK2 may be changed when a predetermined time has elapsed since the change of the gate signal is completed, and may voltage, or alternatively, the first, second and third clock signals CK1, CK1B and CK2 are output after the gate-off voltage is changed to the gate-open voltage.

According to an exemplary embodiment of the present invention as described herein, since the common voltage is fixed at a predetermined level, and a storage signal whose amplitude varies with a predetermined period is applied to the storage electrode line, the range of the pixel electrode voltage is increased, And the range of the pixel voltage is expanded, but the range of the gray voltage is not increased accordingly. Therefore, the effective voltage range of the gray scale voltage is expanded, thereby effectively improving the resolution.

Also, the range of pixel voltages generated when a certain range of data voltages is applied is larger than the range of pixel voltages generated when a storage signal of a predetermined value is applied. Therefore, power consumption is effectively reduced. In addition, a liquid crystal display including a bidirectional gate driver and a storage signal generator is adopted without additional selection circuits, thereby effectively reducing the size of the liquid crystal display and/or reducing the manufacturing cost of the liquid crystal display.

In alternative exemplary embodiments, a liquid crystal display according to an exemplary embodiment of the present invention may operate according to, for example, frame inversion and row inversion, but is not limited thereto.

The present invention should not be construed as limited to the exemplary embodiments presented herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

Although the present invention has been particularly described with reference to certain exemplary embodiments of the present invention, those skilled in the art will understand that various changes in form and details may be made therein without departing from the teachings. The spirit and scope of the invention are defined by the appended claims.

Claims (20)

1. a display device, comprising:

Many door lines, for transmitting the gate signal having enabling voltage and close gate voltage;

A plurality of data lines, for transmitting data voltage;

Many storage electrode lines, for transmitting storage signal;

Be arranged in multiple pixels of approximate matrix pattern, wherein, the first pixel of the plurality of pixel comprises:

The on-off element be connected with a data line in first line of transmission first gate signal in many door lines and a plurality of data lines;

The liquid crystal capacitor be connected with on-off element and utility voltage; And

The holding capacitor be connected with a storage electrode line in on-off element and many storage electrode lines;

Gate driver, for generating gate signal along the first direction of scanning or the second direction of scanning; And

Multiple signal generating circuit, for generating storage signal,

Wherein, the storage signal be applied in the first pixel has the voltage level changed after charge data voltage is charged to liquid crystal capacitor and holding capacitor,

Storage signal becomes from the output order of multiple signal generating circuit with the direction of scanning of gate driver,

The first signal generating circuit that the storage electrode line to the first pixel in the plurality of signal generating circuit applies storage signal comprises the signal input unit exporting drive control signal, the storage signal applying unit exporting storage signal, control module and keeps the signal holding unit of storage signal

This signal input unit comprises the first transistor and transistor seconds, the first transistor comprises the input end receiving first direction signal and the control end receiving the second gate signal, transistor seconds comprises the input end receiving second direction signal and the control end receiving the 3rd gate signal, this signal input unit comprises the input end having and be connected with pass gate voltage further, the control end be connected with clock signal and the 7th transistor of output terminal be connected with drive control signal, the first transistor, transistor seconds, the output terminal of the 7th transistor is connected the output terminal forming this signal input unit,

This storage signal applying unit comprises third transistor, and it comprises the input end of reception first control signal, comprises the control end be connected with the output terminal of signal input unit, and comprises the output terminal be connected with storage electrode line, and

This control module comprises two the 4th transistors, described two the 4th transistors comprise the control end be connected with the output terminal of signal input unit, one of described two the 4th transistors comprise the input end be connected with the second control signal, and another of described two the 4th transistors comprises the input end be connected with the 3rd control signal

Wherein, this signal holding unit comprises:

Containing the control end be connected with the output terminal of one of described two the 4th transistors, the input end be connected with the first driving voltage and the 5th transistor of output terminal that is connected with storage electrode line;

Containing the control end be connected with another output terminal of described two the 4th transistors, the input end be connected with the second driving voltage and the 6th transistor of output terminal that is connected with storage electrode line;

Be connected to the first capacitor between the input end of the 5th transistor and control end; And

Be connected to the second capacitor between the input end of the 6th transistor and control end,

Wherein, the storage signal be applied in the first pixel changes over high level when charge data voltage has positive polarity from low level, and changes over low level when charge data voltage has negative polarity from high level,

Wherein, utility voltage is fixed voltage.

2. display device according to claim 1, wherein, each frame of this storage signal is anti-phase.

3. display device according to claim 1, wherein,

Starting after-applied second gate signal applying the first gate signal to first line,

The 3rd gate signal was applied before beginning applies the first gate signal to first line,

Wherein, mistiming between the enabling voltage application time of the first gate signal and the enabling voltage application time of the second gate signal is about two horizontal cycles (2H), and the mistiming between the enabling voltage application time of the first gate signal and the enabling voltage application time of the 3rd gate signal is about two horizontal cycles (2H).

4. display device according to claim 1, wherein, the second control signal that this signal holding unit applies according to the mode of operation according to control module or the 3rd control signal and operate.

5. display device according to claim 1, wherein, first direction signal and second direction signal have the signal condition of the direction of scanning based on gate driver separately.

6. display device according to claim 5, wherein, the phase place of first direction signal is in fact contrary with the phase place of second direction signal.

7. display device according to claim 1, wherein, the level of first direction signal and each constant of level of second direction signal.

8. display device according to claim 1, wherein, this signal input unit selects one of first direction signal and second direction signal according to the second gate signal and the 3rd gate signal, and exports drive control signal according to selected first direction signal or selected second direction signal.

9. display device according to claim 8, wherein, the level of first direction signal and each constant of level of second direction signal.

10. display device according to claim 9, wherein, this signal input unit is supplied the clock signal of the second electrical level voltage having the first level voltage and be different from the first level voltage, and each predetermined period in succession of the level of this clock signal replaces between the first level voltage and second electrical level voltage.

11. display devices according to claim 10, wherein, the interval of this predetermined period is about two horizontal cycles (2H).

12. display devices according to claim 11, wherein, the phase place being applied to the clock signal on the first signal generating circuit of multiple signal generating circuit is in fact contrary with the phase place being applied to the clock signal on the secondary signal generative circuit adjacent with the first signal generating circuit.

13. display devices according to claim 12, wherein, this signal input unit is by changing the state of operation signal holding unit of the drive control signal based on first direction signal or second direction signal according to clock signal.

14. display devices according to claim 13, wherein, the voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is practically identical with the voltage level being applied to the storage signal on the second storage electrode line adjacent with the first storage electrode line.

15. display devices according to claim 14, wherein, the voltage level of the voltage level of the first control signal, the voltage level of the second control signal and the 3rd control signal is giving constant in framing, and each successive frames is anti-phase.

16. display devices according to claim 1, wherein, the voltage level being applied to the storage signal on the first storage electrode line of many storage electrode lines is different with the voltage level of the storage signal be applied on the second storage electrode line adjacent from the first storage electrode line.

17. display devices according to claim 16, wherein,

First control signal, the second control signal and the 3rd control signal each there is the first level voltage and second electrical level voltage,

The respective level of the first control signal, the second control signal and the 3rd control signal giving in framing every subsequent cycles between the first level voltage and second electrical level voltage alternately, and

The respective level of the first control signal, the second control signal and the 3rd control signal is anti-phase every a frame.

18. display devices according to claim 1, comprise at least one extra gate line gate signal being sent to a signal generating circuit in multiple signal generating circuit further.

19. display devices according to claim 1, wherein, adjacent gate signal predetermined time cycle at least partially in overlapped in time.

20. display devices according to claim 19, wherein, the interval of this predetermined period of time is an about horizontal cycle (1H).