CN102611854B

CN102611854B - Realization Device of Column Level ADC in CMOS Image Sensor

Info

Publication number: CN102611854B
Application number: CN201210074364.5A
Authority: CN
Inventors: 徐江涛; 徐文静; 姚素英; 高静; 史再峰; 聂凯明; 高岑
Original assignee: Tianjin University
Current assignee: Tianjin University
Priority date: 2012-03-20
Filing date: 2012-03-20
Publication date: 2014-01-15
Anticipated expiration: 2032-03-20
Also published as: CN102611854A

Abstract

The invention relates to the field of analog integrated circuit design. In order to provide an ADC structure with a simple structure and a short conversion period to achieve the purpose of improving the dynamic range of the sensor, the technical solution adopted by the present invention is that the realization device of the column-level ADC in the CMOS image sensor includes: a single-slope analog-to-digital converter, A successive approximation analog-to-digital converter, two ramp signal generators; a single-slope analog-to-digital converter, a successive approximation analog-to-digital converter and a group of 6 switches form a unit, and each column in the sensor pixel array is provided with one aforementioned unit; two A ramp signal generator is shared by each column of the sensor pixel array. The invention is mainly applied to the design and manufacture of semiconductor image sensors.

Description

The implement device of row level ADC in cmos image sensor

Technical field

The present invention relates to analog integrated circuit design field, relate in particular to the implement device of a kind of row level ADC applying in imageing sensor, be i.e. the implement device of row level ADC in cmos image sensor.

Background technology

Along with developing rapidly of digital technology, semiconductor fabrication, cmos image sensor becomes object current and that future market is paid close attention to.At present, the analog to digital converter (ADC) being applied in cmos image sensor has three kinds of different types: Pixel-level, row level, chip-scale.Fig. 1 is row level ADC Organization Chart, and row level ADC compares with chip-scale ADC, low to ADC rate request, has therefore reduced power consumption and the design difficulty of chip.Row level ADC compares with Pixel-level ADC simultaneously, and ADC is by transferring in pixel outside pel array, and this has improved fill factor, curve factor greatly, thereby has improved the sensitivity of imageing sensor.Therefore row level ADC has a wide range of applications in imageing sensor.But the layout size of row level ADC is subject to the restriction of Pixel Dimensions, this has increased the layout design difficulty of row level ADC.

Monocline ADC (SS ADC, Single Slope ADC) and successive approximation analog to digital C (SA ADC, Successive Approximation ADC) are two kinds of common implementations in row level ADC.Fig. 2 is N position SS adc circuit structure chart, and in cmos image sensor, all row SS ADC share Yi Ge slope, and each row only needs a comparator and 1 N bit register, so simplicity of design, and every row chip area is little, is easy to realize.The shortcoming of SS ADC is that the change-over period is long, and N position SS ADC needs 2 ⁿ-1 clock cycle just can complete once conversion.Fig. 3 is N position SAADC circuit structure diagram, compare with SS ADC, the change-over period of SA ADC is very short, the SA ADC of N position only needs N clock cycle just can complete once conversion, its shortcoming is that each row all needs a complete N position ADC, therefore the chip area of every row is very large, has increased design difficulty.

Summary of the invention

The present invention is intended to solution and overcomes the deficiencies in the prior art, the row level ADC that a kind of chip area is little, the change-over period is little structure is provided, the technical scheme that the present invention takes is, the implement device of row level ADC in a kind of cmos image sensor, it is characterized in that, comprising: two ramp signal generators, pulse latches, M bit register, gradually-appoximant analog-digital converter; Pulse latches, M bit register, gradually-appoximant analog-digital converter and one group of 6 switch form Yi Ge unit; In sensor pixel array, every row are provided with an aforementioned unit;

Two ramp signal generators are that the every row of sensor pixel array share, two ramp signal generators are corresponding respectively provides height reference potential by the 4th switch in one group of 6 switch, the 5th switch for gradually-appoximant analog-digital converter, and one of them ramp signal generator is connected to the comparator inverting input of monocline analog to digital converter by the 1st switch in one group of 6 switch;

In sensor pixel array, the output of every row is connected to the in-phase input end of the comparator of monocline analog to digital converter, and the output of the comparator of monocline analog to digital converter connects the pulse latches of monocline analog to digital converter after by the 6th switch in one group of 6 switch successively, high M bit register carries out high M position and exports;

The N-M figure place weighted-voltage D/A converter of gradually-appoximant analog-digital converter is connected to the comparator inverting input of monocline analog to digital converter by the 2nd switch in one group of 6 switch, the N-M position logic control of gradually-appoximant analog-digital converter is connected to the output of the comparator of monocline analog to digital converter by the 3rd switch in one group of 6 switch;

The 1st switch in one group of 6 switch, the 6th switch gearing; The 2nd switch in one group of 6 switch, the 3rd switch gearing; The high level pulse that pulse latches produces is controlled the 4th switch, the 5th switch gearing.

Between the 4th switch, the 5th switch and gradually-appoximant analog-digital converter, pass through respectively a capacity earth.

Described N < 15, M < N.

Technical characterstic of the present invention and effect:

Of the present invention is that row level SS ADC and row level SAADC are combined, utilize SS ADC to carry out high position data conversion, utilize SA ADC to carry out low data conversion, because SS ADC only need to carry out high-order portion data transaction, switching rate is compared with independent SS ADC and is index lifting, meanwhile, and because SA ADC only need to carry out low portion data transaction, every row chip area is compared and is index decreased with independent SAADC, thus the good compromise of the speed of obtaining and area.

Accompanying drawing explanation

Fig. 1 is listed as a grade ADC Organization Chart.

The row level SS adc circuit structure chart that Fig. 2 is traditional.

The row level SA adc circuit structure chart that Fig. 3 is traditional.

Fig. 4 row level provided by the invention adc circuit structure chart.

The fundamental diagram of Fig. 5 row level provided by the invention ADC.

Embodiment

Take the scheme shown in Fig. 4 as example, all row share Liang Ge slope, produce the binary system code value on slope 1 than producing the binary system code value Duo Yiwei， slope 1 on slope 2 and signal that slope 2 produces and receive respectively by sampling hold circuit and voltage buffer (buffer) in the SA ADC of every row on the needed height reference voltage of DAC.The required circuit structure of every row and SA ADC are similar, but have increased switch S 4, S5 and sampling capacitance C1, C2 and two buffer.The comparator negative terminal of each row has double switch, and when carrying out the conversion of high M position, comparator negative terminal connects the ramp signal that slope 1 produces; When carrying out the conversion of low N-M position, negative terminal connects the signal that in SAADC, DAC produces, so SS ADC and the shared comparator of SAADC.

Operation principle is as follows:

First stage: first outside sequencing control switch S 1, S6 closure, switch S 2, S3 disconnect, the ramp signal vramp1 that slope 1 produces receives the negative terminal of comparator, the input signal vin that the positive termination of comparator need to be changed, the SS ADC that at this moment integrated circuit provided by the invention is equivalent to a M position is in work.Quantizing process is as shown in Fig. 5-1, when vin is greater than vramp1, comparator overturns, pulse latches produces high level pulse, the high M bit code value of changing out is deposited in high M bit register, high level pulse control switch S4 meanwhile, S5 is closed, vramp1 and vramp2 corresponding when comparator is overturn sample sampling capacitance C1, on C2, then high level pulse finishes, pulse latches output low level, control switch S4, S5 disconnects, sampling capacitance C1, magnitude of voltage on C2 remains comparator vramp1 corresponding to when upset, the magnitude of voltage of vramp2, these two voltages provide needed height reference voltage to DAC respectively by buffer.

Second stage: outside sequencing control switch S 2, S3 closure, switch S 1, S6 disconnect.Quantizing process is as shown in Fig. 5-2, and now the height reference voltage of DAC is between the sloped region at first stage vin place, and SAADC only need to successively approach vin in this interval.At this moment circuit provided by the invention is equivalent to the SAADC of a N-M position.After N-M clock cycle, the output valve Vout SA of DAC equals vin within the scope of error requirements, and logic control element has produced corresponding low N-M code value simultaneously, and this code value and high M bit code merge the complete N bit code value of last output.

N provided by the invention ranks in grade ADC, and SS ADC is partly responsible for conversion high M position, and SA ADC is partly responsible for conversion low N-M position (M < N).

The speed ratio of N provided by the invention position ADC and N position SS ADC is: N position SS ADC required change-over time is 2 ⁿ-1 clock cycle, be 2 the change-over time of N provided by the invention position ADC ^mthe individual clock cycle of-1+ (N-M), than SS ADC speed, be index and promote.

The chip area comparison of N provided by the invention position ADC and N position SA ADC: N position SA ADC comprises a N position DAC, a comparator and a N position logic control element, wherein most of area is shared by N position DAC, adopts the N position DAC of traditional binary capacitance structure to need 2 ⁿindividual specific capacitance.N provided by the invention position ADC increases Liao Liangge slope, switch S 1-S6, capacitor C 1-C2 and two buffer memory buffer than N position SAADC, and N position DAC is reduced to N-M position DAC simultaneously, and the logic control of N position is reduced to the logic control of N-M position.Because Liang Ge slope is that all row share, the area therefore increasing than the whole chip area ，Zhe Liangge slope of all row is negligible.Because the logic control of N position is reduced to the logic control of N-M position, the logic control of N-M position with lacked M switch being connected of DAC, therefore, the switch S 1-S6 of increase can not increase area substantially.Therefore because buffer only drives the electric capacity in row, so the area of buffer is less, and two the buffer areas and two electric capacity (C1, the C2) area that increase are very little.But because SAADC part only need to be changed N-M position, so adopt the DAC of traditional binary capacitance structure only to need 2 ^n-Mindividual specific capacitance, therefore than DAC in the SA ADC of N position required 2 ⁿindividual specific capacitance DAC chip area of the present invention is index decreased.Because DAC has taken the overwhelming majority of whole chip area, so the required chip area of N provided by the invention position ADC is compared and is index decreased with N position SAADC.

For the row provided by the invention level ADC of 10 precision, it is high 5 that SS ADC is partly responsible for conversion, and it is low 5 that SAADC is partly responsible for conversion, i.e. M=5, N=10.

The speed ratio of 10 ADC provided by the invention and 10 SS ADC is: during 10 required conversions of SS ADC, be 1023 clock cycle, be 36 clock cycle the change-over time of 10 ADC provided by the invention, and its conversion speed is about 28 times of 10 SS ADC conversion speeds.

The chip area comparison of 10 ADC provided by the invention and 10 SAADC: 10 the every row of SAADC DAC need 1024 specific capacitances, 10 the every row of ADC DAC provided by the invention need 32 specific capacitances, and the required DAC area of its every row is 3.1% of SAADC.

Row level ADC execution mode provided by the invention had both met 10 required precisions, can realize again the best compromise of speed and area.

N=14, M=12 or 13; Or N=2, under the limiting case of M=1, the present invention still can bring into play good effect, and just at N=10, under the situation of M=5, compromise effect is better.

Claims

1. A realization device of column-level ADC in a CMOS image sensor is characterized in that it comprises: two ramp signal generators, pulse latches, M-bit registers, successive approximation analog-to-digital converters, and single-slope analog-to-digital converters The comparator of the pulse latch, the M-bit register, the successive approximation analog-to-digital converter, the comparator of the single-slope analog-to-digital converter and a group of 6 switches form a unit; each column in the sensor pixel array is provided with one aforementioned unit ;

The two ramp signal generators are shared by all columns in the sensor pixel array, and the two ramp signal generators respectively provide high and low reference potentials for the successive approximation analog-to-digital converter through the fourth switch and the fifth switch in a group of six switches, wherein A ramp signal generator in a group of 6 switches is connected to the comparator inverting input terminal of the single-slope analog-to-digital converter through the first switch in a group of 6 switches;

The output of each column in the sensor pixel array is connected to the non-inverting input terminal of the comparator of the single-slope analog-to-digital converter, and the output terminal of the comparator of the single-slope analog-to-digital converter is connected sequentially through the sixth switch in a group of 6 switches The pulse latch of the single-slope analog-to-digital converter and the high-M-bit register perform high-M-bit output;

The N-M digit-to-analog converter of the successive approximation analog-to-digital converter is connected to the comparator inverting input terminal of the single-slope analog-to-digital converter through the second switch in a group of 6 switches, and the N-M bit logic of the successive approximation analog-to-digital converter controls the output of a comparator connected to a single-slope analog-to-digital converter through a third switch in a set of six switches;

The first switch and the sixth switch in a group of 6 switches are linked; the second switch and the third switch in a group of 6 switches are linked; the high-level pulse generated by the pulse latch controls the fourth switch and the fifth switch linkage.

2 . The device for implementing column-level ADC in a CMOS image sensor according to claim 1 , wherein the fourth switch, the fifth switch, and the successive approximation analog-to-digital converter are respectively grounded through a capacitor.

3. The realization device of column-level ADC in CMOS image sensor as claimed in claim 1, it is characterized in that, described N<15, M<N.