CN102610624A - Method for packaging semiconductor - Google Patents
Method for packaging semiconductor Download PDFInfo
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- CN102610624A CN102610624A CN2012100646861A CN201210064686A CN102610624A CN 102610624 A CN102610624 A CN 102610624A CN 2012100646861 A CN2012100646861 A CN 2012100646861A CN 201210064686 A CN201210064686 A CN 201210064686A CN 102610624 A CN102610624 A CN 102610624A
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- substrate
- temporary base
- conducting medium
- described hole
- weld pad
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 21
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- 239000000853 adhesive Substances 0.000 claims abstract description 19
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- 238000003466 welding Methods 0.000 claims abstract description 15
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Abstract
The invention discloses a method for packaging a semiconductor. The method includes steps: providing a substrate including an upper surface and a lower surface opposite to the upper surface, and arranging a photosensitive area and a welding pad which is electrically connected with the photosensitive area on the substrate; providing a temporary substrate, and forming a holding space capable of holding the photosensitive area at least on the temporary substrate; arranging adhesive on the surface, with the holding area, of the temporary substrate, adhering the surface of the temporary substrate on the upper surface of the substrate and leading the photosensitive area to be positioned in the holding space; forming a hole which is exposed out from the welding pad on the lower surface of the substrate; forming a conducting medium which is electrically connected with the welding pad in the hole; and stripping the substrate off from the temporary substrate. Compared with the prior art, the method has the advantages that a transparent substrate on the photosensitive area is removed, accordingly, light is received and transmitted smoothly, and integral performances of a chip are enhanced.
Description
Technical field
The invention belongs to the field of semiconductor manufacture technology, relate in particular to a kind of method for packaging semiconductor.
Background technology
Wafer-level packaging (Wafer Level Packaging, WLP) technology is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, chip size and nude film after the encapsulation are in full accord.The crystal wafer chip dimension encapsulation technology has thoroughly been overturned conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic LeadlessChip Carrier) isotype, has complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.
In the existing wafer-level packaging technology, for example be the encapsulation of sensitive chip, the photosensitive area of its sensitization often receives the influence of the transparency carrier on it, makes that the reception of light is not smooth with emission, thereby influences the overall performance of chip.
Summary of the invention
The object of the present invention is to provide a kind of method for packaging semiconductor.
For realizing the foregoing invention purpose, the present invention provides a kind of method for packaging semiconductor, and this method may further comprise the steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, comprise photosensitive area on the said substrate, and the weld pad that electrically connects with said photosensitive area;
One temporary base is provided, on said temporary base, forms receiving space, said receiving space can hold said photosensitive area at least;
Be formed with at said temporary base on the one side of receiving space adhesive is set, and it is fitted on the upper surface of said substrate, said photosensitive area is positioned at said receiving space;
Lower surface from said substrate forms the hole that exposes said weld pad;
In described hole, form the conducting medium that electrically connects with said weld pad;
Said substrate and said temporary base are peeled off.
As further improvement of the present invention, said " in described hole, forming the conducting medium that electrically connects with said weld pad " step specifically comprises:
On the sidewall of described hole and bottom, form insulating barrier;
Remove insulating barrier on the described hole bottom to expose said weld pad;
On the sidewall of described hole and bottom, form the conducting medium that electrically connects with said weld pad.
As further improvement of the present invention, this method also comprises:
On the lower surface of said substrate, form insulating barrier, and the conducting medium in the described hole is extended on the insulating barrier of bottom surface section;
On the conducting medium of the lower surface of said substrate, form welding resisting layer;
On said welding resisting layer, form the opening that part exposes said conducting medium, and form pedestal or the contact array that electrically connects with said conducting medium through said opening.
As further improvement of the present invention, specifically comprise " said substrate and said temporary base are peeled off ": cutting said substrate and said temporary base is a plurality of chips; Respectively said substrate on a plurality of chips and said temporary base are peeled off.
As further improvement of the present invention, described hole near the bore of the opening of said base lower surface bore near the opening of said upper surface of base plate greater than described hole.
The foregoing invention purpose can also solve through following method, and a kind of method for packaging semiconductor is provided, and this method may further comprise the steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, comprise photosensitive area on the said substrate, and the weld pad that electrically connects with said photosensitive area;
One temporary base is provided, and on said temporary base, forms the obstruct wall, said obstruct wall and said temporary base form a receiving space, and said receiving space can hold said photosensitive area at least;
On the obstruct wall of said formation, adhesive is set, and said temporary base is manufactured with the one side that intercepts wall is fitted on the upper surface of said substrate, said photosensitive area is positioned at said receiving space;
Lower surface from said substrate forms the hole that exposes said weld pad;
In described hole, form the conducting medium that electrically connects with said weld pad;
Said substrate and said temporary base are peeled off.
As further improvement of the present invention, said " forming the obstruct wall on the said temporary base " step specifically comprises: spin coating one adhesion glue on said temporary base, and the said adhesion glue of photoetching forms said obstruct wall.
As further improvement of the present invention, said " in described hole, forming the conducting medium that electrically connects with said weld pad " step specifically comprises:
On the sidewall of described hole and bottom, form insulating barrier;
Remove insulating barrier on the described hole bottom to expose said weld pad;
On the sidewall of described hole and bottom, form the conducting medium that electrically connects with said weld pad.
As further improvement of the present invention, this method also comprises:
On the lower surface of said substrate, form insulating barrier, and the conducting medium in the described hole is extended on the insulating barrier of bottom surface section;
On the conducting medium of the lower surface of said substrate, form welding resisting layer;
On said welding resisting layer, form the opening that part exposes said conducting medium, and form pedestal or the contact array that electrically connects with said conducting medium through said opening.
As further improvement of the present invention, specifically comprise " said substrate and said temporary base are peeled off ": cutting said substrate and said temporary base is a plurality of chips; Respectively said substrate on a plurality of chips and said temporary base are peeled off.
As further improvement of the present invention, described hole near the bore of the opening of said base lower surface bore near the opening of said upper surface of base plate greater than described hole.
Compared with prior art, the present invention has removed the transparency carrier of photosensitive area on it, make light reception and emission smoothly, improve the overall performance of chip.
Description of drawings
Fig. 1 is the structural representation of the temporary base that is formed with receiving space of first embodiment of the invention encapsulating structure;
Fig. 2 is the structural representation that adhesive is set on temporary base shown in Figure 1;
Fig. 3 is the structural representation that the substrate of first embodiment of the invention encapsulating structure cooperates with temporary base;
Fig. 4 is in structure shown in Figure 3, on substrate, makes the structural representation that exposes weld pad;
Fig. 5 is in structure shown in Figure 4, in hole, makes the structural representation of insulating barrier;
Fig. 6 is in structure shown in Figure 5, and the insulating barrier of hole bottom is removed to expose the structural representation of weld pad;
Fig. 7 is in structure shown in Figure 6, in hole, makes the structural representation of the conducting medium that electrically connects with weld pad;
Fig. 8 is in structure shown in Figure 7, makes the structural representation of the pedestal that is connected with extraneous pcb board;
Fig. 9 is the structural representation that the encapsulation of first embodiment of the invention encapsulating structure is accomplished;
Figure 10 is the flow chart of the method for packaging semiconductor of first embodiment of the invention;
Figure 11 is the structural representation that adheres to the glue of adhering on the temporary base of second embodiment of the invention encapsulating structure;
Figure 12 forms the structural representation that intercepts wall at temporary base photoetching adhesion glue shown in Figure 11;
Figure 13 is the structural representation that adhesive is set on the obstruct wall of second embodiment of the invention encapsulating structure;
Figure 14 is the structural representation that the substrate of second embodiment of the invention encapsulating structure cooperates with temporary base;
Figure 15 is in structure shown in Figure 14, on substrate, makes the structural representation that exposes weld pad;
Figure 16 is in structure shown in Figure 15, in hole, makes the structural representation of insulating barrier;
Figure 17 is in structure shown in Figure 16, and the insulating barrier of hole bottom is removed to expose the structural representation of weld pad;
Figure 18 is in the structure shown in 17, in hole, makes the structural representation of the conducting medium that electrically connects with weld pad;
Figure 19 is in structure shown in Figure 180, makes the structural representation of the pedestal that is connected with external pcb board;
Figure 20 is the structural representation that adopts semiconductor module one execution mode of encapsulating structure of the present invention;
Figure 21 is the structural representation that adopts the another execution mode of semiconductor module of encapsulating structure of the present invention;
Figure 22 is the flow chart of the method for packaging semiconductor of first embodiment of the invention.
Embodiment
Below will combine embodiment shown in the drawings to describe the present invention.But these execution modes do not limit the present invention, and the conversion on the structure that those of ordinary skill in the art makes according to these execution modes, method or the function all is included in protection scope of the present invention.
In addition, in different execution modes, possibly use the label or the sign of repetition.These repeat to be merely simply clearly narrates the present invention, does not represent between the different execution modes discussed and/or the structure to have any relevance.
In addition, the label of mentioning in each execution mode of the present invention relevant for step only to be the convenience in order describing, and not to have the contact of sequencing in fact.Different step in each embodiment can be carried out the combination of different sequencings, realizes goal of the invention of the present invention.
Ginseng Fig. 1 to Fig. 9, a series of processing procedure profiles of the encapsulating structure of demonstration first embodiment of the invention.Below at first introduce an execution mode of the semiconductor package that method for packaging semiconductor of the present invention makes, this encapsulating structure comprises substrate 10, hole 13 and is formed at the conducting medium 15 in the hole 13.
Substrate have upper surface 100a and with upper surface 100a opposing lower surface 100b, comprise photosensitive area 12 on it, and the weld pad 11 that electrically connects with photosensitive area 12.Should be understood that said photosensitive area 12 and/or weld pad 11 can be the side surface or the parts that are arranged at substrate 10/all be positioned at substrate 10 inside here.And said upper surface 100a and lower surface 100b do not have the implication on the three-dimensional position, and said photosensitive area 12 is produced on the upper surface with weld pad 11 usually, perhaps in the substrate relatively near upper surface 100a place.
The material of weld pad 11 is generally metal material, for example is aluminium, copper, gold or its homologue or its two or more combination arbitrarily.
The opening of hole 13 can have different shape, for example is circle, ellipse, square or rectangular etc.When opening was circle, above-mentioned bore was the diameter of circular open.
Conducting medium 15 is formed in the hole 13, and electrically connects with weld pad 11.
Should be understood that the photosensitive area of mentioning in the embodiment of the present invention 12 is notions of upperization, it can be the functional circuit of on substrate 10, making, and also can comprise wafer.Here said functional circuit/wafer can comprise logical operation circuit/wafer, physics sensing circuit/wafer that MEMS circuit/wafer, microfluid system circuit/wafer or physical change amounts such as utilization heat, light and pressure are measured, radio circuit/element wafer etc.In this execution mode, this photosensitive area 12 is manufactured with photosensitive circuit, under this situation, can select on this photosensitive area 12, to be provided with optical lens (figure does not indicate).Optical lens can comprise lens arra.Like this, can reduce the influence of transparency carrier greatly, promote the encapsulating structure quality photosensitive area 12.
With reference to Figure 20 and Figure 21; Be two kinds of execution modes of the semiconductor module that adopts encapsulating structure of the present invention, it has all comprised semiconductor encapsulating structure, a lens assembly, wherein; Said lens assembly comprises lens container 51, and is fixedly installed at least one camera lens 52 in the lens container 51.Different is, through the BGA encapsulation, promptly realizes being connected of semiconductor modules and pcb board 40 through tin ball 17 among Figure 20; And among Figure 21 through LGA encapsulation, promptly realize being connected of semiconductor modules and pcb board 40 through contact array 18.
Cooperation is below introduced the method for packing of the encapsulating structure of first embodiment of the invention with reference to Figure 10.
S11 provides a substrate 10, it comprise upper surface 100a and with the opposing lower surface 100b of upper surface 100a.The material of substrate 10 can comprise semi-conducting material, ceramic material or macromolecular material etc.In one embodiment, substrate 10 can be a silicon base.In another embodiment, substrate 10 can be a Silicon Wafer, and preferable with wafer-level packaging cooperation cutting step, to form out simultaneously a plurality of semiconductor packages, can practice thrift processing procedure cost and time.Wherein, in this execution mode, this substrate adopts Silicon Wafer.
Also comprise photosensitive area 12 and the weld pad 11 that electrically connects with photosensitive area 12 on this substrate.
S12 provides a temporary base 20, and the material of this temporary base 20 can comprise semi-conducting material, ceramic material or metal material etc.And on this temporary base 20, forming receiving space 21 through photoetching, etching, this receiving space 21 can hold photosensitive area 12 at least.
S13 then is formed with at this temporary base 20 on the one side of receiving space 21 adhesive 30 is set, and it is fitted on the upper surface 100a of substrate 10.But the adhesive 30 preferable materials of selecting easy removal for use for example can make it scission of link through applying of energy, help temporary base 20 on substrate 10, to remove.In this execution mode, can for example remove adhesive 30 with mode of heating.
And adhesive preferably adopts light-transmitting materials, like this, after encapsulation is accomplished, can practice thrift cost through the quality in transparent adhesives check pattern zone.
Preferably, in this execution mode, adhesive 30 only is arranged on the position outside the receiving space 21 on the temporary base 20 (being not to be provided with adhesive 30 on sidewall and the bottom of receiving space 21).When temporary base 20 was fitted mutually with substrate 10, the photosensitive area 12 on the substrate 10 was received in the receiving space 21 fully, and the photosensitive area 12 on the substrate does not contact with the sidewall and the bottom of receiving space 21.
S14 removes the substrate of part from the lower surface 100b of substrate 10 subsequently, exposes the hole 13 of weld pad 11 with formation, particularly, can be through photoetching, semiconductor technologies such as etching make.In this execution mode, hole 13 near the bore of the opening of lower surface 100b greater than the bore of hole 13 near the opening of upper surface 100a, and have the profile of circular cone or pyramid, and have steep sidewalls.In concrete technology, the process parameter such as concentration that can adjust power in the etch process, pressure, etching gas/liquid are to obtain above-mentioned hole 13 structures.
S15 forms the conducting medium 15 that electrically connects with weld pad 11 in hole 13 after hole 13 forms.Particularly:
At first on the sidewall of hole 13 and bottom, form insulating barrier 14.The material of insulating barrier 14 for example comprises epoxy resin, anti-welding material or other megohmite insulant that is fit to, the for example silicon oxide layer of inorganic material, silicon nitride layer, silicon oxynitride layer, metal oxide or aforesaid combination; Or also can be polyimide resin, benzocyclobutene, Parylene, naphthalene polymer, fluorine carbide, acrylic acid ester of high-molecular organic material etc.The generation type of insulating barrier 14 can comprise coating method, for example, and rotary coating, spraying, or other depositional mode that is fit to, for example, physical vapour deposition (PVD), chemical vapour deposition (CVD).
Then, remove insulating barrier 14 on hole 13 bottoms to expose weld pad 11.Since hole 13 near the bore of the opening of lower surface 100b greater than the bore of hole 13 near the opening of upper surface 100a, so can remove the insulating barrier 14 on hole 13 bottoms more easily, further reduce technology difficulty.
Then, on the sidewall of hole 13 and bottom, form the conducting medium 15 that electrically connects with weld pad 11.Conducting medium 15 electrically contacts with weld pad 11, therefore also electrically connects with photosensitive area 12.The material of conducting medium 15 can comprise copper, aluminium, gold, platinum or its combination.Conducting medium 15 can form through common manufacture of semiconductor technology such as plating, electroless plating, physical vapour deposition (PVD), chemical vapour deposition (CVD).
For the encapsulating structure that obtains is realized and being connected of external pcb board 40, in this execution mode, also need carry out following step:
On the lower surface of substrate 10, also form insulating barrier 14, and during the conducting medium 15 in forming hole 13, this conducting medium 15 is extended on the substrate 10 lower surface 100b partial insulating layer 14.On the conducting medium 15 of the lower surface 100b of substrate 10, form welding resisting layer 16, this welding resisting layer 16 in fact also is full of in hole 13.
This welding resisting layer 16 of etching forms the opening (figure does not indicate) that part exposes conducting medium 15; And with in this opening of tin material implantation; Form the pedestal 17 (BGA) or the contact array (LGA) that electrically connect with conducting medium 15; Be used for being connected, preferably, use contact array can optimize image quality with external pcb board 40.
S16 (is substrate and temporary base Silicon Wafer in this execution mode at last; And employing wafer-level packaging technology) be cut into a plurality of chips; Promptly be to obtain encapsulating structure disconnected from each other; And, respectively substrate on a plurality of chips and temporary base 20 are peeled off through heated adhesive 30, obtain final chip-packaging structure.
Cooperation is with reference to Figure 11 to Figure 19, and Figure 22, introduces second execution mode of method for packaging semiconductor of the present invention.
S21 provides a substrate 10, its have upper surface 100a and with the opposing lower surface 100b of upper surface 100a, comprise photosensitive area 12 on the substrate 10, and the weld pad 11 that electrically connects with photosensitive area 12.
S22 provides a temporary base 202, spin coating one thin adhesion glue 201 on this temporary base 202, and through photoetching process formation one obstruct wall, this intercepts and forms a receiving space 21 between wall and the temporary base 202, this receiving space 21 can hold photosensitive area 12 at least.
S23 is at obstruct wall surface attachment one adhesive that forms, and this temporary base 202 is fitted on the upper surface 100a of substrate 10.
S24 then forms the hole 13 that exposes weld pad 11 from the lower surface 100b of substrate 10.
S25 forms the conducting medium 15 that electrically connects with weld pad 11 in hole 13.
S26 (is substrate 10 and temporary base Silicon Wafer in this execution mode; And employing wafer-level packaging technology) be cut into a plurality of chips; Promptly be to obtain encapsulating structure disconnected from each other; And, respectively substrate on a plurality of chips 10 and temporary base 202 are peeled off through heated adhesive, obtain final chip-packaging structure.
The difference that can find out second execution mode and first execution mode of the method for packaging semiconductor of introducing of the present invention from above here only is to hold on the temporary base generation type of the receiving space 21 of photosensitive area; So, other identical or similar processing step do not done gives unnecessary details at this.
The present invention is through above-mentioned execution mode; Have following beneficial effect: through be provided with on the temporary base one can hold photosensitive area on the substrate receiving space; Adhesive etc. is not contacted with photosensitive area; Avoid the follow-up injury that possibly cause photosensitive area that removes in the temporary base process, promoted the encapsulating structure performance, improved the yield of encapsulation.
Before removing temporary base and adhesive, earlier substrate cutting is obtained encapsulating structure disconnected from each other, will the external force influence of chip body be reduced, help further improving the performance of encapsulating structure.
Be to be understood that; Though this specification is described according to execution mode; But be not that each execution mode only comprises an independently technical scheme, this narrating mode of specification only is for clarity sake, and those skilled in the art should make specification as a whole; Technical scheme in each execution mode also can form other execution modes that it will be appreciated by those skilled in the art that through appropriate combination.
The listed a series of detailed description of preceding text only is specifying to feasibility execution mode of the present invention; They are not in order to restriction protection scope of the present invention, allly do not break away from equivalent execution mode or the change that skill of the present invention spirit done and all should be included within protection scope of the present invention.
Claims (11)
1. a method for packaging semiconductor is characterized in that, this method may further comprise the steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, comprise photosensitive area on the said substrate, and the weld pad that electrically connects with said photosensitive area;
One temporary base is provided, on said temporary base, forms receiving space, said receiving space can hold said photosensitive area at least;
Be formed with at said temporary base on the one side of receiving space adhesive is set, and it is fitted on the upper surface of said substrate, said photosensitive area is positioned at said receiving space;
Lower surface from said substrate forms the hole that exposes said weld pad;
In described hole, form the conducting medium that electrically connects with said weld pad;
Said substrate and said temporary base are peeled off.
2. method for packing according to claim 1 is characterized in that, said " in described hole, forming the conducting medium that electrically connects with said weld pad " step specifically comprises:
On the sidewall of described hole and bottom, form insulating barrier;
Remove insulating barrier on the described hole bottom to expose said weld pad;
On the sidewall of described hole and bottom, form the conducting medium that electrically connects with said weld pad.
3. method for packing according to claim 1 is characterized in that, this method also comprises:
On the lower surface of said substrate, form insulating barrier, and the conducting medium in the described hole is extended on the insulating barrier of bottom surface section;
On the conducting medium of the lower surface of said substrate, form welding resisting layer;
On said welding resisting layer, form the opening that part exposes said conducting medium, and form pedestal or the contact array that electrically connects with said conducting medium through said opening.
4. method for packing according to claim 1 is characterized in that, specifically comprises " said substrate and said temporary base are peeled off ": cutting said substrate and said temporary base is a plurality of chips; Respectively said substrate on a plurality of chips and said temporary base are peeled off.
5. method for packaging semiconductor according to claim 1 is characterized in that, described hole near the bore of the opening of said base lower surface bore near the opening of said upper surface of base plate greater than described hole.
6. a method for packaging semiconductor is characterized in that, this method may further comprise the steps:
One substrate is provided, it comprise upper surface and with the opposing lower surface of upper surface, comprise photosensitive area on the said substrate, and the weld pad that electrically connects with said photosensitive area;
One temporary base is provided, and on said temporary base, forms the obstruct wall, said obstruct wall and said temporary base form a receiving space, and said receiving space can hold said photosensitive area at least;
On the obstruct wall of said formation, adhesive is set, and said temporary base is manufactured with the one side that intercepts wall is fitted on the upper surface of said substrate, said photosensitive area is positioned at said receiving space;
Lower surface from said substrate forms the hole that exposes said weld pad;
In described hole, form the conducting medium that electrically connects with said weld pad;
Said substrate and said temporary base are peeled off.
7. method for packing according to claim 6 is characterized in that, said " forming the obstruct wall on the said temporary base " step specifically comprises: spin coating one adhesion glue on said temporary base, and the said adhesion glue of photoetching forms said obstruct wall.
8. method for packing according to claim 6 is characterized in that, said " in described hole, forming the conducting medium that electrically connects with said weld pad " step specifically comprises:
On the sidewall of described hole and bottom, form insulating barrier;
Remove insulating barrier on the described hole bottom to expose said weld pad;
On the sidewall of described hole and bottom, form the conducting medium that electrically connects with said weld pad.
9. method for packing according to claim 6 is characterized in that, this method also comprises:
On the lower surface of said substrate, form insulating barrier, and the conducting medium in the described hole is extended on the insulating barrier of bottom surface section;
On the conducting medium of the lower surface of said substrate, form welding resisting layer;
On said welding resisting layer, form the opening that part exposes said conducting medium, and form pedestal or the contact array that electrically connects with said conducting medium through said opening.
10. method for packing according to claim 6 is characterized in that, specifically comprises " said substrate and said temporary base are peeled off ": cutting said substrate and said temporary base is a plurality of chips; Respectively said substrate on a plurality of chips and said temporary base are peeled off.
11. method for packing according to claim 6 is characterized in that, described hole near the bore of the opening of said base lower surface bore near the opening of said upper surface of base plate greater than described hole.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100646861A CN102610624A (en) | 2012-03-13 | 2012-03-13 | Method for packaging semiconductor |
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| CN104637967A (en) * | 2015-02-13 | 2015-05-20 | 苏州晶方半导体科技股份有限公司 | Packaging method and packaging structure |
| CN105226074A (en) * | 2015-10-28 | 2016-01-06 | 苏州晶方半导体科技股份有限公司 | Image sensor chip packaging structure and packaging method |
| CN105428378A (en) * | 2015-11-27 | 2016-03-23 | 苏州晶方半导体科技股份有限公司 | Image sensor chip package structure and package method thereof |
| US20160218133A1 (en) * | 2015-01-28 | 2016-07-28 | Xintec Inc. | Photosensitive module and method for forming the same |
| CN105826339A (en) * | 2015-01-28 | 2016-08-03 | 精材科技股份有限公司 | Photosensitive module and manufacturing method thereof |
| WO2017071427A1 (en) * | 2015-10-28 | 2017-05-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
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| US9966400B2 (en) | 2015-01-28 | 2018-05-08 | Xintec Inc. | Photosensitive module and method for forming the same |
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| US10529758B2 (en) | 2015-02-13 | 2020-01-07 | China Wafer Level Csp Co., Ltd. | Packaging method and packaging structure |
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| JP2018535549A (en) * | 2015-10-28 | 2018-11-29 | 蘇州晶方半導体科技股▲分▼有限公司Ｃｈｉｎａ Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｓｐ Ｃｏ．， Ｌｔｄ． | Image detection chip mounting structure and mounting method |
| WO2017071427A1 (en) * | 2015-10-28 | 2017-05-04 | 苏州晶方半导体科技股份有限公司 | Image sensing chip packaging structure and packaging method |
| CN105428378A (en) * | 2015-11-27 | 2016-03-23 | 苏州晶方半导体科技股份有限公司 | Image sensor chip package structure and package method thereof |
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