[go: up one dir, main page]

CN102605359A - 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺 - Google Patents

化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺 Download PDF

Info

Publication number
CN102605359A
CN102605359A CN2011101925171A CN201110192517A CN102605359A CN 102605359 A CN102605359 A CN 102605359A CN 2011101925171 A CN2011101925171 A CN 2011101925171A CN 201110192517 A CN201110192517 A CN 201110192517A CN 102605359 A CN102605359 A CN 102605359A
Authority
CN
China
Prior art keywords
palladium
coating
gold
pad
copper wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2011101925171A
Other languages
English (en)
Inventor
林明宏
刘昆正
李英杰
邱国宾
郭蔡同
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Uyemura Co Ltd
Original Assignee
Taiwan Uyemura Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW100102660A external-priority patent/TW201233279A/zh
Priority claimed from TW100102661A external-priority patent/TW201233280A/zh
Application filed by Taiwan Uyemura Co Ltd filed Critical Taiwan Uyemura Co Ltd
Publication of CN102605359A publication Critical patent/CN102605359A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/31Coating with metals
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/1601Process or apparatus
    • C23C18/1633Process of electroless plating
    • C23C18/1646Characteristics of the product obtained
    • C23C18/165Multilayered product
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/16Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
    • C23C18/52Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating using reducing agents for coating with metallic material not provided for in a single one of groups C23C18/32 - C23C18/50
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C18/00Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
    • C23C18/54Contact plating, i.e. electroless electrochemical plating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164Palladium [Pd] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644Gold [Au] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45163Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/45164Palladium (Pd) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/4554Coating
    • H01L2224/45565Single coating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48844Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00011Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01015Phosphorus [P]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/12All metal or with adjacent metals
    • Y10T428/12493Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12535Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Organic Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • General Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electrochemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemically Coating (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Wire Bonding (AREA)

Abstract

本发明提供化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺。此化学钯金镀膜,其位于一焊垫上,包含有一位于焊垫上的钯镀层;与一位于钯镀层上的金镀层。此化学钯金镀膜以及打线接合于金镀层上的铜线或钯铜线成为封装结构。本发明亦提供此化学钯金镀膜的制作方法以及此封装结构的封装工艺。本发明以钯镀层来取代已知镍层的使用,以提升铜或铜钯线与焊垫的打线接合强度。

Description

化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺
技术领域
本发明有关焊垫表面保护层,特别是化学钯金镀膜所成保护层,亦有关其制作方法。此外,本发明亦有关封装工艺及其结构,特别是铜线或钯铜线的封装工艺及其结构。 
背景技术
在晶圆、液晶显示器基板、陶瓷基板、铝基板、IC载板与印刷电路板等电子工业零件的封装工艺上,需于构成电性连接的焊垫表面上形成一化镍金层,以提升打线与焊垫在焊接上的接合性与耐蚀性。但在焊垫上形成镍层后进行无电解镀金以形成金层时,镍与金的取代反应会对镍层中所析出粒子的粒界部分进行强烈的选择性攻击,导致金层下方形成残缺部分而产生蚀孔,相对的镍层将变的脆弱,在焊接时将无法确保充分的焊接接合强度。 
因此,化镍钯金工艺被提出,以经由钯层来解决金对镍强烈攻击现象,化镍钯金工艺虽然可以解决上述问题,但镍层的存在却导致硬度增加,使得后续无法顺利打线接合铜线或者铜钯线。 
有鉴于此,本发明针对上述已知技术的缺失,提出一种崭新的化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺,以有效克服上述的这些问题。 
发明内容
本发明的主要目的在于提供化学钯金镀膜结构及其制作方法,其能应用于较为低阶但线路密集度高的电子产品封装工艺上。 
本发明的另一目的在于提供化学钯金镀膜结构及其制作方法,本发明的结构及其制作方法没有使用镍层,能提升铜线或铜钯线与焊垫的接合可靠度,并可减低成 本。 
本发明的另一主要目的在于提供一种将上述化学钯金镀膜结构与铜线或钯铜线接合的封装结构及其工艺,本发明的结构及其制作工艺没有使用镍层,能提升铜线或铜钯线与焊垫的接合可靠度,并可减低成本。 
本发明的另一目的在于提供一种铜线或钯铜线的封装工艺及其结构,其能应用于较为低阶但线路密集度高的电子产品封装工艺上。 
本发明的另一目的在于提供铜线或钯铜线封装工艺产品一种可作业的新表面处理。
为达上述的目的,本发明提供一种化学钯金镀膜结构,其位于一焊垫上,此化学钯金镀膜包含有一位于焊垫上的钯镀层;以及一位于钯镀层上的金镀层。 
本发明还提供一种化学钯金镀膜的制作方法,包括提供一焊垫,于焊垫上形成一钯镀层,以及于钯镀层上形成一金镀层。较佳地,钯镀层为利用置换反应于焊垫上形成的置换型钯镀层,更佳地,再于置换型钯镀层上利用还原反应形成还原型钯镀层。较佳地,金镀层为利用置换型、还原型或者半置换半还原型反应于钯镀层上形成。 
本发明还提供另一种化学钯金镀膜的制作方法,包括提供一焊垫,使用一兼具触媒钯与化学钯效用的溶液同时进行置换与还原反应,以于焊垫上形成一钯镀层。最后,利用置换型、还原型或者半置换半还原型反应于钯镀层上形成一金镀层。 
本发明还提供一种上述化学钯金镀膜结构与铜线或钯铜线接合的封装结构,其包含有一焊垫;一位于焊垫上的钯镀层;一位于钯镀层上的金镀层;以及一打线接合于金镀层上的铜线或钯铜线。 
本发明还提供一种铜线或钯铜线的封装工艺,其步骤包含有先提供一焊垫;接续,于焊垫上形成一钯镀层;然后,于钯镀层上形成一金镀层;最后,于金镀层上打线接合一铜线或钯铜线。 
其中,上述的钯镀层可以是利用置换反应、或者置换反应与还原反应二阶段来形成,或者是使用单一溶液同步进行置换与还原反应所形成。 
下面将藉由具体实施例的详细说明,以便于更容易了解本发明的目的、技术内容、特点及其所达成的功效。 
在本发明说明中,除非另有不同表明,否则所有的量,包括用量、百分比、份 数、及比例,都理解以″约″字修饰,且各数量皆无意为任何有效位数的表示。 
除非另有不同表明,否则冠词“一”意图表示“一或多”。“包含”与“包括”等词意图作概括性表示,而且表示除所列成份、组件外还可有额外的成份、组件。 
附图说明
图1是本发明的化学钯金镀膜的第一种制作步骤流程图。 
图2是图1的步骤所制得的化学钯金镀膜的结构示意图。 
图3是本发明的化学钯金镀膜的第二种制作步骤流程图。 
图4是图3的步骤所制得的化学钯金镀膜的结构示意图。 
图5是本发明的化学钯金镀膜的第三种制作步骤流程图。 
图6是图5的步骤所制得的化学钯金镀膜的结构示意图。 
图7是本发明的铜线或钯铜线的封装结构的示意图。 
图8是本发明的铜线或钯铜线的封装工艺的第一种工艺步骤流程图。 
图9是图8的步骤所制得的铜线或钯铜线的封装结构示意图。 
图10是本发明的铜线或钯铜线的封装工艺的第二种工艺步骤流程图。 
图11是图10的步骤所制得的铜线或钯铜线的封装结构示意图。 
图12是本发明的铜线或钯铜线的封装工艺的第三种工艺步骤流程图。 
图13是图12的步骤所制得的铜线或钯铜线的封装结构示意图。 
主要组件符号说明: 
10:焊垫 
12:置换型钯镀层 
14:还原型钯镀层 
16:金镀层 
18:置换型/还原型钯镀层 
20:钯镀层 
30:封装结构 
32:铜线或钯铜线 
具体实施方式
本发明揭示一种化学钯金镀膜结构及其制作方法,其针对欲进行铜线或铜钯线封装工艺的焊垫表面进行表面处理,前述焊垫较佳为铜,以直接在焊垫表面依序形成一致密性高的钯镀层与一金镀层,在无使用镍层的情况下,增进后续铜线或铜钯线的打线接合强度。 
上述钯镀层可以是利用电化学反应所形成。钯镀层的材质可以是纯钯或者是钯磷合金。本发明的化学钯金镀膜结构的制作方法有下列三种: 
参阅图1,其是第一种制作方法的步骤流程图。首先如步骤S1所述,提供一焊垫10。接着,如步骤S2所述,进行置换反应于焊垫10表面形成一置换型钯镀层12。再如步骤S3所述,以还原反应增厚形成一位于置换型钯镀层12上的还原型钯镀层14。最后,如步骤S4所述,以置换型或还原型或半置换半还原型反应形成一覆盖于还原型钯镀层14上的金镀层16,形成如图2所示的结构。 
在此方式下,置换型钯镀层12加上还原型钯镀层14的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米;金镀层16的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米。 
参阅图3,其是第二种制作方法的步骤流程图。首先,如步骤S1所述,提供一焊垫10。接着,如步骤S12所述,利用单一溶液来进行作业,此溶液兼具触媒钯与化学钯效用,因此,可同时进行置换及还原反应于焊垫上形成一钯镀层18。最后,如步骤S13所述,再以置换型或还原型或半置换半还原型反应于钯镀层18上形成一金镀层16,形成如图4所示的结构。 
在此方式下,钯镀层的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米;金镀层的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米。 
参阅图5,其是第三种制作方法的步骤流程图。此方法相较于上述第一种方法,其实就是省略形成还原型钯镀层的步骤S3。第三种制作方法的步骤包括,如步骤S1所述,提供一焊垫10。接着,如步骤S2所述,先进行置换反应于焊垫10表面形成一置换型钯镀层12。再如步骤S23所述,以置换型或还原型或半置换半还原型反应形成一覆盖于置换型钯镀层12上的金镀层16,形成如图6所示的结构。 
在此方式下,置换型钯镀层12的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米;金镀层16的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米。 
上述三种制作方法各步骤的操作温度大约在25℃~95℃的范围,酸碱值约在pH 4~9之间。 
由上述的图2、4与6,可知本发明的化学钯金镀膜结构包含有一焊垫10;一位于焊垫上的钯镀层12及选择性的14,或者18;以及一位于此钯镀层上的金镀层16。 
参阅图7,其本是发明的铜线或钯铜线的封装结构示意图。如图所示,本发明的铜线或钯铜线的封装结构30,包含有一焊垫10,其材质可以为铜;一位于焊垫10上且紧邻焊垫10的钯镀层20;一位于钯镀层20上且紧邻钯镀层20的金镀层16;以及一接合于金镀层16上,以与焊垫10形成电性连接的铜线或者钯铜线32。 
上述的钯镀层20的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米;金镀层16的厚度为0.03~0.2微米,亦可为0.03~0.07微米,较佳为0.06~0.12微米,亦佳为0.09~0.2微米。 
在工艺上,本发明于欲进行铜线或铜钯线封装工艺的焊垫10表面先进行表面处理,以直接在焊垫10表面依序形成一致密性高的钯镀层20与一金镀层16,以在无使用镍层的情况下,增加接合于金镀层16上的铜线或铜钯线32的打线接合强度。 
本发明在形成钯镀层20与金镀层16时各步骤的操作温度大约在25℃~95℃的范围,酸碱值是在约pH4~9之间。 
本发明的铜线或钯铜线32的封装工艺可依照钯镀层20的制作方式进一步区分为下列三种: 
请参阅图8,其是第一种封装方法的步骤流程图,包括上述第一种化学钯金镀膜结构的制作方法步骤S1、步骤S2、步骤S3、步骤S4,以及,如步骤S5所述,于焊垫10上的金镀层16打线接合一铜线或钯铜线32,形成如图9所示的结构。 
在此方式下,钯镀层20是由一置换型钯镀层12与还原型钯镀层14所组合而成。 
请参阅图10,其是第二种封装方法的步骤流程图,包括上述第二种化学钯金 镀膜结构的制作方法步骤S1、步骤S12、步骤S13,以及,如步骤S14所述,于焊垫10的金镀层16上打线接合一铜线或钯铜线32,形成如图11所示的封装结构。 
请参阅图12,其是第三种封装方法的步骤流程图,包括上述第三种化学钯金镀膜结构的制作方法步骤S1、步骤S2、步骤S23,以及,如步骤S24所述,于焊垫10的金镀层16上打线接合一铜线或钯铜线32,形成如图13所示的结构。 
本发明经由使用钯镀层来取代镍层的存在,以避免镍存在时所产生的各种问题,提供铜线或者铜钯线封装工艺产品一种可作业的新表面处理。而且,本发明技术的最佳施行范例是应用于较为低阶但线路密集度高的电子产品封装工艺上。因为低阶电子产品所需的回焊次数较低,因此铜原子的移动较少,并不会大幅度地扩散至钯镀层内。此外,当组件整体体积缩小且线路密集度高时,焊垫体积也会缩小,而本发明无使用镍层的特性上,有利于铜焊垫与铜线或钯铜线的打线,不仅不会影响可靠度,更可减低成本。 
以上仅为本发明的较佳实施例而已,并非用来限定本发明实施的范围。故所有依本发明权利要求书所述的特征及精神所为的均等变化或修饰,均应包括在本发明的保护范围内。 

Claims (26)

1.一种化学钯金镀膜结构,其位于一焊垫上,该化学钯金镀膜包含有:
一钯镀层,其位于该焊垫上;以及
一金镀层,其位于该钯镀层上。
2.如权利要求1的化学钯金镀膜结构,其特征在于,该钯镀层是利用置换型或置换型搭配还原型反应所形成,该金镀层是置换型、还原型或者半置换半还原型反应所形成。
3.一种化学钯金镀膜的制作方法,其步骤包含有:
提供一焊垫;
利用置换反应于该焊垫上形成一置换型钯镀层;以及
利用置换型、还原型或者半置换半还原型反应于该置换型钯镀层上形成一金镀层。
4.如权利要求3的方法,其特征在于,该焊垫的材质为铜,该置换型钯镀层的材质是纯钯或者是钯磷合金。
5.如权利要求3的方法,其特征在于,其在温度为25℃~95℃,酸碱值为pH4~9进行。
6.如权利要求3的方法,其特征在于,该置换型钯镀层的厚度为0.03~0.2微米,该金镀层的厚度为0.03~0.2微米。
7.如权利要求3的方法,其特征在于,其应用于低阶但线路密集度高的电子产品封装工艺。
8.如权利要求3的方法,其特征在于,在形成该金镀层前还包括一利用还原反应于该置换型钯镀层上形成一还原型钯镀层的步骤。
9.如权利要求8的方法,其特征在于,该置换型钯镀层的厚度加上该还原型钯镀层的厚度为0.03~0.2微米,该金镀层的厚度为0.03~0.2微米。
10.一种化学钯金镀膜的制作方法,其步骤包含有:
提供一焊垫;
使用一兼具触媒钯与化学钯效用的溶液同时进行置换与还原反应,以于该焊垫上形成一钯镀层;以及
利用置换型、还原型或者半置换半还原型反应于该钯镀层上形成一金镀层。
11.如权利要求10的方法,其特征在于,该焊垫的材质为铜,该钯镀层的材质是纯钯或者是钯磷合金。
12.如权利要求10的方法,其特征在于,其于温度为25℃~95℃,酸碱值为pH 4~9进行。
13.如权利要求10的方法,其特征在于,该钯镀层的厚度为0.03~0.2微米,该金镀层的厚度为0.03~0.2微米。
14.如权利要求10的方法,其特征在于,其应用于低阶但线路密集度高的电子产品封装工艺。
15.一种铜线或钯铜线的封装结构,其包含有:
一焊垫;
一钯镀层,其位于该焊垫上;
一金镀层,其位于该钯镀层上;以及
一铜线或钯铜线,其打线接合于该金镀层上。
16.如权利要求15的封装结构,其特征在于,该焊垫的材质为铜,该钯镀层的材质为纯钯或者是钯磷合金。
17.如权利要求15的封装结构,其特征在于,该钯镀层包含有一置换型钯镀层与一还原型钯镀层。
18.如权利要求15的封装结构,其特征在于,该钯镀层的厚度为0.03~0.2微米,该金镀层的厚度为0.03~0.2微米。
19.一种铜线或钯铜线的封装工艺方法,其包含有下列步骤:
提供一焊垫;
于该焊垫上形成一钯镀层;
于该钯镀层上形成一金镀层;以及
于该金镀层上打线接合一铜线或钯铜线。
20.如权利要求19的方法,其特征在于,于该焊垫上形成该钯镀层的步骤还包括有:
利用置换反应于该焊垫上先形成一置换型钯镀层;以及
利用还原反应于该置换型钯镀层上形成一还原型钯镀层。
21.如权利要求19的方法,其特征在于,该焊垫的材质为铜,该钯镀层的材质为纯钯或者是钯磷合金。
22.如权利要求19的方法,其特征在于,形成该钯镀层与该金镀层的步骤于温度为25℃~95℃、酸碱值为pH 4~9进行。
23.如权利要求19的方法,其特征在于,该钯镀层的厚度为0.03~0.2微米,该金镀层的厚度为0.03~0.2微米。
24.如权利要求19的方法,其特征在于,于该焊垫上形成该钯镀层的步骤是使用一兼具触媒钯与化学钯效用的溶液同时进行置换与还原反应所达成。
25.如权利要求19的方法,其特征在于,该金镀层是利用置换型、还原型或者半置换半还原型反应所形成。
26.如权利要求19的方法,其特征在于,于该焊垫上形成该钯镀层的步骤是使用置换反应所达成。
CN2011101925171A 2011-01-25 2011-06-28 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺 Pending CN102605359A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
TW100102661 2011-01-25
TW100102660 2011-01-25
TW100102660A TW201233279A (en) 2011-01-25 2011-01-25 Copper or palladium-copper wire package process and structure thereof
TW100102661A TW201233280A (en) 2011-01-25 2011-01-25 Chemical palladium-gold plating film method

Publications (1)

Publication Number Publication Date
CN102605359A true CN102605359A (zh) 2012-07-25

Family

ID=46523109

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2011101925171A Pending CN102605359A (zh) 2011-01-25 2011-06-28 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺

Country Status (4)

Country Link
US (1) US20120186852A1 (zh)
JP (1) JP2012153974A (zh)
KR (1) KR20120086253A (zh)
CN (1) CN102605359A (zh)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104066267A (zh) * 2014-06-03 2014-09-24 深圳市创智成功科技有限公司 铜基材的化学镀层结构及其工艺
CN104867530A (zh) * 2014-02-26 2015-08-26 日立金属株式会社 导电性颗粒、导电性粉体、导电性高分子组合物及各向异性导电片
CN106574388A (zh) * 2014-08-14 2017-04-19 微软技术许可有限责任公司 具有经镀覆的电接触的电子设备
CN115011953A (zh) * 2022-06-21 2022-09-06 深圳芯源新材料有限公司 一种复杂结构自适应的可焊接柔性金属垫片及其制备方法

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2887779A1 (en) 2013-12-20 2015-06-24 ATOTECH Deutschland GmbH Silver wire bonding on printed circuit boards and IC-substrates
JP2015142240A (ja) * 2014-01-28 2015-08-03 セイコーエプソン株式会社 量子干渉ユニット、量子干渉装置、原子発振器、電子機器および移動体
JP6329589B2 (ja) 2016-06-13 2018-05-23 上村工業株式会社 皮膜形成方法
JP6754152B1 (ja) * 2020-02-18 2020-09-09 日本高純度化学株式会社 めっき積層体
KR102675931B1 (ko) 2021-05-25 2024-06-19 주식회사 나노코어 와이어 본딩 패드, 이를 포함하는 카메라 모듈 및 와이어 본딩 패드 제조방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006063386A (ja) * 2004-08-26 2006-03-09 Tokyo Electron Ltd 半導体装置の製造方法
JP2007031740A (ja) * 2005-07-22 2007-02-08 Shinko Electric Ind Co Ltd 電子部品及びその製造方法
CN1956632A (zh) * 2005-10-25 2007-05-02 三星电机株式会社 用于镀覆印刷电路板的方法以及由此制造的印刷电路板
CN101668880A (zh) * 2007-04-27 2010-03-10 日立化成工业株式会社 连接端子、使用了连接端子的半导体封装件及半导体封装件的制造方法

Family Cites Families (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1003524B (zh) * 1985-10-14 1989-03-08 株式会社日立制作所 无电浸镀金溶液
US4674671A (en) * 1985-11-04 1987-06-23 Olin Corporation Thermosonic palladium lead wire bonding
JPH05327187A (ja) * 1992-05-18 1993-12-10 Ishihara Chem Co Ltd プリント配線板及びその製造法
US5882736A (en) * 1993-05-13 1999-03-16 Atotech Deutschland Gmbh palladium layers deposition process
JP2885113B2 (ja) * 1995-01-30 1999-04-19 日本電気株式会社 印刷配線板およびその製造方法
KR0177395B1 (ko) * 1995-04-27 1999-05-15 문정환 반도체소자를 칩 상태로 장착시켜서 된 전자회로 보드 및 그 제조방법
US6086946A (en) * 1996-08-08 2000-07-11 International Business Machines Corporation Method for electroless gold deposition in the presence of a palladium seeder and article produced thereby
US6180523B1 (en) * 1998-10-13 2001-01-30 Industrial Technology Research Institute Copper metallization of USLI by electroless process
US6221763B1 (en) * 1999-04-05 2001-04-24 Micron Technology, Inc. Method of forming a metal seed layer for subsequent plating
US6521532B1 (en) * 1999-07-22 2003-02-18 James A. Cunningham Method for making integrated circuit including interconnects with enhanced electromigration resistance
US6361823B1 (en) * 1999-12-03 2002-03-26 Atotech Deutschland Gmbh Process for whisker-free aqueous electroless tin plating
US20010033020A1 (en) * 2000-03-24 2001-10-25 Stierman Roger J. Structure and method for bond pads of copper-metallized integrated circuits
DE60109339T2 (de) * 2000-03-24 2006-01-12 Texas Instruments Incorporated, Dallas Verfahren zum Drahtbonden
TWI287282B (en) * 2002-03-14 2007-09-21 Fairchild Kr Semiconductor Ltd Semiconductor package having oxidation-free copper wire
US20050001316A1 (en) * 2003-07-01 2005-01-06 Motorola, Inc. Corrosion-resistant bond pad and integrated device
US7078796B2 (en) * 2003-07-01 2006-07-18 Freescale Semiconductor, Inc. Corrosion-resistant copper bond pad and integrated device
EP1813696B1 (en) * 2004-11-15 2018-12-26 JX Nippon Mining & Metals Corporation Electroless gold plating solution
JP4792045B2 (ja) * 2005-01-12 2011-10-12 ユミコア ガルヴァノテヒニク ゲゼルシャフト ミット ベシュレンクテル ハフツング パラジウム層を堆積する方法およびこのためのパラジウム浴
US20060189131A1 (en) * 2005-02-24 2006-08-24 Taiwan Semiconductor Manufacturing Co., Ltd. Composition and process for element displacement metal passivation
KR100726241B1 (ko) * 2005-05-02 2007-06-11 삼성전기주식회사 금-구리 층을 포함하는 도전성 기판, 모터, 진동모터 및전기 접점용 금속 단자
WO2007003223A1 (en) * 2005-07-04 2007-01-11 Freescale Semiconductor, Inc. Method and apparatus for forming a noble metal layer, notably on inlaid metal features
JP4844716B2 (ja) * 2005-09-27 2011-12-28 上村工業株式会社 無電解パラジウムめっき浴
JP5013077B2 (ja) * 2007-04-16 2012-08-29 上村工業株式会社 無電解金めっき方法及び電子部品
CN101578394B (zh) * 2007-07-31 2011-08-03 日矿金属株式会社 通过无电镀形成金属薄膜的镀敷物及其制造方法
JP2009043793A (ja) * 2007-08-07 2009-02-26 Panasonic Corp 半導体装置、およびその半導体装置の製造方法
US7939949B2 (en) * 2007-09-27 2011-05-10 Micron Technology, Inc. Semiconductor device with copper wirebond sites and methods of making same
US20090246911A1 (en) * 2008-03-27 2009-10-01 Ibiden, Co., Ltd. Substrate for mounting electronic components and its method of manufacture
US7906377B2 (en) * 2008-12-24 2011-03-15 Via Technologies, Inc. Fabrication method of circuit board
TWI380423B (en) * 2008-12-29 2012-12-21 Advanced Semiconductor Eng Substrate structure and manufacturing method thereof
US20100200981A1 (en) * 2009-02-09 2010-08-12 Advanced Semiconductor Engineering, Inc. Semiconductor package and method of manufacturing the same
US8528200B2 (en) * 2009-12-18 2013-09-10 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
JP5552934B2 (ja) * 2010-07-20 2014-07-16 Tdk株式会社 被覆体及び電子部品
EP2469992B1 (en) * 2010-12-23 2015-02-11 Atotech Deutschland GmbH Method for obtaining a palladium surface finish for copper wire bonding on printed circuit boards and IC-substrates
US8889995B2 (en) * 2011-03-03 2014-11-18 Skyworks Solutions, Inc. Wire bond pad system and method
KR20130007022A (ko) * 2011-06-28 2013-01-18 삼성전기주식회사 인쇄회로기판 및 이의 제조방법
KR101310256B1 (ko) * 2011-06-28 2013-09-23 삼성전기주식회사 인쇄회로기판의 무전해 표면처리 도금층 및 이의 제조방법
CN103137570B (zh) * 2011-11-29 2016-02-10 先进封装技术私人有限公司 基板结构、半导体封装元件及基板结构的制造方法
WO2013095405A1 (en) * 2011-12-20 2013-06-27 Intel Corporation Enabling package-on-package (pop) pad surface finishes on bumpless build-up layer (bbul) package
US20130233602A1 (en) * 2012-03-09 2013-09-12 Ting-Hao Lin Surface treatment structure of circuit pattern
KR101998340B1 (ko) * 2012-07-18 2019-07-09 삼성전자주식회사 전력 소자 모듈 및 그 제조 방법

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006063386A (ja) * 2004-08-26 2006-03-09 Tokyo Electron Ltd 半導体装置の製造方法
JP2007031740A (ja) * 2005-07-22 2007-02-08 Shinko Electric Ind Co Ltd 電子部品及びその製造方法
CN1956632A (zh) * 2005-10-25 2007-05-02 三星电机株式会社 用于镀覆印刷电路板的方法以及由此制造的印刷电路板
CN101668880A (zh) * 2007-04-27 2010-03-10 日立化成工业株式会社 连接端子、使用了连接端子的半导体封装件及半导体封装件的制造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867530A (zh) * 2014-02-26 2015-08-26 日立金属株式会社 导电性颗粒、导电性粉体、导电性高分子组合物及各向异性导电片
CN104066267A (zh) * 2014-06-03 2014-09-24 深圳市创智成功科技有限公司 铜基材的化学镀层结构及其工艺
CN106574388A (zh) * 2014-08-14 2017-04-19 微软技术许可有限责任公司 具有经镀覆的电接触的电子设备
CN115011953A (zh) * 2022-06-21 2022-09-06 深圳芯源新材料有限公司 一种复杂结构自适应的可焊接柔性金属垫片及其制备方法

Also Published As

Publication number Publication date
KR20120086253A (ko) 2012-08-02
JP2012153974A (ja) 2012-08-16
US20120186852A1 (en) 2012-07-26

Similar Documents

Publication Publication Date Title
CN102605359A (zh) 化学钯金镀膜结构及其制作方法、铜线或钯铜线接合的钯金镀膜封装结构及其封装工艺
CN104024473B (zh) 布线基板及布线基板的制造方法
JP2002124533A (ja) 電極材料、半導体装置及び実装装置
TW201343309A (zh) 接合方法、接合結構體及其製造方法
JP4130508B2 (ja) 半田接合方法及び電子装置の製造方法
TW201246414A (en) Method for producing package substrate for mounting semiconductor element, package substrate for mounting semiconductor element, and semiconductor package
TWI403596B (zh) 半導體封裝用之銅合金線
CN103531485B (zh) 基板结构的制作方法
CN102244062B (zh) 半导体封装结构以及半导体封装工艺
CN104066267A (zh) 铜基材的化学镀层结构及其工艺
CN102246607B (zh) 电极连接结构、用于电极连接结构的导电粘合剂、以及电子装置
JP2004047510A (ja) 電極構造体およびその形成方法
CN106793484B (zh) 金属导体结构及线路结构
CN106341943A (zh) 线路板及其制作方法
JPH07263493A (ja) チップマウント方法
JP2008028069A (ja) 外部接合電極付き基板およびその製造方法
CN103681375B (zh) 四方平面无导脚半导体封装件及其制法
TWI351740B (en) Electronic part
JP2002115076A (ja) 置換金めっき方法
TWI463021B (zh) 具電磁遮蔽之無鍍層銅線及其製造方法
JP2553265B2 (ja) Tab用テープキャリア
TWI236756B (en) Flip-chip bonding process and package process
TWI281700B (en) Method and device for enhancing solderability
TW550769B (en) Wafer level package and its manufacturing method
TW201636454A (zh) 化學鈀銀鍍膜的製作方法及其結構

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20120725