CN102597912B - Coordinating device and application break events for platform power saving - Google Patents
Coordinating device and application break events for platform power saving Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
- G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/542—Event management; Broadcasting; Multicasting; Notifications
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Abstract
Systems and methods of managing break events may provide for detecting a first break event from a first event source and detecting a second break event from a second event source. In one example, the event sources can include devices coupled to a platform as well as active applications on the platform. Issuance of the first and second break events to the platform can be coordinated based on at least in part runtime information associated with the platform.
Description
Technical field
Embodiment relates generally to the management of platform interrupt (break) event.More particularly, embodiment relates to the issue coordinated from the not interrupt event of homology and saves to strengthen platform power.
Embodiment
Embodiment can provide a kind of method, wherein detects the first interrupt event from the first event source and the second interrupt event from second event source.The method can also be provided to and be at least partly based on the issue that information working time be associated with platform coordinates the first and second interrupt events of this platform.
Other embodiments can comprise the computer-readable recording medium with instruction set, COMPUTER DETECTION can be impelled from the first interrupt event of the first event source if this instruction set is executed by processor and detects from second interrupt event in second event source.These instructions can also impel computing machine to coordinate the issue of the first and second interrupt events of this platform at least in part based on information working time be associated with platform.
In addition, embodiment can comprise the device with I/O (IO) module, this input/output module have for detect from the first event source the first interrupt event and detect from the logic of second interrupt event in second event source.Described logic can also coordinate the issue of the first and second interrupt events of this platform at least in part based on information working time be associated with platform.
Embodiment can also comprise the system of I/O (IO) module having the first event source, second event source, processor and be coupled to this processor.I/O module can have for detect from the first event source the first interrupt event and detect from the logic of second interrupt event in second event source.In addition, described logic can coordinate the issue of the first and second interrupt events of this system at least in part based on information working time be associated with this system.
Forward Fig. 1 to now, it illustrates the multiple interrupt events 10 (10a-10f) from not homology (such as, power management entity) before and after the issue of the interrupt event 10 coordinating platform.In the example shown, at moment t
1ask I/O (IO) the event 10a (such as, look-at-me (interrupt)) from equipment (such as mouse), and at moment t
2ask the timer event 10b from the applications active operated on platform.In addition, can at moment t
3ask a series of IO event 10c from another equipment (such as network interface unit (NIC)).As will be discussed in more detail like that, can by the merge cells being arranged on NIC or be arranged in central position by IO event 10c grouped by itself to together.Can also at moment t
4ask the IO event 10d from audio frequency apparatus.In addition, example shown shows respectively at moment t
5and t
6detect timer event 10e and 10f from applications active.In their original state, interrupt event 10 may have the time overview that will platform stoped in the period extended to enter some power save state.
Therefore, the issue of the interrupt event 10 of platform can be coordinated, can power consumption be reduced to make this platform.Such as, the shown IO event 10a from mouse is merely deferred until the moment t after delay
1d, so that its can with can moment t after a delay
2dthe issue of the application program timer event 10b be published aligns.In another example, timer event 10b can be not ductile event.In this case, IO event 10a can be delayed by, and timer event 10b can as dispatch be published.In either case, the idle period 12 of prolongation can be produced, wherein due to the period 12 of this prolongation, platform can enter darker power save state (such as quickly, ACPI/ ACPI specification, ACPI specification, edition 4 .0, on June 16th, 2009, low power state) and keep the longer period.In addition, difference moment t after a delay
3dand t
4dplace, the IO event 10c from NIC can align with the IO event 10d from audio frequency apparatus, to produce the period 14 that another extends.Similarly, application program timer event 10e and 10f can be delayed to moment t respectively
5dand t
6d, this can cause the period 16 extended.In brief, the period 12,14,16 of prolongation can make it possible to realize the platform power saving of enhancing and longer battery life.
Fig. 2 shows interrupt event administrative unit (BMU) 18, and this interrupt event administrative unit 18 can detect interrupt event 20 and 24 they is aligned to the interrupt event after coordination 22 based on information working time be associated with platform/OS (operating system) 26 at least in part.BMU 18 can be implemented in the module of platform 26, the system control unit (SCU) of such as mobile internet device (MID) platform or the platform controller center (PCH) of laptop computer platform.In fact, BMU18 can use slightly different interface and actualizing technology to reside in operating system (OS) kernel spacing, or in the user space resident.In the example shown, information 24 working time self can be obtained from the source 28 of interrupt event 20 and platform 26.Such as, QoS (service quality) specification of the maximum delay time for identifying one or more IO event can be comprised from information 24 equipment being coupled to this platform obtains working time.In addition, the delay ability characteristics of one or more timer event can be identified from information 24 application program obtains working time.Such as, if timer event is not ductile, then BMU 18 can attempt other interrupt events and this not ductile timer event to align.Otherwise BMU 18 can managing timer event save and performance to realize optimal platform power.
By way of example, if the every 50ms of application requests timer event occurs once, and can be deferred to the maximum frequency of every 100ms, then BMU 18 can when platform 26 is relatively inactive every 100ms shot timers event.But if platform 26 becomes more active because of the interrupt event of other sources generation, then the issue of timer event can change to 50ms by BMU 18, to realize better application program capacity, and does not have a negative impact to power consumption.
In addition, platform 26 form that can interrupt averaging time, performance requirement able to programme etc. with low power state to provide working time information 24.Low power state interrupts platform 26 can being indicated should to rest in specific low power state to compensate/to repay and the time quantum entering and leave any power cost overhead that this low power state is associated averaging time.As will be discussed in more detail below, BMU 18 can use low power state to interrupt determining averaging time the retention time of each interrupt event be delayed by.In this, when the retention time becomes more much longer than interruption averaging time, the benefit that power is saved can decline fast, and performance can obviously worsen simultaneously.Therefore, BMU 18 can determine the rational retention time based on interruption averaging time and desired performance.
Performance requirement able to programme can be defined by the user of platform 26.Therefore, if user likes higher performance, then the retention time can be adjusted to shorter value downwards to provide the performance responding faster and improve (lose some power potentially and save chance) simultaneously.On the other hand, if user requires longer battery life, then the retention time can be configured to relative longer value to provide more chance to remain in lower power state to platform 26.
Forward Fig. 3 to now, it illustrates the illustrative methods 30 of the issue coordinating interrupt event.The method 30 can to use circuit engineering (such as ASIC, complementary metal oxide semiconductor (CMOS) (CMOS) or transistor-transistor logic (TTL) technology) the hardware of fixed function realize, can be embodied as and be stored in storer (such as random access memory (RAM) by executive software, ROM (read-only memory) (ROM), programming ROM (PROM), flash memory etc.) machine or computer-readable recording medium in firmware and/or logical order collection, or realize with their combination in any.Processing block 32 for collecting information working time from equipment, application program and platform, and determines the retention time based on information working time.As already noted, the determination of retention time can consider that low-power interrupts averaging time and the maximum delay time of performance requirement able to programme and IO event and the delay ability characteristics of timer event.
If interrupt event detected at frame 34, then can determine whether the retention time expires at frame 36 place.If no, then this interrupt event can be postponed at frame 38 place.Depend on environment, the delay of interrupt event can be realized in a number of different manners.Such as, interrupt event can be placed in queue, wherein this queue can be configured (collocate) by BMU 18 (Fig. 2), can be configured by the equipment issuing this interrupt event in the merge cells be associated with this equipment, etc.In fact, if interrupt event and management transaction are (such as, DMA/ direct memory access (DMA)) bus be associated, then can by not declaring that (de-assert) PCIe (high-speed peripheral parts interconnected) OBFF (chance buffering refresh/fill) signal should not be used to postpone interrupt event with notification source equipment PCIe bus.
If not ductile interrupt event detected at frame 40 or determine that the retention time expires at frame 36, then can discharge/issue all interrupt events be delayed by platform at frame 42.Shown frame 44 is for dispatching next retention time based on information working time collected.As already noted, dynamically the retention time can be regulated.At frame 46, this next retention time can be notified to platform power management unit.
Fig. 4 shows system 48, wherein BMU 50 is coupled to the processor/platform 52 receiving various interrupt event from application program timer 54 and equipment 56 (56a-56c), and wherein interrupt event can make processor/platform 52 leave (or entry deterrence) one or more low power state.In the example shown, merge cells 58 can be used in by such as by otherwise the multiple of multiple interrupt event can be caused to be grouped into the quantity that single interrupt event reduces interrupt event.Therefore, merge cells 58 is useful especially for communication facilities (such as network controller), although other equipment and application program also can be benefited from merging treatment.
From the initial phase of start-up time, merge cells 58 can obtain or may learn the systematic parameter of such as overlay strategy, equipment buffer size, the tolerance requirement of equipment stand-by period etc.These parameters can be used for determining the initial retention time based on equipment/application program by merge cells 58, and this retention time can adjust based on behavior working time subsequently when needed.Period operationally, merge cells 58 can follow the tracks of each equipment possessing interrupt event ability to determine this equipment whether reticent predetermined period (such as, α ms do not generate look-at-me) in the past.When occur this inactive time, the merge cells 58 of above-mentioned discussion can enter and keep interval (such as, β ms), and the look-at-me not from this particular source in this maintenance interval will by relaying to BMU 50 and/or processor/platform 52.The method can be implemented on the basis of each equipment/application program, and uses different parameters for each equipment/application program.In addition, some strategy can be used walk around (bypass) merge cells 58, such as high-performance/reference mode etc.
Although can realize merge cells 58 in equipment 56 and application program timer 54, by eliminating any requirement of aiming at the support interrupt event of equipment manufacturers, it can be more scalable for making them be arranged in BMU 50.Realize in BMU 50 merge cells 58 can comprise guarantee to keep the upper limit of timer β and equipment internal buffer size mutually compatibility to avoid buffer to overflow.In addition, inactive timer α can be configured to enough large value, to avoid too early expiring and any negative effect to maximum system performance.
Multiple different strategy can be used for merging timer adjustment.Such as, " static policies " can comprise system merging behavior being arranged (or based on OS overview) with user and like and be associated.Therefore, if user likes high-performance overview, then merging can be walked around with β=0.For the performance/power profile of equilibrium, the representative value of β=5ms can be selected.For the low-power mode with peak power saving, the representative value of β=10ms can be selected.Alternatively, based on the average interrupt event count observed on certain count cycle, can be used in wherein based on " dynamic strategy " of closed loop control β.Therefore, the method can make merging right and wrong interfering as much as possible, so that interrupt event behavior (on average) does not change significantly.From typical little β value, in relatively long time period (such as, second-time) upper quantity of observing from the interrupt event of individual equipment, and can increase β cumulatively until the par of event obviously changes.Depend on this change, β can reset to start from scratch and carry out adjusting or being reduced exponentially.
Forward Fig. 5 to now, it illustrates system 60.System 60 can be have computing function (such as, personal digital assistant/PDA, laptop computer), communication function (such as, intelligent wireless phone), the part of the mobile platform of imaging function, media play function or their combination in any (such as, mobile internet device/MID).In shown example, system 60 comprises processor 62, integrated memory controller (IMC) 74, I/O module 64, system storage 66, network controller (such as, network interface unit) 68, audio I/O device 72, solid-state disk (SSD) 70 and other controllers 80 one or more.As already noted, the processor 62 that can comprise the nucleus with one or several processor cores 76 can be considered based on performance and/or power management and use power management block (PMU) 78 that its core 76 and other system parts are placed in one or more activity and/or idle condition.
Shown I/O module 64 (being sometimes referred to as the south bridge of chipset or southern aggregate) is as main equipment and communicate with network controller 68, this network controller 68 can (such as cell phone (such as various object widely, W-CDMA (UMTS), CDMA2000 (IS-856/IS-2000) etc.), WiFi (such as, IEEE 802.11, version in 1999, LAN/MAN WLAN S), bluetooth (such as, IEEE 802.15.1-2005, wireless personal-area network), WiMax (such as, IEEE802.16-2004, LAN/MAN broadband wireless LANS), GPS (GPS), spread spectrum (such as, 900MHz) with other radio frequencies (RF) phone object) and communication function outside platform is provided.I/O module 64 can also comprise one or more wireless hardware circuitry block to support this function.
SSD 70 can comprise one or more NAND chip, and can be used to provide high capacity data storage and/or very large parallel work-flow amount.Such solution can also be there is, this solution comprises being implemented as and is connected to STD bus (such as serial ATA (SATA, such as SATA version 3 .0 specification, on May 27th, 2009, SATA international organization/SATA-IO) bus or PCI high speed graphic (PEG, such as peripheral parts interconnected/PCI high speed x16 figure 150W-ATX specification 1.0, PCI special interest group) bus) on the NAND controller of special IC (ASIC) controller of separation of I/O module 64.SSD 70 can also be used as USB (USB (universal serial bus), such as USB specification 2.0, USB application person forum) flash memory device.
Shown I/O module 64 comprises BMU 82, and this BMU 82 is configured to detect the interrupt event from multiple not homology (such as network controller 68, audio I/O device 72, SSD 70, the applications active etc. that performs on the processor 62) and coordinates the issue of the interrupt event of processor 62 based on information working time be associated with system 60.In one example, coordinate the issue of interrupt event to comprise and determine the retention time based on information working time and postpone at least one interrupt event based on this retention time.Such as, system 60 can perform VoIP (voice-over ip) application program, and wherein network controller 68 and audio I/O device 72 generate or incoherent IO event seldom relevant to the IO event generated by other equipment separately actively.The interrupt event from network controller 68 and audio I/O device 72 is coordinated by use BMU 82, shown I/O module 64 can make the parts of system 60 enter the darker low power state longer time period, and therefore, it is possible to strengthens the power saving realized by system 60 significantly.
Therefore, technology above can provide the method for entirety to define computing system framework and interface, their is coordinated and aims at the activity of multiple I/O device and application program.As a result, the platform free time can be maximized and save for the platform power optimized.In addition, this coordination and aligning make platform can more closely close to having desirable " work-load proportion " power consumption of sane performance.
Embodiments of the present invention are applicable to use together with all types of SIC (semiconductor integrated circuit) (" IC ") chip.The example of these IC chips includes but not limited to processor, controller, chip set components, programmable logic array (PLA), memory chip, network chip, SOC (system on a chip) (SoC), SSD/NAND controller ASIC etc.In addition, in some drawings, signal conductor line is represented with line.Some can be thicker to show more constituent signals path, and some can have number designation to show the quantity in constituent signals path, and/or some at one end or more can have arrow to show main information flow direction by end.But this should not make an explanation in a restricted way.On the contrary, the details that these can be used to add in conjunction with one or more illustrative embodiments, more easily to understand circuit.Any described signal wire (no matter whether having additional information) can comprise the one or more signals that can propagate in a plurality of directions practically, and can realize with the signaling plan of any suitable type, such as, the numeral using differential pair to realize or artificial line, optical fiber cable and/or single ended line.
Given exemplary sizes/models/values/ranges, but embodiments of the present invention are not limited thereto.When process technology (such as, photolithography) is ripe along with the time, expect the equipment that can produce smaller szie.In addition, for the simplification illustrated and discuss so that the object of the main aspect of not fuzzy embodiment of the present invention, can illustrate or not illustrate that IC chip is connected with the conventional power source/ground of miscellaneous part in the accompanying drawings.In addition, the platform realizing embodiment is wherein depended in order to avoid fuzzy embodiments of the present invention and in view of the details height relevant to the implementation that block diagram is arranged, namely these details should be positioned at the ken of those skilled in the art fully, described layout can be shown in form of a block diagram.Although set forth detail (such as, circuit) to describe illustrative embodiments of the present invention, can when there is no these details or adopt when the distortion of these details to realize embodiments of the present invention but it will be readily apparent to one skilled in the art that.Therefore, this instructions should be considered to illustrative and nonrestrictive.
No matter herein term " coupling " can be used to refer to the relation of any type between discussed parts, be direct or indirectly, and can be applied to electrically, machinery, fluid, optical, electrical magnetic, electromechanical or other connection.In addition, term used herein " first ", " second " etc. are only discussed for being convenient to, and without specific time or in chronological sequence tactic importance, unless otherwise indicated.
Those skilled in the art will recognize from the foregoing description, can realize the broad range of techniques of embodiments of the present invention in a variety of manners.Therefore, although describe embodiments of the present invention in conjunction with particular example of the present invention, but the true scope of embodiments of the present invention should not be limited to this, because by research accompanying drawing, instructions and appending claims, other amendment will be apparent for skilled practitioner.
Background technology
In traditional mobile computing platform, many IO (I/O) equipment (such as, communication interface) and software application may tend to generate inharmonic interrupt event, this can stop platform and parts thereof to enter lower power rating rapidly and rest on the period extended in those states.In fact, shortlyer platform can be caused to remain on more frequently in high power state than the situation of needs with the battery life of suboptimum.
Accompanying drawing explanation
By reading instructions below and appending claims and by reference to the following drawings, the various advantages of embodiments of the present invention will become apparent to those skilled in the art, wherein:
Fig. 1 is the block diagram of the example of multiple coordinated interrupt event according to embodiment;
Fig. 2 is the block diagram of the example of interrupt event administrative unit according to embodiment;
Fig. 3 is the process flow diagram of the example of the method for the issue of coordination interrupt event according to embodiment;
Fig. 4 is the block diagram of interrupt event administrative unit according to embodiment and multiple merge cells; And
Fig. 5 is the block diagram of the example of platform according to embodiment.
Claims (17)
1. issue a method for one or more interrupt event, comprising:
Detect the first interrupt event from the first event source;
Detect the second interrupt event from second event source; And
Described first interrupt event of described platform and the issue of described second interrupt event is coordinated at least in part based on information working time be associated with platform;
Wherein, the issue coordinating described first interrupt event and described second interrupt event comprises: determine the retention time based on information described working time at least in part, and postpone at least one in described first interrupt event and described second interrupt event based on the described retention time at least in part.
2. method according to claim 1, also comprises: obtain information described working time from least one described first event source and described second event source.
3. method according to claim 2, wherein, described working time, information obtains from the equipment being coupled to described platform, at least one in described first interrupt event and described second interrupt event comprises I/O event, and the time delay of I/O event described in described information identification working time.
4. method according to claim 2, wherein, described working time, information obtains from the applications active described platform, at least one in described first interrupt event and described second interrupt event comprises timer event, and the delay ability characteristics of timer event described in described information identification working time.
5. method according to claim 1, also comprises: obtain information described working time from described platform.
6. method according to claim 5, wherein, described information identification working time low power state interrupts averaging time.
7. method according to claim 5, wherein, described information identification working time performance requirement able to programme.
8., for issuing a device for one or more interrupt event, comprising:
Input/output module, it has:
For detecting the module of the first interrupt event from the first event source;
For detecting the module of the second interrupt event from second event source; And
For coordinating the module of described first interrupt event of described platform and the issue of described second interrupt event at least in part based on information working time be associated with platform;
Wherein, the issue coordinating described first interrupt event and described second interrupt event comprises: determine the retention time based on information described working time at least in part, and postpone at least one in described first interrupt event and described second interrupt event based on the described retention time at least in part.
9. device according to claim 8, wherein, described input/output module also comprises: for obtaining the module of information described working time from least one in described first event source and described second event source.
10. device according to claim 9, wherein, described working time, information obtains from the equipment being coupled to described platform, at least one in described first interrupt event and described second interrupt event comprises I/O event, and described working time information for identifying the time delay of described I/O event.
11. devices according to claim 9, wherein, described working time, information obtains from the applications active described platform, at least one in described first interrupt event and described second interrupt event comprises timer event, and described working time information for identifying the delay ability characteristics of described timer event.
12. devices according to claim 8, wherein, described input/output module also comprises the logic for obtaining information described working time from described platform, and at least one for identifying that low power state interrupts in averaging time and performance requirement able to programme of information described working time.
13. 1 kinds, for issuing the system of one or more interrupt event, comprising:
First event source;
Second event source;
Processor; And
Be coupled to the input/output module of described processor, described input/output module has:
For detecting the module of the first interrupt event from described first event source,
For detecting the module of the second interrupt event from described second event source; And
For coordinating the module of described first interrupt event of described system and the issue of described second interrupt event at least in part based on information working time be associated with described system;
Wherein, the issue coordinating described first interrupt event and described second interrupt event comprises: determine the retention time based on information described working time at least in part, and postpone at least one in described first interrupt event and described second interrupt event based on the described retention time at least in part.
14. systems according to claim 13, wherein, described input/output module also comprises: for obtaining the module of information described working time from least one in described first event source and described second event source.
15. systems according to claim 14, wherein, at least one in described first event source and described second event source comprises the equipment being coupled to described system, at least one in described first interrupt event and described second interrupt event comprises I/O event, and described working time information for identifying the time delay of described I/O event.
16. systems according to claim 14, wherein, at least one in described first event source and described second event source comprises the parts for executed activity application program of described system, at least one in described first interrupt event and described second interrupt event comprises timer event, and described working time information for identifying the delay ability characteristics of described timer event.
17. systems according to claim 13, wherein, described input/output module also comprises the module for obtaining information described working time from described system, and at least one for identifying that low power state interrupts in averaging time and performance requirement able to programme of information described working time.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/888,855 | 2010-09-23 | ||
| US12/888,855 US8612998B2 (en) | 2010-09-23 | 2010-09-23 | Coordinating device and application break events for platform power saving |
| PCT/US2011/052045 WO2012040068A1 (en) | 2010-09-23 | 2011-09-16 | Coordinating device and application break events for platform power saving |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102597912A CN102597912A (en) | 2012-07-18 |
| CN102597912B true CN102597912B (en) | 2015-03-25 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201180002743.7A Active CN102597912B (en) | 2010-09-23 | 2011-09-16 | Coordinating device and application break events for platform power saving |
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|---|---|
| US (3) | US8612998B2 (en) |
| JP (1) | JP5628431B2 (en) |
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| TW201217973A (en) | 2012-05-01 |
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| DE112011103194B4 (en) | 2017-02-09 |
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| DE112011103194T5 (en) | 2013-06-27 |
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