CN102593799B - A relay protection circuit - Google Patents

Abstract

The invention discloses a relay protection circuit, which comprises a controller, a first nand gate, a second nand gate, a first delay circuit, a second delay circuit, a signal drive circuit, a triode Q2, a photoelectric isolator, a silicon controlled rectifier, a first relay RLY 1 and a second relay RLY 2, wherein the elements are connected to form the circuit. The relay protection circuit has the advantages that as two delay circuits are arranged in the circuit to be matched with other elements, the electricity-passing-time of contacts of the relays is delayed relative to the closing time of the contacts, so that the phenomena that the contacts of the relays are electrified immediately when the relays are in contact and contact splashing matters are produced are avoided.

Description

A relay protection circuit

technical field

The invention relates to a protection circuit for a relay in a controller of an intelligent lighting control system.

Background technique

In the control of equipment such as motors or lights, many circuits are connected in parallel by several load units, so that the load power is very large, and the power is as high as 2000W-3000W. Because contact spatters are easily generated when switching on and off a large load, they will adhere to the contacts. The greater the current, the easier it is to cause the contacts to stick and cannot be disconnected.

When many lamps are in a cold state, the resistance is very small, almost close to an instantaneous short circuit, and the current is 5 times to 10 times larger than the normal operation when starting, so it is easy to cause damage to the relay contacts in the control circuit in an instant, causing the controller to fail. Shortened lifespan, failure. Especially the motor load is greater at the moment of starting, which is easy to damage the relay.

Contents of the invention

The object of the present invention is to overcome the defects of the prior art and provide a relay protection circuit, which can effectively prevent the relay from being burned and improve the service life of the relay.

In order to achieve the purpose of the above invention, the present invention adopts the following technical solutions: a relay protection circuit, including: a controller, a first NAND gate, a second NAND gate, a first delay circuit, a second delay circuit, a signal drive circuit, Transistor Q2, photoelectric isolator, silicon controlled rectifier, first relay RLY1 and second relay RLY2; The input terminal and output terminal of described first NAND gate are respectively connected with one of the output terminals of the controller and the input of the first delay circuit The input terminal and the output terminal of the signal driving circuit are respectively connected to the output terminal of the first delay circuit and the base of the transistor Q2, the collector of the transistor Q2 is connected to one end of the control circuit of the first relay RLY1, and the emitter of the transistor Q2 Grounded, the other end of the control circuit of the first relay is connected to 12 volts; the input and output of the second delay circuit are respectively connected to the input of the first NAND gate and the input of the second NAND gate, and the second The output terminal of the NAND gate is connected to the input terminal of the photoelectric isolator, and the two output terminals of the photoelectric isolator are respectively connected to the input terminal of the thyristor and the neutral line of the working power supply, and the working circuit terminal of the first relay RLY1 is respectively connected to the The SCR output terminal is connected to the live wire of the working power supply, the control circuit end of the second relay RLY2 is respectively connected to the 12 volt voltage and the other output terminal of the controller, and the working circuit end of the second relay RLY2 is respectively connected to the live wire and neutral wire of the working power supply.

The delay circuit includes a resistor R, a diode D and a capacitor C, one end of the resistor R is connected to the positive pole of the diode D, the other end is connected to the negative pole of the diode D, the positive pole of the capacitor C is connected to the negative pole of the diode D, and the negative pole of the capacitor is grounded , where the anode of the diode D is the input end of the delay circuit, and the cathode is the output end of the delay circuit.

The driving signal circuit includes a third NAND gate and a fourth NAND gate, the input end and the output end of the third NAND gate are connected to the output end of the first delay circuit and the input end of the fourth NAND gate respectively, The output terminals of the four NAND gates are connected to the base of the triode Q2.

The beneficial effects of the present invention are: by setting two time-delay circuits in the circuit and cooperating with other components, the contact over-current time of the relay is delayed relative to the contact closing time, so as to prevent the contact from being energized immediately when the relay contact is in contact, which may cause a trigger Point splatter.

Description of drawings

Fig. 1 is a working principle diagram of the present invention;

Fig. 2 is a circuit diagram of the present invention;

Fig. 3 is the oscillogram of point a, b, c when the present invention works.

Detailed ways

Referring to Fig. 1, the relay protection circuit of the present invention includes a controller, a first NAND gate, a second NAND gate, a first delay circuit, a second delay circuit, a triode Q2, a photoelectric isolator, a controllable Silicon, relay RLY1 and relay RLY2; the delay circuit includes a resistor R, a diode D and a capacitor C, one end of the resistor R is connected to the positive pole of the diode D, the other end is connected to the negative pole of the diode D, and the positive pole of the capacitor C is connected to the diode The negative pole of D and the negative pole of the capacitor are grounded, wherein the positive pole of the diode D is the input terminal of the delay circuit, and the negative pole is the output terminal of the delay circuit; the drive signal circuit includes a third NAND gate and a fourth NAND gate, and the third NAND gate The input end and the output end of the NOT gate are respectively connected with the output end of the first delay circuit and the input end of the fourth NAND gate, and the output end of the fourth NAND gate is connected with the base of the transistor Q2; the first NAND The input end and the output end of the gate are respectively connected with one of the output ends of the controller and the input end of the first delay circuit, and the input end and output end of the signal driving circuit are respectively connected with the output end of the first delay circuit and the base of the transistor Q2 connection, the collector of the triode Q2 is connected to one end of the control circuit of the first relay RLY1, the emitter of the triode Q2 is grounded, and the other end of the control circuit of the first relay is connected to 12 volts; the input end and output end of the second delay circuit They are respectively connected to the input end of the first NAND gate and the input end of the second NAND gate, the output end of the second NAND gate is connected to the input end of the photoelectric isolator, and the two output ends of the photoelectric isolator are respectively connected to the controllable The input terminal of the silicon is connected to the zero line of the working power supply, the working circuit terminal of the first relay RLY1 is respectively connected to the output terminal of the thyristor and the live wire of the working power supply, and the control circuit terminal of the second relay RLY2 is respectively connected to the 12 volt voltage and the controller’s The other output terminal, the working circuit terminal of the second relay RLY2 is respectively connected to the live wire and the neutral wire of the working power supply.

The specific work flow of relay protection circuit of the present invention is as follows:

As shown in Figure 2, the process of turning on the load: the controller first inputs a low-level signal from the signal input terminal DO1. Since the positive terminal of capacitor C1 was originally at a high level, after R2 discharges, the discharge time is 220ms, and point C needs 220ms to complete. To reach a high level, the silicon controlled rectifier can be turned on. Capacitor C2 is originally low level, when D01 terminal input low level, it becomes high level through X1A NAND gate, and directly charges C2 through diode D2, there is no resistance current limiting, it is quickly charged, and becomes high level , through the NAND gate X1C, X1D to enhance the signal driving ability, output high level at point b, drive the transistor Q2, energize the control circuit of the relay RLY1, and the contact of the relay RLY1 is closed. , RLY1 contact closure does not produce arc. While inputting low level at the D01 terminal, C1 is directly discharged through R2. After the discharge time is 220ms, it outputs a high level through the X1B NAND gate to drive the photoelectric isolator U1, and the isolated output signal triggers the thyristor, and the relay RLY1 is energized. The load starts working. The controller delays 300ms after outputting a low-level signal at the D01 terminal, and outputs a low-level signal to the relay RLY2 through the RY1 terminal, and the relay RLY2 is connected. Transistor Q1 will generate heat. In order not to increase the heat sink, the controller needs to disconnect the DO1 signal after the load starts to work. Point a becomes high level, and directly charges C1 through the D1 diode to become high level. After a X1B NAND gate, point C becomes low level, outputs low level signal through optocoupler isolation, SCR is disconnected, at the same time point a becomes low level through X1A NAND gate, C2 discharges through R1, It takes 220ms to discharge the electricity, and then through two NAND gates to enhance the driving ability, point b becomes low level, transistor Q2 is cut off, RLY1 is disconnected, and the action of turning on the load is completed. This process not only protects RLY2, but also solves the heat dissipation problem of the thyristor through RLY1.

Load shutdown process: the controller first inputs a low level signal from the DO1 terminal. Since the positive terminal of C1 is originally a high level, it is discharged after R2, and the discharge time is 220ms, so it takes 220ms for point C to reach a high level and turn on SCR. While C2 was originally low level, when D01 terminal input low level, it will charge C2 directly through D2, without delay, it will be fully charged soon, and become high level, and then through two NAND gates X1C, X1D to enhance the driving ability, Output high level at point b, drive Q2 triode to conduct relay RLY1. The controller delays 300ms to input a high-level signal from RY1, the relay RLY2 is disconnected, and the load stops working. In order to cut off the protection circuit, the DO1 signal needs to be disconnected at this time, point a becomes high level, C1 charges and becomes high level, passes through an X1B NAND gate, point C becomes low level, and the thyristor is disconnected. Point a becomes low level through the NAND gate of X1A, C2 discharges through R1, and it takes 220ms to discharge the electricity, point b becomes low level, RLY1 is disconnected, and the load-closing action of the switch is completed at this point. This process protects the RLY2 during the disconnection process, prevents the arc from burning the contacts, and also solves the problem of heat dissipation of the thyristor. The output timing waveform diagram is shown in Figure 3.

Claims (3)

1. a relay protection circuit, is characterized in that comprising: controller, the first NAND gate, the second NAND gate, the first delay circuit, the second delay circuit, signal drive circuit, triode Q2, photoisolator, controllable silicon, the first relay R LY1 and the second relay R LY2, the input of described the first NAND gate and output are connected with the input of the first delay circuit with one of output of controller respectively, the input of signal drive circuit is connected with the base stage of triode Q2 with the output of the first delay circuit respectively with output, the collector electrode of triode Q2 is connected with control circuit one end of the first relay R LY1, the grounded emitter of triode Q2,12 volts of voltages of another termination of the control circuit of the first relay R LY1, the input of described the second delay circuit is connected with the input of the second NAND gate with the input of the first NAND gate respectively with output, the output of the second NAND gate is connected with the input of photoisolator, two outputs of photoisolator are connected with the zero line of silicon controlled input and working power respectively, the operating circuit end of the first relay R LY1 is connected with working power live wire with controllable silicon output respectively, the control circuit end of the second relay R LY2 connects respectively another output of 12 volts of voltages and controller, the operating circuit end of the second relay R LY2 connects respectively live wire and the zero line of working power.

2. relay protection circuit according to claim 1; it is characterized in that: described delay circuit comprises resistance R, diode D and capacitor C; one end of described resistance R is connected with the positive pole of diode D; the other end is connected with the negative pole of diode D; the positive pole of capacitor C connects the negative pole of diode D; the minus earth of electric capacity, the input of the just very delay circuit of diode D wherein, the output that negative pole is delay circuit.

3. relay protection circuit according to claim 1; it is characterized in that: described drive signal circuit comprises the 3rd NAND gate and the 4th NAND gate; the input of the 3rd NAND gate is connected with the input of the 4th NAND gate with the output of the first delay circuit respectively with output, and the output of the 4th NAND gate is connected with the base stage of triode Q2.

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