CN102593173A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The invention discloses a novel MOSFET device and its realization method, comprising a silicon-containing substrate, a channel region located in the substrate, source and drain regions located on both sides of the channel region, and a gate structure located on the channel region As well as the isolation spacers located on both sides of the gate structure, the source and drain regions have nickel-based metal silicide, which is characterized in that: the nickel-based metal silicide has doping ions that inhibit the diffusion of nickel metal; the nickel-based metal silicide/ditch The interface of the channel region also has a gathering area of doped ions, and the gathering area is located under the isolation sidewall and does not enter the channel area. The dopant ions distributed in the nickel-based metal silicide and gathered at the nickel-based metal silicide/channel interface can prevent the lateral growth of the nickel-based metal silicide, thus preventing source-drain punch-through or gate leakage current, thereby improving Device reliability further improves product yield.

Description

Semiconductor device and manufacturing method thereof

technical field

The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a novel CMOS structure suitable for controlling the lateral growth of nickel-based metal silicides and a manufacturing method thereof.

Background technique

The continuous increase of IC integration requires the continuous reduction of device size, but the electrical operating voltage sometimes remains unchanged, which makes the electric field strength in the actual MOS device continue to increase. The high electric field brings a series of reliability problems, which degrades the performance of the device.

The parasitic series resistance between the source and drain regions of the MOSFET will reduce the equivalent operating voltage. In order to reduce contact resistivity and source-drain series resistance, deep submicron small-sized MOSFETs often use highly doped source and drain and cover metal silicide, especially nickel-based metal silicide, on the source and drain regions as contacts. As shown in FIG. 1 , it is a traditional highly doped source-drain MOSFET. The substrate 10 is divided into a plurality of active regions including a channel region 14 by a shallow trench isolation (STI) 20, a gate structure 50 and its top. The cover layer 60 is formed on the substrate 10, and isolation spacers 70 are formed on both sides of the gate structure 40, and the source and drain regions 30 are formed in the substrate 10 on both sides of the side walls 70. The source and drain regions can be highly doped as a whole, It can also be a partially lightly doped structure (LDD), and a metal silicide 40 is formed on the source and drain regions 30, and the metal silicide 40 is usually a nickel-based metal silicide. Wherein, the substrate 10 may be bulk silicon, or silicon-on-insulator (SOI) including a silicon substrate 11 , a buried oxide layer 12 and a thin silicon layer 13 , or a compound semiconductor material such as SiGe.

It should be noted that, in FIG. 1 and subsequent drawings, for convenience of illustration, the STI 20 between the bulk silicon substrate 10 and the SOI substrate (11, 12, and 13) is only a schematic isolation, not an actual separation between the two. Adjacent or touching.

However, this traditional highly doped source-drain MOSFET with Ni-based metal silicide also has some disadvantages. As shown in Figure 2, in its manufacturing process, it is necessary to deposit a thin layer of metal, usually nickel-based metal, on the basic structure including the substrate, the gate on the substrate, and the gate isolation spacer, and then anneal at high temperature to make The metal reacts with the silicon in the substrate to form a metal silicide. During this high-temperature annealing, the thin layer of metal not only directly reacts with the silicon in the substrate, but also diffuses laterally into the substrate bypassing the gate isolation spacers, which are usually nitrides, thus forming the dotted ellipse in Figure 3. Nickel-based metal silicide lateral growth. This lateral growth not only occurs under the gate isolation spacer, but also may occur in the channel region in the substrate under the gate. Accompanying drawings 4A and 4B are transmission electron microscope cross-sectional views of a device in which nickel-based metal silicide has grown laterally. The dotted line shown in FIG. The arrow in FIG. 4B indicates the Ni-based metal silicide that has undergone lateral growth.

When the device size is reduced to sub-50nm, the lateral growth (or lateral invasion) of this nickel-based metal silicide will greatly increase the gate leakage current and reduce the reliability of the device. When the substrate is SOI, due to the buried oxide layer The thin silicon layer itself is less, so that the source and drain may be connected due to the lateral growth of the nickel-based metal silicide, resulting in an electrical short circuit, which will cause major problems, resulting in a decrease in product yield and an increase in cost.

In order to solve this problem, people usually use two-step annealing to form nickel-based metal silicide.

First, as shown in Figure 5, a thin layer of metal is deposited on the base structure. On the substrate 10 with STI 20 (it can also be an SOI substrate including thick silicon 11, buried oxide layer 12 and thin silicon layer 13), gate 50, capping layer 60, gate spacer 70 are sequentially formed, ion implantation And annealing and activating to form highly doped source and drain 30 . A thin metal layer 80 of Ni or Ni-Pt is deposited over the entire basic structure. Then a first low temperature annealing is performed, the annealing temperature is about 300°C.

After the first low-temperature annealing, as shown in FIG. 6 , the part of the nickel-based metal thin layer 80 directly in contact with the substrate 10, that is, located in the source and drain regions, will react with the silicon in the substrate to form a nickel-rich phase of the nickel-based metal. silicide. At this low annealing temperature of about 300° C., the thin metal layer on the gate spacer 70 is less likely to diffuse laterally into the substrate around the spacer spacer.

Next, as shown in FIG. 7, the unreacted thin metal layer 80 is peeled off. The second high-temperature annealing is performed at a temperature of about 450 to 500° C., so that the nickel-based metal silicide in the nickel-rich phase is transformed into a nickel-based metal silicide 40 with low resistivity, so as to reduce the source-drain parasitic resistance and improve the response speed of the device . It can be seen from Figure 7 that the lateral growth of nickel-based metal silicides is suppressed to a certain extent due to the two-step annealing at different temperatures, but the process complexity is increased, and a certain amount of nickel-based metal silicide still occurs during the second high-temperature annealing. The metal silicide grows laterally.

All in all, in the self-aligned silicide process, the excess Ni diffusion on the isolation nitride sidewall is very fast, and the lateral growth of the Ni-based metal silicide is easy to occur, resulting in increased gate leakage current, reduced device stability, and possible source-drain leakage. Punchthrough occurs, especially for SOI devices. Therefore, there is a need for a manufacturing method that can effectively reduce the lateral growth of nickel-based metal silicides in the process of manufacturing novel semiconductor devices.

Contents of the invention

From the above, the object of the present invention is to provide a method for effectively reducing the lateral growth of nickel-based metal silicide.

The present invention provides a semiconductor device, comprising a silicon-containing substrate, a channel region located in the substrate, source and drain regions located on both sides of the channel region, and a gate located on the channel region structure and the isolation spacers located on both sides of the gate structure, the source and drain regions have a nickel-based metal silicide, which is characterized in that: the nickel-based metal silicide has doping that can inhibit the diffusion of nickel metal ion.

Wherein, the interface between the nickel-based metal silicide and the channel region also has a gathering region of the dopant ions, and the gathering region is located under the isolation sidewall and does not enter the channel region. The ion accumulation region can also inhibit the diffusion of nickel metal.

Wherein, the dopant ions can inhibit the diffusion of nickel metal, and are any one of carbon, nitrogen, oxygen, fluorine, sulfur and their combination, and the dose of dopant ions is 1×10 ¹³ cm ⁻² to 8×10 ¹⁵ cm ^-2 .

Wherein, a nickel-based metal silicide is formed on the source and drain regions. Wherein, the substrate is bulk silicon or silicon-on-insulator (SOI).

Wherein, the source and drain regions are highly doped source and drain regions with an LDD structure.

Wherein, the nickel-based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.

The present invention also provides a method for manufacturing a semiconductor device, comprising:

forming a gate structure on a silicon-containing substrate;

The source and drain LDD regions are formed after the first source and drain implant annealing, and the substrate between the source and drain LDD regions becomes the channel region;

forming isolation spacers on both sides of the gate structure;

The source and drain highly doped regions are formed after the second implant annealing of the source and drain;

obliquely implanting dopant ions capable of suppressing the diffusion of nickel metal into the substrate below the isolation spacer;

depositing a nickel-based metal layer on the substrate, the gate structure, and the isolation spacers;

Rapid thermal annealing, so that the nickel-based metal layer on both sides of the isolation spacer reacts with the silicon in the substrate to form a nickel-based metal silicide, and at the same time, the dopant ions are distributed in the nickel-based metal silicide middle;

Stripping off the unreacted nickel-based metal layer.

Wherein, during rapid thermal annealing, an accumulation region of doped ions is also formed at the interface of the nickel-based metal silicide/channel region, and the accumulation region is located under the isolation sidewall and does not enter the channel region .

Wherein, the dopant ion is any one of carbon, nitrogen, oxygen, fluorine, sulfur and a combination thereof, and the dose of the dopant ion is 1×10 ¹³ cm ⁻² to 8×10 ¹⁵ cm ⁻² .

Wherein, the silicon-containing substrate is bulk silicon or silicon-on-insulator (SOI).

Wherein, the oblique implantation of dopant ions is performed at room temperature or at low temperature, specifically, the oblique implantation of dopant ions is performed at 0°C to -250°C.

Wherein, the oblique implantation of the dopant ions forms a pocket-like or halo-like dopant-ion distribution region in the substrate below the isolation sidewall, and the dopant-ion distribution region does not enter the channel region. Wherein, the silicon in the dopant ion distribution region is completely consumed in the rapid thermal annealing stage.

Wherein, the source and drain regions are highly doped source and drain regions with an LDD structure.

Wherein, the nickel-based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.

In the novel MOSFET manufactured according to the present invention, the accumulation region of dopant ions distributed under the isolation sidewall but not entering the channel region under gate control can prevent the lateral growth of nickel-based metal silicide, thus preventing source-drain through or gate Pole leakage current, thereby improving device reliability and further improving product yield.

The stated objects of the invention, as well as other objects not listed here, are met within the scope of the independent claims of the present application. Embodiments of the invention are defined in the independent claim and specific features are defined in its dependent claims.

Description of drawings

Describe technical scheme of the present invention in detail below with reference to accompanying drawing, wherein:

FIG. 1 shows a schematic cross-sectional view of a highly doped source-drain MOSFET in the prior art;

Fig. 2 and Fig. 3 have shown the schematic cross-sectional view of the lateral growth of nickel-based metal silicide in the prior art;

Figure 4A and Figure 4B show the transmission electron micrographs of the lateral growth of nickel-based metal silicide in the prior art;

Figures 5 to 7 show the cross-sectional schematic diagrams of the prior art two-step annealing method for inhibiting the lateral growth of nickel-based metal silicide; and

8 to 12 show a method for controlling the lateral growth of nickel-based metal silicide during the preparation of traditional heavily doped source-drain MOSFET according to the present invention.

Detailed ways

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments, and a novel semiconductor device structure and its manufacturing method that can effectively reduce the lateral growth of nickel-based metal silicides are disclosed. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures. These modifications do not imply a spatial, sequential or hierarchical relationship of the modified device structures unless specifically stated.

8 to 12 illustrate the method for controlling the lateral growth of nickel-based metal silicide in the source and drain regions in the preparation of traditional heavily doped source and drain MOSFETs according to the present invention.

First, form the base structure. Figure 8 is a schematic cross-sectional view of the basic structure. A gate dielectric layer 310 is deposited on a substrate 100 having a shallow trench isolation (STI) 200, wherein the substrate 100 may be bulk silicon, silicon-on-insulator (SOI) or other compound semiconductor substrates containing silicon, such as SiGe , SiC, etc., and combinations of these substances; the gate dielectric layer 310 can be low-k silicon oxide, silicon oxynitride, or high-k material, such as hafnium oxide. Deposit gate layer 300 on gate dielectric layer 310, the material of gate layer 300 can be polysilicon (poly Si), amorphous silicon (α-Si), also can be metal or alloy and its nitride, such as Al, Ti, Ta, TiN, TaN, etc., even when the gate layer 300 is used as a dummy gate of the gate-last process, is an oxide, especially silicon dioxide, or a stack or a mixture of these substances. A capping layer 400 is deposited on the gate layer 300 , and its material is usually nitride, such as silicon nitride (SiN), for a hard mask layer to be etched later. A gate stack structure formed by overlapping the gate dielectric layer 310 , the gate layer 300 and the capping layer 400 is formed by using a common photolithography mask etching process. Using the gate stack structure as a mask, perform the first low-dose implantation of the source and drain, and anneal to form the source and drain LDD regions. Subsequently, an isolation insulating layer is deposited on the entire structure and etched, leaving isolation spacers 500 on both sides of the gate stack structure, and the material of the isolation spacers 500 can be nitride or oxynitride. Using the gate stack structure and the isolation spacer 500 as a mask, perform the second high-dose implantation of the source and drain, and anneal to form a highly doped source and drain region, thereby forming a highly doped source and drain with an LDD structure as shown in FIG. 8 region 600 in order to further reduce the source-drain resistance. Naturally, the source-drain ion implantation can also be performed only once to form the highly doped source-drain region 600 with an LDD structure.

Next, oblique ion implantation is performed. As shown in FIG. 9 , with a large inclination angle (the line between the source and drain regions 600 and the channel region forms an obtuse angle, the angle of the obtuse angle depends on the position of the dopant ion distribution region to be formed, and the closer the distribution region is to the channel region , the larger the angle) perform pocket or halo-shaped ion implantation, that is, the implanted dopant ions are obliquely implanted into the substrate below the isolation spacer 500 at a large inclination angle, which is similar to obliquely inserting a pocket from the side from a cross-sectional view or form a halo shape. Doping ions are ions that can hinder the diffusion of Ni, such as any one of carbon C, nitrogen N, oxygen O, fluorine F or sulfur S and their combination, and any other ions that can inhibit the diffusion of Ni. The dose of oblique ion implantation can be 1×10 ¹³ cm ^-2 to 8×10 ¹⁵ cm ^-2 , and the implantation temperature can be room temperature or low temperature. Specifically, low temperature implantation is performed at 0°C to -250°C, so it is also called Cold infusion. The result obtained by oblique ion implantation is shown in FIG. 10 . A distribution region 700 of dopant ions is formed at a place under the isolation spacer 500 that does not protrude beyond the channel region, which is represented by a shaded ellipse. Specifically, the distribution region 700 of dopant ions is 700 is located below the gate isolation spacer 500 and will not enter the channel region, that is, located on both sides of the gate layer 300 , preferably close to or outside the isolation spacer 500 . The dopant ion distribution region 700 is similar to pockets or halos under the isolation spacers on both sides from a cross-sectional view, so oblique ion implantation is also called pocket or halo ion implantation.

Subsequently, as shown in FIG. 11 , a thin nickel-based metal layer 800 is deposited on the entire structure, ie, the substrate 100, the STI 200, the gate stack structure, and the source-drain region 600. The material of the metal thin layer 800 can be nickel (Ni), nickel-platinum alloy (Ni-Pt, wherein the Pt content is less than or equal to 8%), nickel-cobalt alloy (Ni-Co, wherein the Co content is less than or equal to 10%) or nickel-platinum-cobalt Ternary alloy.

Next, a salicide process (SALICIDE) is performed by rapid thermal annealing. As shown in Figure 12, rapid thermal annealing (RTP) is performed at about 450-550°C, the annealing time is generally 1 microsecond to 100 seconds, and the energy density of the laser, ion beam, electron beam or incoherent broadband light source used is about 1 to 100J/cm ² ), the deposited nickel-based metal thin layer 800 reacts with the silicon in the source and drain regions 600 to form a corresponding nickel-based metal silicide, and the part of the unreacted nickel-based metal thin layer 800 is peeled off , leaving the Ni-based metal silicide 900 in the source-drain region 600 of the substrate 100 . During the rapid thermal annealing process, the silicon region containing the dopant ions is completely consumed, that is, a part of the ions that can inhibit the diffusion of nickel in the dopant ion distribution region 700 is distributed in the formed nickel-based metal silicide 900, The other part gathers at the interface of nickel-based metal silicide 900/silicon channel, thereby forming a gathering region 910 of dopant ions, which is located in the substrate below the isolation spacer 500, but does not enter The channel region, that is, on both sides of the gate structure, is preferably close to or located outside the isolation spacer 500 . Both the dopant ions distributed in the nickel-based metal silicide 900 and the dopant ion accumulation region 910 can inhibit the lateral growth of the nickel-based metal silicide, so the lateral growth of the nickel-based metal silicide can be controlled. The nickel-based metal silicide 900 can be NiSi, NiPtSi, NiCoSi, NiPtCoSi according to different materials of the thin metal layer 800 .

The structure of the novel MOSFET device formed according to the above-mentioned manufacturing method of the present invention is shown in FIG. 12 . There is a shallow trench isolation (STI) 200 in the substrate 100; a highly doped source and drain region 600 is formed in the active region between the STI 200 in the substrate 100, and nickel-based metal silicide is grown on the doped source and drain region 600 object 900; the gate stack structure formed on the substrate 100 is located between the source and drain regions 500, the gate stack structure includes a gate dielectric layer 310, a gate layer 300 and a capping layer 400, and both sides of the gate stack structure have isolation sides wall 500; the channel region is located in the substrate 100, between the source and drain regions 600 on both sides of the gate stack structure; the interface between the nickel-based metal silicide 900 and the silicon of the highly doped source and drain regions The gathering region 910 of hetero ions, the gathering region 910 of doped ions is located in the highly doped source-drain region 600 below the isolation spacer 500, and does not enter the channel region under the control of the gate stack structure, that is, the dopant ion The gathering area 910 is close to or located on the outer side of the isolation side wall 500 .

After that, similar to the traditional MOSFET process, an interlayer dielectric layer can be deposited and planarized, contact via holes can be formed by etching, and contact pad layers and metal contact materials can be deposited. When the gate layer 300 is a dummy gate used in the gate-last process, after forming the interlayer dielectric layer and before forming contact vias, the dummy gate can also be etched and removed, and then the high-k gate dielectric material and the metal gate are sequentially deposited. Pole material and planarized.

According to the novel MOSFET manufactured by the present invention, the dopant ion accumulation region distributed in the nickel-based metal silicide and gathered at the interface of the nickel-based metal silicide/silicon channel can prevent the lateral growth of the nickel-based metal silicide, thus preventing Source-drain punch-through or gate leakage current, thereby improving device reliability and further improving product yield.

While the invention has been described with reference to one or more exemplary embodiments, those skilled in the art will recognize various suitable changes and equivalents in device structures that do not depart from the scope of the invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (18)

1. semiconductor device, comprise siliceous substrate, be arranged in said substrate channel region,

Be positioned at the source-drain area of said channel region both sides, the isolation side walls that is positioned at the grid structure on the said channel region and is positioned at said grid structure both sides, said source-drain area has the nickel based metal silicide, it is characterized in that:

Has the dopant ion that can suppress the nickel metal diffusing in the said nickel based metal silicide.

2. semiconductor device as claimed in claim 1; Wherein, The accumulation regions that also has said dopant ion at the interface of said nickel based metal silicide and said channel region, the accumulation regions of said dopant ion are positioned at said isolation side walls below and do not get into said channel region.

3. semiconductor device as claimed in claim 1, wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.

4. semiconductor device as claimed in claim 1, wherein, said dopant ion is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.

5. semiconductor device as claimed in claim 1, wherein, the dosage of said dopant ion is 1 * 10 ¹³Cm ^-2To 8 * 10 ¹⁵Cm ^-2

6. semiconductor device as claimed in claim 1, wherein, said siliceous substrate is body silicon or silicon-on-insulator (SOI).

7. semiconductor device as claimed in claim 1, wherein, said source-drain area is the highly doped source-drain area with LDD structure.

8. the manufacturing approach of a semiconductor device comprises:

On siliceous substrate, form grid structure;

Carry out the source leakage and inject leakage LDD district, after annealing formation source for the first time, the substrate that leak between the LDD district in the source becomes channel region;

Form isolation side walls in said grid structure both sides;

Carry out the source leakage and inject after annealing formation source leakage high-doped zone for the second time;

The dopant ion that can suppress the nickel metal diffusing tilts to be injected in the substrate of isolation side walls below;

Nickel deposited Base Metal layer on said substrate, said grid structure and said isolation side walls;

Rapid thermal annealing, so that the nickel based metal layer of said isolation side walls both sides and the pasc reaction in the said substrate form the nickel based metal silicide, simultaneously, said dopant ion is distributed in the said nickel based metal silicide;

Divest unreacted said nickel based metal layer.

9. the manufacturing approach of semiconductor device as claimed in claim 8; Wherein, During rapid thermal annealing, in the accumulation regions that also forms dopant ion at the interface of said nickel based metal silicide/channel region, the accumulation regions of said dopant ion is positioned at said isolation side walls below and does not get into said channel region.

10. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said dopant ion is any and combination thereof of carbon, nitrogen, oxygen, fluorine, sulphur.

11. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, the dosage of said dopant ion is 1 * 10 ¹³Cm ^-2To 8 * 10 ¹⁵Cm ^-2

12. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said siliceous substrate is body silicon or silicon-on-insulator (SOI).

13. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said dopant ion tilts to be injected to the room temperature injection or low temperature injects.

14. the manufacturing approach of semiconductor device as claimed in claim 13, wherein, it is under 0 ℃ to-250 ℃, to carry out that said low temperature injects.

15. the manufacturing approach of semiconductor device as claimed in claim 8; Wherein, The inclination of said dopant ion is infused in the dopant ion distributed area that forms pocket-like or halation shape in the substrate below the said isolation side walls, and said dopant ion distributed area does not get into said channel region.

16. the manufacturing approach of semiconductor device as claimed in claim 15, wherein, the silicon in the said dopant ion distributed area the rapid thermal annealing stage by full consumption.

17. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said source-drain area is that leak in the highly doped source with LDD structure.

18. the manufacturing approach of semiconductor device as claimed in claim 8, wherein, said nickel based metal silicide is NiSi, NiPtSi, NiCoSi or NiPtCoSi.

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