CN102593088A - Semiconductor chip, semiconductor structure using same, and manufacturing method thereof - Google Patents
Semiconductor chip, semiconductor structure using same, and manufacturing method thereof Download PDFInfo
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- CN102593088A CN102593088A CN2012100699958A CN201210069995A CN102593088A CN 102593088 A CN102593088 A CN 102593088A CN 2012100699958 A CN2012100699958 A CN 2012100699958A CN 201210069995 A CN201210069995 A CN 201210069995A CN 102593088 A CN102593088 A CN 102593088A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims description 24
- 230000008878 coupling Effects 0.000 claims description 15
- 238000010168 coupling process Methods 0.000 claims description 15
- 238000005859 coupling reaction Methods 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000000034 method Methods 0.000 description 8
- 229910000952 Be alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000004308 accommodation Effects 0.000 description 1
- 230000009172 bursting Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Wire Bonding (AREA)
Abstract
一种半导体芯片、应用其的半导体结构及其制造方法。半导体芯片包括基材及阶梯状导电柱。阶梯状导电柱形成于基材且包括第一导电柱及第二导电柱。第二导电柱形成于第一导电柱上，第二导电柱的剖面积小于第一导电柱的剖面积。第一导电柱及第二导电柱中至少一者各包括第一部分及第二部分，第二部分连接于第一部分且与第一部分之间形成一凹部。
A semiconductor chip, a semiconductor structure using the same, and a manufacturing method thereof. The semiconductor chip includes a substrate and a stepped conductive column. The stepped conductive column is formed on the substrate and includes a first conductive column and a second conductive column. The second conductive column is formed on the first conductive column, and the cross-sectional area of the second conductive column is smaller than the cross-sectional area of the first conductive column. At least one of the first conductive column and the second conductive column each includes a first portion and a second portion, and the second portion is connected to the first portion and forms a recess between the second portion and the first portion.
Description
Technical field
The invention relates to a kind of semiconductor chip, use its semiconductor structure and manufacturing approach thereof, and particularly have the semiconductor chip of stepped conductive pole, the semiconductor structure of using it and a manufacturing approach thereof relevant for a kind of.
Background technology
Semiconductor chip generally includes straight conductive pole, and semiconductor chip is located on the substrate with straight conductive pole.
Yet, semiconductor chip to be located in the process of substrate, the stress that straight conductive pole is born is big, the destruction that often causes straight conductive pole, even straight conductive pole does not obviously destroy in setting up procedure, the stress that it bore also can cause the decline of durability.
Summary of the invention
The present invention is relevant for a kind of semiconductor chip, the semiconductor structure of using it and manufacturing approach thereof, and meeting with stresses of its stepped conductive pole is little.
According to one embodiment of the invention, a kind of semiconductor chip is proposed.Semiconductor chip comprises a base material and a stepped conductive pole.Stepped conductive stud is formed in base material and comprises one first conductive pole and one second conductive pole.Second conductive stud is formed on first conductive pole, and a sectional area of second conductive pole is less than a sectional area of first conductive pole.Wherein, at least one respectively comprises a first and a second portion in first conductive pole and second conductive pole, second portion be connected in first and and first between form a recess.
According to another embodiment of the present invention, a kind of semiconductor structure is proposed.Semiconductor structure comprises a substrate, semiconductor chip and a primer.Semiconductor chip comprises a base material and a stepped conductive pole.Stepped conductive stud is formed in base material and comprises one first conductive pole and one second conductive pole.Second conductive stud is formed on first conductive pole, and a sectional area of second conductive pole is less than a sectional area of first conductive pole.Wherein, at least one respectively comprises a first and a second portion in first conductive pole and second conductive pole, second portion be connected in first and and first between form a recess.Primer is formed between substrate and the semiconductor chip.
A kind of manufacturing approach of semiconductor chip is proposed according to another embodiment of the present invention.Manufacturing approach may further comprise the steps.One base material is provided; And; Form a stepped conductive pole on base material; Wherein stepped conductive pole comprises one first conductive pole and one second conductive pole, and second conductive stud is formed on first conductive pole, and the sectional area of second conductive pole is less than the sectional area of first conductive pole; At least one respectively comprises a first and a second portion in first conductive pole and second conductive pole, second portion be connected in first and and first between form a recess.
For there is better understanding above-mentioned and other aspects of the present invention, hereinafter is special lifts embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Figure 1A illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.
Figure 1B illustrates among Figure 1A the cutaway view along direction 1B-1B '.
Fig. 2 illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.
Fig. 3 illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.
Fig. 4 illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.
Fig. 5 illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.
Fig. 6 illustrates the experimental result picture that meets with stresses of multiple stepped conductive pole.
The main element symbol description:
10: semiconductor structure
12: substrate
14: primer
100: semiconductor chip
13: connection pad
110: base material
120,220,320,420,520,720: stepped conductive pole
121,321,421,721,821: the first conductive poles
122,222,422,722,822: the second conductive poles
1221,3211: first
1222,3212: second portion
1213,3213: the coupling part
130: scolder
620: straight conductive pole
D1: external diameter
H1, H2: highly
R: recess
W: spacing
Embodiment
Please with reference to Figure 1A, it illustrates the cutaway view according to the semiconductor structure of one embodiment of the invention.Semiconductor structure 10 comprises substrate 12, semiconductor chip 100 and primer (underfill) 14, and wherein primer 14 is formed between substrate 12 and the semiconductor chip 100.
Stepped conductive pole 120 is formed at base material 110 and comprises first conductive pole 121 and second conductive pole 122.Second conductive pole 122 is formed on first conductive pole 121; And the sectional area of second conductive pole 122 (like cross sectional area) is less than the sectional area of first conductive pole 121; Make stepped conductive pole 120 provide one more high surface area (equaling the sectional area of first conductive pole 121 compared to the sectional area of second conductive pole 122) contact with primer 14, and then make primer 14 more closely coat stepped conductive pole 120.In the present embodiment; Whole second conductive pole 122 is overlapped in first conductive pole 121; The right embodiment of the invention is not as limit, and second conductive pole 122 and first conductive pole 121 also can partly overlap, i.e. second conductive pole 122 and first conductive pole 121 distance that laterally staggers.
For the semiconductor chip of thin space,,, so possibly cause intactly coated with conductive post of primer so increased the resistance that primer flows between base material and substrate because the spacing of adjacent two conductive poles is quite little.Review present embodiment; Because the sectional area of second conductive pole 122 is less than the sectional area of first conductive pole 121; The accommodation space of primer 14 is increased, so can reduce the resistance that primer 14 flows between base material 110 and substrate 12, under this design; Even stepped conductive pole 120 is applied to the semiconductor chip of thin space, still can make primer 14 intactly coat whole stepped conductive pole 120.
The volume of first conductive pole 121 can less than, be equal to or greater than the volume of second conductive pole 122, for example, the volume of first conductive pole 121 can be between between 0.1 to 5 times of the volume of second conductive pole 122, so this multiple scope is not in order to the restriction embodiment of the invention.In addition, the material of stepped conductive pole 120 for example is a copper, and the material of right stepped conductive pole 120 also can be alloy or other metal not as limit.
Shown in Figure 1A, the height H 1 of first conductive pole 121 is between about 2 to 50 microns, and preferably between about 2 to 20 microns, and the height H 2 of second conductive pole 122 is greater than 15 microns.Among one embodiment, the height H 2 of second conductive pole 122 is between between 3 to 6 times of the height H 1 of first conductive pole 121, and is preferable but non-exclusively 4 times.Under above-mentioned size relationship, can keep the intensity of second conductive pole 122, semiconductor chip 100 is located in the process on the substrate 12, second conductive pole 122 is difficult for bursting apart (cracking) or can burst apart too seriously.In addition; When the ratio of the height H 1 of the height H 2 of second conductive pole 122 and first conductive pole 121 is too high (slenderness ratio is too big); Cause the electrical quality of stepped conductive pole 120 to descend easily; In the present embodiment, because the height H 2 of second conductive pole 122 is between between 3 to 6 times of the height H 1 of first conductive pole 121, so can keep the electrical quality of stepped conductive pole 120.
Shown in Figure 1A, stepped conductive pole 120 more comprises scolder (solder) 130, and it is formed on the end face of second conductive pole 122, can help stepped conductive pole 120 firmly to be formed on the substrate 12.Among one embodiment, the D outer diameter 1 of scolder 130 greater than or equal 10 microns in fact.When the D outer diameter 1 of scolder 130 is equal to or less than 10 microns, can make semiconductor chip 100 become the semiconductor chip of thin space.The position of stepped conductive pole 120 is corresponding to the connection pad 13 of substrate 12, can make the circuit of semiconductor chip 100 be electrically connected at the connection pad 13 of substrate 12 through stepped conductive pole 120.
Please with reference to Figure 1B, it illustrates among Figure 1A the cutaway view along direction 1B-1B '.In the present embodiment, the section shape of first conductive pole 121 circle, ellipse or polygon, present embodiment are the example explanation with the circle, and the section shape dumb-bell shape of second conductive pole 122 (Daisy Chain).In detail; Second conductive pole 122 comprises first 1221, second portion 1222 and coupling part 1223; Wherein circular, ellipse of the section shape of first 1221, second portion 1222 and/or coupling part 1223 or polygon; The first 1221 of present embodiment and the section shape of second portion 1222 are all with ellipse, and the section shape of coupling part 1223 is the example explanation with the rectangle.
Shown in Figure 1B, form at least one recess R between first 1221 and the first 1212.Because the formation of recess R makes second conductive pole 122 provide extra surface area (sidewall area of recess R) to contact with primer 14, and then makes primer 14 more closely coat second conductive pole 122.Coupling part 1223 connects first 1221 and second portion 1222; And the sectional area of coupling part 1223 can provide the surface area of more (compared to omitting coupling part 1223) to contact with primer 14 less than the sectional area of first 1221 and second portion 1222.
Please with reference to Fig. 2, it illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.In the present embodiment, stepped conductive pole 220 comprises first conductive pole 121 and second conductive pole 222, and wherein first conductive pole 121 is connected in second conductive pole 222.Section shape circle, ellipse or the polygon of first conductive pole 121; Present embodiment is the example explanation with the circle; And second conductive pole 222 comprises first 1221 and second portion 1222; Wherein second portion 1222 directly connects first 1221, and forms recess R between second portion 1222 and the first 1221.
Please with reference to Fig. 3, it illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.In the present embodiment; Stepped conductive pole 320 comprises first conductive pole 321 and second conductive pole 122; First conductive pole 321 is connected in second conductive pole 122; Wherein the section shape of first conductive pole 321 for example is a dumb-bell shape, and it comprises first 3211, second portion 3212 and coupling part 3213.The section shape of first 3211, second portion 3212 and coupling part 3213 similar in appearance to the section shape of above-mentioned first 1221, second portion 1222 and coupling part 1223, holds this and repeats no more respectively.
As shown in Figure 3, form at least one recess R between first 3211 and the second portion 3212.Because the formation of recess R makes first conductive pole 321 provide extra surface area (sidewall area of recess R) to contact with primer 14 (Figure 1A), and then makes primer 14 more closely coat first conductive pole 321.Coupling part 3213 connects first 3211 and second portion 3212; And the sectional area of coupling part 3213 is less than the sectional area of first 3211 and second portion 3212, so can provide the surface area of more (compared to omitting coupling part 3213) to contact with primer 14.
Among another embodiment, first conductive pole 421 that first conductive pole 321 of stepped conductive pole 320 can similar Fig. 4 replaces.
Please with reference to Fig. 4, it illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.In the present embodiment; Stepped conductive pole 420 comprises first conductive pole 421 and second conductive pole 422; First conductive pole 421 is connected in second conductive pole 422; Wherein first conductive pole 421 comprises first 3211 and second portion 3212, and first 3211 is connected in second portion 3212, and and second portion 3212 between form a recess R.Because the formation of recess R makes first conductive pole 421 provide extra surface area (sidewall area of recess R) to contact with primer 14, and then makes primer 14 more closely coat second conductive pole 422.Section shape circle, ellipse or the polygon of second conductive pole 422, present embodiment is the example explanation with the circle.
Please with reference to Fig. 5, it illustrates the cutaway view according to the stepped conductive pole of another embodiment of the present invention.In the present embodiment; Stepped conductive pole 520 comprises first conductive pole 421 and second conductive pole 222; First conductive pole 421 is connected in second conductive pole 222; Wherein first conductive pole 421 comprises first 3211 and second portion 3212, and first 3211 is connected in second portion 3212, and and second portion 3212 between form a recess R.Because the formation of recess R makes first conductive pole 421 provide extra surface area (sidewall area of recess R) to contact with primer 14, and then makes primer 14 more closely coat second conductive pole 222.
Comprehensively above-mentioned, the present invention does not limit the geometry of first conductive pole and second conductive pole.One of first conductive pole and second conductive pole can be dumb-bell shape, circle, ellipse, polygon or other shaped form, and another person of first conductive pole and second conductive pole can be dumb-bell shape, circle, ellipse, polygon or other shaped form.
Please with reference to Fig. 6, it illustrates the experimental result picture that meets with stresses of multiple stepped conductive pole.Rectangular A representes meeting with stresses of cylinder conductive pole 620 (non-stepped conductive pole).Rectangular B and C represent meeting with stresses of stepped conductive pole 720 and 820 respectively; Wherein, First conductive pole 721 and second conductive pole 722 of stepped conductive pole 720 are all cylinder; And first conductive pole 821 of stepped conductive pole 820 and second conductive pole 822 are all cylinder, and in addition, the sectional area of second conductive pole 722 is greater than the sectional area of second conductive pole 822 of stepped conductive pole 820.Rectangular D representes the meeting with stresses of stepped conductive pole 520 of the foregoing description, and rectangular E representes the meeting with stresses of stepped conductive pole 320 of the foregoing description.
As shown in Figure 6, compared to meeting with stresses of conductive pole 620,720 and 820, the stepped conductive pole 320 of present embodiment and 520 meet with stresses all less, wherein, stepped conductive pole 320 meet with stresses and more stepped conductive pole little than 520.All the other stepped conductive poles 120,220 and 420 all have similar effect, hold this and repeat no more.Comprehensively above-mentioned; The stepped conductive pole of present embodiment possesses the characteristic that reduction meets with stresses; It is excessive and be damaged (being located in the process of substrate 12 at base material 110) to avoid or improve stepped conductive pole stress, and the useful life that can increase stepped conductive pole.
The manufacturing approach of semiconductor structure 10 below is described.
At first, provide like base material 110 (Figure 1A).
Then, can adopt for example is plating mode, forms stepped conductive pole 120 (Figure 1A) on base material 110, and wherein stepped conductive pole 120 comprises first conductive pole 121 and second conductive pole 122.Second conductive pole 122 is formed on first conductive pole 121, and the sectional area of second conductive pole 122 is less than the sectional area of first conductive pole 121, and wherein whole second conductive pole 122 and first conductive pole 121 overlap.So far, the semiconductor chip 100 of formation shown in Figure 1A.Other stepped conductive pole 220,320,420 and 520 formation method are held this and are repeated no more similar in appearance to the formation method of stepped conductive pole 120.
Then, can semiconductor chip 100 be butted up against substrate 12 (Figure 1A), wherein the position of the stepped conductive pole 120 of semiconductor chip 100 makes semiconductor chip 100 be electrically connected at substrate 12 through stepped conductive pole 120 corresponding to the connection pad 13 of substrate 12.
Then, carry out a reflow process (reflow), make scolder 130 fusings, to be welded on the connection pad 13.After scolder 130 solidifies, the connection pad 13 of its affixed second conductive pole 122 and substrate 12.
Then, form primer 14 (Figure 1A) between semiconductor chip 100 and substrate 12, wherein primer 14 coats stepped conductive pole 120.So far, the semiconductor structure 10 of formation shown in Figure 1A.
Though above-mentioned formation conductive pole is the example explanation with first conductive pole 121 and second conductive pole 122, so the formation method of other first conductive pole and second conductive pole is held this and is repeated no more similar in appearance to first conductive pole 121 and second conductive pole 122.
In sum, though the present invention discloses as above with embodiment, so it is not in order to limit the present invention.Have common knowledge the knowledgeable in the technical field under the present invention, do not breaking away from the spirit and scope of the present invention, when doing various changes and retouching.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. semiconductor chip comprises:
One base material; And
One stepped conductive pole is formed at this base material and comprises:
One first conductive pole; And
One second conductive pole is formed on this first conductive pole, and the sectional area of this second conductive pole is less than the sectional area of this first conductive pole;
Wherein, at least one respectively comprises a first and a second portion in this first conductive pole and this second conductive pole, this second portion be connected in this first and and this first between form a recess.
2. semiconductor chip as claimed in claim 1, wherein the volume of this second conductive pole is less than the volume of this first conductive pole, and the volume of this first conductive pole is between between 0.1 to 5 times of the volume of this second conductive pole.
3. semiconductor chip as claimed in claim 1, wherein at least one respectively comprises in this first conductive pole and this second conductive pole:
A junction branch connects this first and this second portion, and the sectional area of this coupling part is less than the sectional area of this first and the sectional area of this second portion.
4. semiconductor chip as claimed in claim 1, wherein the section shape of this first conductive pole and this second conductive pole respectively is circle, ellipse or polygon.
5. semiconductor chip as claimed in claim 1 comprises:
Two adjacent these stepped conductive poles, the spacing of adjacent this two conductive poles is less than 80 microns.
6. semiconductor chip as claimed in claim 1, wherein the height of this first conductive pole is between 2 to 50 microns, and the height of this second conductive pole is between between 3 to 6 times of the height of this first conductive pole.
7. semiconductor chip as claimed in claim 1, wherein whole this second conductive pole and this first conductive pole overlap.
8. semiconductor structure comprises:
One substrate;
The semiconductor chip, be located on this substrate and comprise:
One base material; And
One stepped conductive pole is formed on this base material and comprises:
One first conductive pole; And
One second conductive pole is formed on this first conductive pole, and the sectional area of this second conductive pole is less than the sectional area of this first conductive pole;
Wherein, at least one respectively comprises a first and a second portion in this first conductive pole and this second conductive pole, this second portion be connected in this first and and this first between form a recess; And
One primer is formed between this substrate and this semiconductor chip.
9. the manufacturing approach of a semiconductor chip comprises:
One base material is provided; And
Form a stepped conductive pole on this base material; Wherein this stepped conductive pole comprises one first conductive pole and one second conductive pole; This second conductive stud is formed on this first conductive pole; The sectional area of this second conductive pole is less than the sectional area of this first conductive pole, and at least one respectively comprises a first and a second portion in this first conductive pole and this second conductive pole, this second portion be connected in this first and and this first between form a recess.
10. manufacturing approach as claimed in claim 9, wherein at least one respectively comprises in this first conductive pole and this second conductive pole:
A junction branch connects this first and this second portion, and the sectional area of this coupling part is less than the sectional area of this first and the sectional area of this second portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210069995.8A CN102593088B (en) | 2012-03-16 | 2012-03-16 | Semiconductor chip, semiconductor structure using same, and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210069995.8A CN102593088B (en) | 2012-03-16 | 2012-03-16 | Semiconductor chip, semiconductor structure using same, and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102593088A true CN102593088A (en) | 2012-07-18 |
| CN102593088B CN102593088B (en) | 2014-04-09 |
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| Application Number | Title | Priority Date | Filing Date |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508671B2 (en) | 2015-04-20 | 2016-11-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
| CN107004612A (en) * | 2014-12-12 | 2017-08-01 | 高通股份有限公司 | The integrated device including photosensitive filler is encapsulated between substrate and tube core |
| CN110579516A (en) * | 2019-09-02 | 2019-12-17 | 青岛歌尔智能传感器有限公司 | nitrogen dioxide gas detection device, manufacturing method thereof and electronic product |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09275106A (en) * | 1996-04-04 | 1997-10-21 | Nec Corp | Structure of bump and its forming method |
| JP2009081153A (en) * | 2007-09-25 | 2009-04-16 | Taiyo Yuden Co Ltd | Semiconductor device and circuit device mounting the same |
-
2012
- 2012-03-16 CN CN201210069995.8A patent/CN102593088B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09275106A (en) * | 1996-04-04 | 1997-10-21 | Nec Corp | Structure of bump and its forming method |
| JP2009081153A (en) * | 2007-09-25 | 2009-04-16 | Taiyo Yuden Co Ltd | Semiconductor device and circuit device mounting the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107004612A (en) * | 2014-12-12 | 2017-08-01 | 高通股份有限公司 | The integrated device including photosensitive filler is encapsulated between substrate and tube core |
| US9508671B2 (en) | 2015-04-20 | 2016-11-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
| US9768139B2 (en) | 2015-04-20 | 2017-09-19 | Advanced Semiconductor Engineering, Inc. | Semiconductor device and semiconductor package |
| CN110579516A (en) * | 2019-09-02 | 2019-12-17 | 青岛歌尔智能传感器有限公司 | nitrogen dioxide gas detection device, manufacturing method thereof and electronic product |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102593088B (en) | 2014-04-09 |
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