CN102571083B - The production method of numerically-controlled oscillator, quadrature carrier and quadrature amplitude modulation system - Google Patents

Abstract

Embodiments of the present invention provide a digitally controlled oscillator, a method for generating a quadrature carrier wave, and a quadrature amplitude modulation system. The digitally controlled oscillator includes: a DDS address accumulator, a phase register, a phase adder, a combiner switch, and a wave table memory and shunt switch. Through the embodiment of the present invention, the generated orthogonal carrier has strict phase orthogonality and amplitude consistency, and the gain error is small; and the carrier frequency resolution is high, the switching time is short, and the carrier phase is continuous; in addition, the device structure is simple and the cost is low .

Description

Digital control oscillator, quadrature carrier generation method and quadrature amplitude modulation modulation system

technical field

The invention relates to the technical field of quadrature amplitude modulation, in particular to a digitally controlled oscillator, a method for generating a quadrature carrier and a quadrature amplitude modulation system.

Background technique

Quadrature Amplitude Modulation (QAM, QuadratureAmplitudeModulation) is a high-order modulation method that combines amplitude and phase, and has higher frequency band utilization and better power utilization. Therefore, it is widely used in medium and large capacity digital microwave communication systems, high data transmission of cable television networks, satellite communications and other fields.

The so-called quadrature amplitude modulation is to use two independent baseband waveforms to suppress the double sideband modulation of two mutually orthogonal carriers of the same frequency. Parallel transmission of digital information. Therefore, the orthogonality (amplitude difference, phase difference, frequency difference) of the two carriers has a great influence on the QAM modulation system.

The general expression of QAM signal is: s(t)=I cos(ωct)+Q sin(ωct), where I and Q are baseband signals, cos(ωct) and sin(ωct) are two orthogonal carrier.

The realization block diagram of the QAM modulation scheme of the Cartesian architecture based on the above formula is shown in Fig. 1 . A QAM modulator of this structure generally includes an encoder 101 , pulse shaping filters 102 , 103 , a carrier generation module 104 , two multipliers 105 , 106 , and an adder 107 . The encoder 101 first performs level conversion on the input bit stream and divides it into two channels, and then maps them to the positions of the constellation points in the constellation diagram respectively to form an in-phase (I, In_phase) signal and a quadrature (Q, Quadrature) signal. In order to reduce intersymbol interference and improve spectrum utilization, I and Q are respectively passed through pulse shaping filters 102 and 103, usually square root raised cosine filters. The output after filtering is multiplied by two carrier waves which are orthogonal to each other to generate in-phase and quadrature components respectively, and the QAM output signal s(t) can be obtained by adding the two components together.

There are two methods for realizing the above-mentioned quadrature modulation: analog and digital. Since the consistency and stability of the analog devices are not ideal, it is difficult to ensure the consistency of the amplitude and the orthogonality of the phase between the two quadrature paths, which greatly affects the performance of the system. With the rapid development of digital technology, digital methods to realize quadrature modulation are widely used because of their better orthogonality.

At present, there have been technical solutions for realizing quadrature modulation by digital methods. The document "Application of DDS in Orthogonal Modulation Technology" ("Application of Electronic Technology", 2002, Volume 28, Issue 03) discloses a direct digital frequency synthesis (DDS, DirectDigitalSynthesizer) satellite based on Cartesian architecture modulation circuit. The circuit uses the DDS chip AD9854 as the core chip to generate two orthogonal carrier waves. The functional block diagram of the carrier generation module is shown in Figure 2. It is mainly composed of high-speed digital signal processor DSP, AD9854, clock generation circuit, band-pass filter, amplifier, frequency multiplier, switch circuit and so on.

Among them, the DDS chip AD9854 has two orthogonal signal output functions. According to the analysis of the spurious index of AD9854, it can't reach the requirement of broadband spurious index in the output frequency band, so select the frequency band (half of the actual output frequency) with better spurious suppression of AD9854, and then perform frequency multiplication. Since the harmonic suppression of the broadband output signal is also difficult to do well, the A and B signals output by the AD9854 are first split, and then frequency multiplied to improve the harmonic suppression and further reduce the spurious.

Taking channel A as an example, one of the output signals has a frequency of 26-35MHz, and outputs a 52-70MHz signal after being amplified, doubled, and filtered; the other one outputs a 35-44MHz signal, and is output after being amplified, doubled, and filtered. 70 ~ 88MHz signal, and finally produce the required sine signal of 52 ~ 88MHz. The principle of the B channel is the same as that of the A channel.

However, in the process of realizing the present invention, the inventor analyzed the realization process of the carrier generation circuit in Fig. 2 and found that the following problems inevitably existed: the AD9854 chip itself is expensive. Moreover, limited by the spurious index of the AD9854 chip, the satellite modulation circuit also performs amplification, frequency doubling and band-pass filtering on the quadrature signal output by the AD9854 chip according to different carrier frequency bands. Therefore, the circuit control is complicated and the cost is high.

Moreover, the two carrier waves output by the AD9854 chip are not strictly in phase quadrature, but have a phase deviation of 0.2 to 1 degree. The resulting two-way carrier will also have a carrier offset error. Carrier offset does not affect the positions of I and Q points on the constellation diagram, and does not have a great impact on the quality of modulated QAM signals. However, from the frequency spectrum of the modulated signal, there will be baseband leakage, so a band-pass filter is required to filter it out, otherwise it will affect the subsequent power amplifier circuit.

In addition, the AD9854 chip embeds two digital/analog converters (DACs) for outputting two analog carriers. Due to the limitations of the manufacturing process, it is difficult to produce an ideal, completely linear DAC. When a digitized sine wave is input to an actual DAC, not only a sine wave is obtained at the output of the DAC, but also its multiple harmonic components (called harmonic distortion) and the mirror images of these harmonic components portion. The harmonic distortion of the two carriers eventually causes the modulated QAM signal to be distorted, spurious amplitude modulation appears in the time domain, and image interference appears in the frequency domain. Because this distortion is in the same frequency band as the modulated signal, it is difficult to filter it out with a bandpass filter.

Contents of the invention

Embodiments of the present invention provide a digitally controlled oscillator, a method for generating a quadrature carrier, and a quadrature amplitude modulation system, with the purpose of making the quadrature carrier have strict phase orthogonality and amplitude consistency, avoiding gain errors, and Simple and cost-effective.

In order to achieve the above object, the embodiment of the present invention provides a digitally controlled oscillator, which includes: a DDS address accumulator, a phase register, a phase adder, a combiner switch, a wavetable memory, and a shunt switch;

The DDS address accumulator accumulates the carrier frequency control word under the action of the first clock, and sends the accumulated result to the phase register and the phase adder;

Under the action of the first clock, the phase register registers and truncates the accumulated result to obtain address information for generating a sine wave;

Under the action of the first clock, the phase adder truncates the accumulated result and adds a phase offset of 90° to obtain address information for generating cosine waves;

Under the action of the second clock, the combination switch combines the address information generating the sine wave and the address information generating the cosine wave; the second clock is of the same source as the first clock, and the the frequency of the second clock is twice the frequency of the first clock;

Under the action of the second clock, the wavetable memory addresses the wavetable according to the result of the combiner switch and outputs wavetable data;

Under the action of the first clock, the shunt switch outputs a cosine wave signal and a sine wave signal according to the wavetable data to generate a required quadrature carrier.

The embodiment of the present invention also provides a method for generating an orthogonal carrier, the method comprising:

Under the action of the first clock, the DDS address accumulator accumulates the carrier frequency control word, and sends the accumulated result to the phase register and the phase adder;

The phase register registers and truncates the accumulated result to obtain address information for generating a sine wave; the phase adder truncates the accumulated result and adds a 90° phase offset to obtain a cosine wave generated address information;

Under the action of the second clock, the combining switch combines the address information generating the sine wave and the address information generating the cosine wave; wherein, the second clock is of the same source as the first clock, and the the frequency of the second clock is twice the frequency of the first clock;

The wavetable memory addresses the wavetable according to the result of the combination switch and outputs wavetable data;

Under the action of the first clock, the shunt switch outputs a cosine wave signal and a sine wave signal according to the wavetable data to generate a required quadrature carrier.

An embodiment of the present invention also provides a quadrature amplitude modulation modulation system, the quadrature amplitude modulation modulation system includes: a field programmable gate array, and the field programmable gate array includes the above-mentioned digitally controlled oscillator.

The beneficial effect of the embodiment of the present invention is that the quadrature carrier output by the digital oscillator has strict phase orthogonality and amplitude consistency, and the gain error is small; and the carrier frequency resolution is high, the switching time is short, and the carrier phase is continuous; in addition , The device structure is simple and the cost is low.

Description of drawings

The drawings described here are used to provide further understanding of the present invention, constitute a part of the application, and do not limit the present invention. In the attached picture:

Fig. 1 is a functional block diagram of quadrature amplitude modulation in the prior art;

Fig. 2 is the realization block diagram of the orthogonal carrier wave based on dedicated chip of prior art;

3 is a schematic diagram of the composition of a digitally controlled oscillator according to an embodiment of the present invention;

FIG. 4 is a flowchart of a method for generating an orthogonal carrier according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a quadrature amplitude modulation system according to an embodiment of the present invention.

detailed description

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.

An embodiment of the present invention provides a numerically controlled oscillator (NCO, NumericalControlledOscillator), as shown in FIG. Wave table memory 305, shunt switch 306; Wherein,

The DDS address accumulator 301 accumulates the carrier frequency control word K under the action of the first clock, and sends the accumulated result to the phase register 302 and the phase adder 303;

The phase register 302 registers and truncates the accumulated result of the DDS address accumulator 301 under the action of the first clock, and obtains As as the address information for generating the sine wave;

The phase adder 303 truncates the accumulated result of the DDS address accumulator 301 under the action of the first clock, and adds a phase offset of 90° to obtain Ac as the address information for generating the cosine wave;

Combiner switch 304 combines Ac and As under the action of the second clock; wherein, the second clock is of the same source as the first clock, and the frequency of the first clock is fc, and the frequency of the second clock is 2fc; the second clock The frequency is twice the frequency of the first clock, and the period of the first clock is twice the period of the second clock;

The wavetable memory 305 addresses the wavetable according to the result of the combiner switch 304 and outputs wavetable data under the action of the second clock;

Under the function of the first clock, the shunt switch 306 outputs the cosine wave signal and the sine wave signal according to the wavetable data to generate the required quadrature carrier.

In this embodiment, the DDS address accumulator 301 accumulates the carrier frequency control word K every time the first clock with frequency fc comes. The accumulated N-bit result is sent to the phase register 302 and the phase adder 303 at the same time.

In this embodiment, in order to obtain extremely high frequency resolution, the bit width N of the DDS address accumulator 301 is required to be very large; however, due to size and cost constraints, the address bit width Y corresponding to the capacity of the wavetable memory 305 is usually much smaller than that of the DDS The address bit width of the address accumulator 301 is N. Therefore, the phase register 302 and the phase adder 303 must truncate the address before addressing the wavetable memory 305 .

In this embodiment, according to the relational expression: sin(α+π/2)=cos(α), under the first clock whose frequency is fc, the phase adder 303 first truncates the result of the DDS address accumulator 301, and then Add a 90-degree phase offset to it (specifically, add the binary number "01" to the upper 2 bits, and keep the lower bits unchanged), so that the added value Ac can be obtained as the address for generating the cosine wave.

In this embodiment, under the second clock frequency of 2fc, the combining switch 304 combines Ac and As into one. Specifically, in the first half cycle of the first clock, Ac is used as the read address of the wavetable memory 305; in the second half cycle of the first clock, As is used as the read address of the wavetable memory 305.

In this embodiment, the wavetable memory 305 stores one period of sine wave wavetable data (the address space is 2 ^Y , and Y is the address bit width of the wavetable memory). Specifically, the wavetable memory 305 outputs the wavetable data addressed by Ac in the first half period of the first clock, and outputs the wavetable data addressed by As in the second half period of the first clock. And send the read wave table data to the shunt switch 306 .

In this embodiment, every time a first clock with frequency fc comes, the shunt switch 306 outputs 2 channels of wavetable data, one is the cosine wave signal sin obtained by addressing Ac, and the other is obtained by addressing As Sine wave signal cos. Sin and cos are digitized sine and cosine waves, and the bit width is equal to the data bit width of the wave table memory 305; the frequency of both is fc*K/2 ^N , where K is the carrier frequency control word, and N is the DDS address accumulator 301 The address bit width. Usually N>Y, in actual implementation, the Y bit in the N-bit output of the DDS address accumulator can be intercepted as the read address of the wavetable memory.

In this embodiment, the digitally controlled oscillator is implemented by a Field-Programmable Gate Array (FPGA, Field-Programmable Gate Array).

It can be seen from the above embodiments that the quadrature carrier output by the digital oscillator has strict phase orthogonality and amplitude consistency, and the gain error is small; because the two carrier waves are taken out from the same wavetable memory, the amplitudes are strictly equal , to avoid the carrier gain error; the phase difference of the two carriers is strictly 90 degrees, so there is no phase offset of the quadrature carrier.

Moreover, the resolution of the carrier frequency is high, and the carrier frequency is equal to fc*K/2 ^N. As long as the bit width N of the DDS address accumulator is large enough, a sufficiently high frequency resolution can be obtained;

The switching time of the carrier frequency is short. When the digital oscillator receives the new carrier frequency control word, it only needs a few clock pulses with frequency fc to generate the quadrature carrier wave of the new frequency;

The phase of carrier frequency agility is continuous, and the change of carrier output frequency is realized by changing the frequency control word. What is changed in realization is the carrier phase growth rate, and the carrier phase itself is continuous.

In addition, it adopts an all-digital structure and is easy to realize by FPGA, so it is very beneficial to the realization of QAM modulation function; the structure is simple and the cost is low.

The embodiment of the present invention also provides a method for generating an orthogonal carrier, as shown in FIG. 4, the method includes:

Step 401, under the action of the first clock, the DDS address accumulator accumulates the carrier frequency control word, and sends the accumulated result to the phase register and the phase adder;

Step 402, under the action of the first clock, the phase register registers and truncates and accumulates the result to obtain the address information for generating the sine wave; the phase adder adds a 90° phase offset to the truncated and accumulated result to obtain Generate the address information of the cosine wave;

Step 403, under the action of the second clock, the combiner switch combines the address information generating the sine wave and the address information generating the cosine wave; wherein, the second clock has the same source as the first clock, and the frequency of the second clock is the first twice the frequency of a clock;

Step 404, under the action of the second clock, the wavetable memory addresses the wavetable according to the result of the combiner switch and outputs wavetable data;

Step 405 , under the action of the first clock, the shunt switch outputs the cosine wave signal and the sine wave signal according to the wave table data to generate the required quadrature carrier wave.

When step 403 is implemented, the combining switch combines the address signal generating the sine wave and the address signal generating the cosine wave, specifically including:

In the first half cycle of the first clock, the address information that generates the cosine wave is used as the read address information of the wave table memory; in the second half cycle of the first clock, the address information that generates the sine wave is used as the read address information of the wave table memory Address information.

In this embodiment, the wavetable memory stores a sine wave wavetable of one period. When step 404 is implemented, the wavetable memory addresses the wavetable according to the result of the combining switch and outputs the wavetable data, specifically including:

In the first half cycle of the first clock, address in the sine wave table according to the address signal that generates the cosine wave, and output the wave table data obtained after addressing; in the second half cycle of the first clock, according to the address signal that generates the sine wave The address signal is addressed in the sine wave table, and the wave table data obtained after addressing is output.

In this embodiment, the generation method is realized by a field programmable gate array.

It can be seen from the above embodiments that the orthogonal carrier generated by the above method has strict phase orthogonality and amplitude consistency, and the gain error is small; and the carrier frequency resolution is high, the switching time is short, and the carrier phase is continuous; in addition, the device structure is simple ,low cost.

The embodiment of the present invention also provides a quadrature amplitude modulation modulation system, as shown in FIG. 5 , the quadrature amplitude modulation modulation system includes: FPGA501, and the FPGA501 includes the aforementioned digitally controlled oscillator 5011.

As shown in FIG. 5, further, the quadrature amplitude modulation system further includes: a central processing unit 502 and a clock circuit 503; wherein,

Central processing unit 502 is provided with carrier frequency control word and modulation frequency control word and modulation type (FPGA501 can be set to select the data to be modulated locally, and modulation type is internal adjustment for FPGA501; also can be set by the I, Q that analog-to-digital converter sends in data, the modulation type is external transfer). The clock circuit 503 provides a high-precision stable clock source for the FPGA 501 .

As shown in Figure 5, further, the quadrature amplitude modulation modulation system also includes: user interface 504, Flash memory 505, in-phase analog-to-digital converter (I_ADC) 506, quadrature analog-to-digital converter (Q_ADC) 507 and modulation wave table memory 508; wherein,

The central processing unit 502 realizes system control and signal processing, and receives user control through the user interface 504; and the built-in file stored in the Flash memory 505 or the file to be modulated issued by the user interface 504 is encoded into I and Q data and then sent to the FPGA501 . Among them, it can be coded according to the QAM modulation type set by the user, such as 16QAM, 64QAM, 8PSK and so on.

The user interface 504 receives the user's local or remote control, including through a general-purpose interface bus (GPIB, General-PurposeInterfaceBus), a local area network (LAN, LocalAreaNetwork), a universal serial bus (USB, UniversalSerialBus) and the like. Flash memory 505 stores built-in files to be modulated.

FPGA501 sends the I, Q data encoded by central processing unit 502 to modulation wave table memory 508, and modulation wave table memory 508 stores I, Q data; Read out the data to be modulated.

The in-phase analog-to-digital converter 506 and the quadrature analog-to-digital converter 507 are respectively used to convert the analog signals of the I and Q data input from the outside into digital forms and send them to the FPGA 501 .

As shown in Figure 5, further, the quadrature amplitude modulation modulation system further includes: a digital-to-analog converter 509 and an analog circuit 510;

The digital-to-analog converter (DAC) 509 converts the digital quadrature amplitude modulation signal output by the FPGA 501 into an analog signal; the analog circuit 510 processes the analog signal output by the digital-to-analog converter 509, including filtering, attenuation, and amplification.

As shown in Figure 5, the FPGA501 specifically further includes: a clock module 5012, a CPU interface module 5013, a modulation controller 5014, a first multiplier 5015, a second multiplier 5016 and an adder 5017; wherein,

The clock module 5012 performs frequency synthesis on the clock provided by the clock circuit 503 to generate the required first clock with a frequency of fc and a second clock with a frequency of 2fc, the second clock has the same source as the first clock, and the frequency of the second clock is twice the frequency of the first clock.

The CPU interface module 5013 implements the communication between the FPGA 501 and the central processing unit 502, parses the data issued by the central processing unit 502 into frequency control words and sends them to the digital control oscillator 5011, and sends the data to be modulated and the modulation frequency words to the modulation control device 5014.

Before outputting the quadrature amplitude modulation modulation signal, the modulation controller 5014 writes the data to be modulated into the modulation wavetable memory 508; when outputting the quadrature amplitude modulation modulation signal, the I data is sent to the first multiplier 5015, and the Q data is sent to the first multiplier 5015. to the second multiplier 5016.

Among them, if the user requires internal modulation, the modulation controller 5014 takes out the I and Q data to be modulated from the modulation wave table memory 508 at the modulation frequency determined by the modulation frequency word (that is, the symbol rate of QAM modulation), and sends them to the multiplier If the user requires external modulation, the modulation controller 5014 sends the converted I and Q data to the multiplier module through the communication interface with the in-phase analog-to-digital converter 506 and the quadrature analog-to-digital converter 507.

The first multiplier 5015 realizes the multiplication of the I data and the cosine wave signal output by the digitally controlled oscillator 5011, and the second multiplier 5016 realizes the multiplication of the Q data and the sine wave signal output by the digitally controlled oscillator 5011;

The adder 5017 sums the in-phase component sent by the first multiplier 5015 and the quadrature component sent by the second multiplier 5016 , and sends the summed result to the digital-to-analog converter 509 .

It can be seen from the above embodiments that the quadrature carrier output by the digital oscillator has strict phase orthogonality and amplitude consistency, and the gain error is small; because the two carrier waves are taken out from the same wavetable memory, the amplitudes are strictly equal , to avoid the carrier gain error; the phase difference of the two carriers is strictly 90 degrees, so there is no phase offset of the quadrature carrier.

Moreover, the resolution of the carrier frequency is high, and the carrier frequency is equal to fc*K/2 ^N. As long as the bit width N of the DDS address accumulator is large enough, a sufficiently high frequency resolution can be obtained; the switching time of the carrier frequency is short, and when the digital oscillator After receiving the new carrier frequency control word, only a few clock pulses with frequency fc can generate the quadrature carrier wave of the new frequency; the phase of the carrier frequency agility is continuous, and the change of the carrier output frequency is controlled by changing the frequency It is implemented by words, and what is changed in implementation is the phase growth rate of the carrier, and the carrier phase itself is continuous.

In addition, it adopts an all-digital structure and is easy to realize by FPGA, so it is very beneficial to the realization of QAM modulation function; the quadrature carrier in digital form is directly multiplied by I and Q data in digital form, avoiding the use of two carrier DACs in traditional implementation methods , which avoids the harmonic distortion of the two orthogonal carrier waves caused by the nonlinear distortion of the DAC, and also reduces the cost.

Those of ordinary skill in the art can further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the hardware and Interchangeability of software. In the above description, the components and steps of each example have been generally described according to their functions. Whether these functions are executed by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be regarded as exceeding the scope of the present invention.

The steps of the methods or algorithms described in connection with the embodiments disclosed herein may be implemented by hardware, software modules executed by a processor, or a combination of both. Software modules can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other Any other known storage medium.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (13)

1. A digitally controlled oscillator, characterized in that, said digitally controlled oscillator comprises: a DDS address accumulator, a phase register, a phase adder, a combiner switch, a wavetable memory and a shunt switch; The DDS address accumulator accumulates the carrier frequency control word under the action of the first clock, and sends the accumulated result to the phase register and the phase adder; Under the action of the first clock, the phase register registers and truncates the accumulated result to obtain address information for generating a sine wave; Under the action of the first clock, the phase adder truncates the accumulated result and adds a phase offset of 90° to obtain address information for generating cosine waves; Under the action of the second clock, the combination switch combines the address information generating the sine wave and the address information generating the cosine wave; the second clock is of the same source as the first clock, and the the frequency of the second clock is twice the frequency of the first clock; Under the action of the second clock, the wavetable memory addresses the wavetable according to the result of the combiner switch and outputs wavetable data; Under the action of the first clock, the shunt switch outputs a cosine wave signal and a sine wave signal according to the wavetable data to generate a quadrature carrier wave. 2. The digitally controlled oscillator according to claim 1, wherein the combining switch is specifically used for: In the first half cycle of the first clock, the address information for generating the cosine wave is used as the read address information of the wavetable memory; In the second half period of the first clock, the address information for generating the sine wave is used as the read address information of the wavetable memory. 3. The digitally controlled oscillator according to claim 2, wherein the wave table memory stores a cycle of sine wave wave table, and the wave table memory is specifically used for: In the first half cycle of the first clock, addressing in the sine wave table according to the address information for generating the cosine wave, outputting the wave table data obtained after addressing; In the second half cycle of the first clock, according to the address information for generating the sine wave, the sine wave table is addressed, and the wave table data obtained after addressing is output. 4. The digitally controlled oscillator according to claim 1, wherein the digitally controlled oscillator is realized by a field programmable gate array. 5. A method for generating an orthogonal carrier, characterized in that the method comprises: Under the action of the first clock, the DDS address accumulator accumulates the carrier frequency control word, and sends the accumulated result to the phase register and the phase adder; The phase register registers and truncates the accumulated result to obtain address information for generating a sine wave; the phase adder truncates the accumulated result and adds a 90° phase offset to obtain a cosine wave generated address information; Under the action of the second clock, the combining switch combines the address information generating the sine wave and the address information generating the cosine wave; wherein, the second clock is of the same source as the first clock, and the the frequency of the second clock is twice the frequency of the first clock; The wavetable memory addresses the wavetable according to the result of the combination switch and outputs wavetable data; Under the action of the first clock, the shunt switch outputs a cosine wave signal and a sine wave signal according to the wavetable data to generate a quadrature carrier wave. 6. The generating method according to claim 5, wherein the combining switch combines the address signal generating the sine wave and the address signal generating the cosine wave, specifically comprising: In the first half cycle of the first clock, the address information for generating the cosine wave is used as the read address information of the wavetable memory; In the second half period of the first clock, the address information for generating the sine wave is used as the read address information of the wavetable memory. 7. generation method according to claim 6, is characterized in that, described wave table memory stores the sine wave wave table of one cycle, and described wave table memory addresses wave table according to the result of described combining switch and Output wavetable data, including: In the first half cycle of the first clock, addressing in the sine wave table according to the address signal generating the cosine wave, outputting the wave table data obtained after addressing; In the second half cycle of the first clock, according to the address signal for generating the sine wave, the sine wave table is addressed, and the wave table data obtained after addressing is output. 8. The generating method according to claim 5, characterized in that, the generating method is realized by a field programmable gate array. 9. A quadrature amplitude modulation modulation system, characterized in that the quadrature amplitude modulation modulation system comprises: a field programmable gate array, and the field programmable gate array comprises the digitally controlled oscillator as claimed in claim 1. 10. The quadrature amplitude modulation modulation system according to claim 9, characterized in that, the quadrature amplitude modulation modulation system further comprises: a central processing unit and a clock circuit; The central processing unit sets a carrier frequency control word, a modulation frequency control word, and a modulation type for the field programmable gate array; the clock circuit provides a clock source for the field programmable gate array. 11. quadrature amplitude modulation modulation system according to claim 10, is characterized in that, described quadrature amplitude modulation modulation system also comprises: user interface, Flash memory, in-phase analog-to-digital converter, quadrature analog-to-digital converter and modulation wave table memory; The central processing unit realizes system control and signal processing, receives user control through the user interface; and encodes the built-in file stored in the Flash memory or the file to be modulated issued by the user interface into in-phase or quadrature Send the data to the field programmable gate array; The modulated wave table memory stores the encoded in-phase or quadrature data of the central processing unit; the in-phase analog-to-digital converter and the quadrature analog-to-digital converter are used to convert the externally input in-phase or quadrature data into analog signals converted into digital form and sent to the FPGA. 12. The quadrature amplitude modulation modulation system according to claim 11, characterized in that, the quadrature amplitude modulation modulation system further comprises: a digital-to-analog converter and an analog circuit; The digital-to-analog converter converts the digital quadrature amplitude modulation signal output by the field programmable gate array into an analog signal; the analog circuit processes the analog signal output by the digital-to-analog converter. 13. quadrature amplitude modulation system according to claim 12, is characterized in that, described field programmable gate array also comprises: clock module, CPU interface module, modulation controller, first multiplier, second multiplier and Adder; The clock module performs frequency synthesis on the clock provided by the clock circuit to generate the required first clock and second clock, and the frequency of the second clock is twice the frequency of the first clock; The CPU interface module realizes the communication between the field programmable gate array and the central processing unit, parses the data issued by the central processing unit into a carrier frequency control word and sends it to the digitally controlled oscillator, and The data to be modulated and the modulation frequency control word are sent to the modulation controller; Before outputting the quadrature amplitude modulation modulation signal, the modulation controller writes the data to be modulated into the modulation wavetable memory; when outputting the quadrature amplitude modulation modulation signal, sends the in-phase data to the first multiplier, sending the quadrature data to the second multiplier; The first multiplier implements the multiplication of the in-phase data and the cosine wave signal output by the digitally controlled oscillator to generate an in-phase component, and the second multiplier implements the quadrature data and the digitally controlled oscillator The multiplication of the output sine wave signals generates quadrature components; The adder sums the in-phase component sent by the first multiplier and the quadrature component sent by the second multiplier, and sends the summed result to the digital-to-analog converter.