CN102570998B - High-frequency power amplifier device - Google Patents

Abstract

A high-frequency power amplifier device capable of reducing call current is disclosed. For example, a high-frequency power amplifier device has first and second power amplifier circuits, first and second transmission lines, and a region in which the first and second transmission lines are arranged close to each other. Depending on the output level, the first or second power amplifier circuit is activated. When the second power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in the same direction so that magnetic coupling occurs to strengthen the magnetic force of each transmission line. On the other hand, when the first power amplifier circuit is activated, currents flowing in the first and second transmission lines are transmitted in opposite directions so that magnetic coupling occurs to weaken the magnetic force of each transmission line.

Description

High Frequency Power Amplifier Equipment

Cross References to Related Applications

The disclosure of Japanese Patent Application No. 2010-280296 filed on December 16, 2010 including specification, drawings and abstract is hereby incorporated by reference in its entirety.

technical field

The present invention relates to a high-frequency power amplifier device, and more particularly, to an effective technique applicable to a high-frequency power amplifier device that changes a transistor to be used according to an output level setting for transmission.

Background technique

In the described construction, for example, in US Patent No. 7,135,919, the first amplifier and the second amplifier are coupled to a common output node. The first and second amplifiers are activated complementary. A transmission line having a length of λ/4 is provided between the second amplifier and the common output node.

In recent years, high-frequency power amplifier devices (high-frequency power amplifier modules) required to realize transmission functions such as mobile phones have become smaller in size and reduced call current. The call current is the probability distribution of the usage frequency per output level for transmission and the integrated value of the consumption current per output level. For example, reducing the call current reduces the power consumption of, for example, a mobile phone and increases the life of its battery. FIG. 10 shows an example of the probability distribution of each output level usage frequency in a W-CDMA (Wideband Code Division Multiple Access) mobile phone. As shown in Figure 10, low to medium output levels centered around 0 dBm are often used in eg W-CDMA mobile phones. Therefore, improving the power-added efficiency (PAE) of the high-frequency power amplifier module at low to medium output levels is beneficial to reduce talk current.

For example, power added efficiency at low to medium output levels can be improved by utilizing the configuration shown in FIGS. 11A to 11C. 11A to 11C show a high-frequency power amplifier device investigated as a premise of the present invention. FIG. 11A is a schematic diagram for explaining an example configuration of essential parts of a high-frequency power amplifier device. FIG. 11B shows exemplary characteristics of the main path shown in FIG. 11A . FIG. 11C illustrates exemplary properties of the subpaths shown in FIG. 11A . The high-frequency power amplifier device shown in FIG. 11A includes a main power amplifier circuit (power amplifier circuit) PA2m that amplifies a signal input from a common input node N2 through a capacitor C1 and a signal that is input from the common input node N2 through a capacitor C2. Amplified sub-power amplifier circuit PA2s.

The output of the main power amplifier circuit PA2m is coupled to one end of the transmission line LNmn, and the output of the sub power amplifier circuit PA2s is coupled to one end of the transmission line LNmn through the transmission line LNsub. The capacitor C5 is coupled between the other end of the transmission line LNmn and the output node Pout. The capacitor C4 is coupled between the other end of the transmission line LNmn and the ground power supply voltage GND. The capacitor C3 and the NMOS transistor MNsw are sequentially coupled to the output node (one end of the transmission line LNsub) of the sub power amplifier circuit PA2s and directed to the ground power supply voltage GND. The transistors included in the main power amplifier circuit PA2m are larger in size than the transistors included in the sub power amplifier circuit PA2s. High power can be transmitted by activating the main power amplifier circuit PA2m, deactivating the sub power amplifier circuit PA2s, performing control to turn off the NMOS transistor MNsw with the control signal Vsw, and transmitting the output power of the main power amplifier circuit PA2m to the output node Pout through the transmission line LNmn. The output level is sent to the output node Pout. By activating the sub power amplifier circuit PA2s, deactivating the main power amplifier circuit PA2m, performing control to turn on the NMOS transistor MNsw with the control signal Vsw and transmit the output power of the sub power amplifier circuit PA2s to the output node Pout through the transmission line LNsub and the transmission line LNmn Low to medium output levels can be delivered to output node Pout.

As described above, when using the example configuration shown in FIG. 11A , the power amplifier circuit PA2 s with a small transistor size can realize power amplification at low to middle output levels. Therefore, power added efficiency (PAE) can be improved. However, it has been found that this example configuration may make it difficult to optimize the design of the transmission line LNsub. First, when the main path is operated due to activation of the main power amplifier circuit PA2m, the impedance observed from the output node of the main power amplifier circuit PA2m toward the transmission line LNsub is high because control is performed to turn off the NMOS transistor MNsw. Therefore, ideally, no power loss occurs through the transmission line LNsub. Actually, however, the NMOS transistor MNsw has an off capacitance (Coff). Therefore, due to the series resonant circuit formed by the transmission line LNsub, the capacitor C3 and the off capacitance (Coff), it is difficult to completely avoid the power loss through the transmission line LNsub. As shown in FIG. 11B , the power loss increases (thus reducing the PAE) as the length of the transmission line LNsub increases (as the number of inductor components increases) because this lowers the resonant frequency of the series resonant circuit towards the carrier frequency.

Meanwhile, when the sub-path is operated due to the activation of the sub-power amplifier circuit PA2s, the output impedance (for example, tens of ohms) of the sub-power amplifier circuit PA2s is converted by the capacitor C3, the transmission line LNsub, the transmission line LNmn, the capacitor C4, and the capacitor C5. to a predetermined impedance (for example, 50 ohms) because control is performed to turn on the NMOS transistor MNsw. In this case, PAE increases as the length of the transmission line LNsub increases as shown in FIG. 11C. The reason is that a sufficient amount of clockwise rotation can be obtained in the Smith chart (impedance chart) shown in FIG. 12 when the length of the transmission line LNsub is increased (when the number of inductor components is increased). The resulting amount of clockwise rotation can then be combined with capacitor C3 to achieve sufficient impedance transformation.

As mentioned above, the transmission line LNsub is preferably short during main path operation to improve power added efficiency (PAE). Conversely, during sub-path operation, it is preferred that the transmission line LNsub be long to improve PAE. In order to reduce the talk current and improve the overall PAE, it is necessary to devise a scheme that will solve the above-mentioned balance problem. It should be noted that when the length of the transmission line LNsub is eg λ/4, the transmission line LNsub can be used as a stub during the main path operation. However, for example when using a W-CDMA frequency of 2 GHz, the value λ/4 represents approximately several centimeters. Therefore, it may not be possible to reduce the size of the high-frequency power amplifier module.

Contents of the invention

The present invention has been made in view of the above circumstances and provides a high-frequency power amplifier device capable of reducing call current. The foregoing and other advantages and novel features of the invention will become apparent from the following detailed description and accompanying drawings.

Representative embodiments of the invention disclosed in this document are outlined below.

A high-frequency power amplifier device according to a representative embodiment of the present invention includes a first power amplifier circuit, a second power amplifier circuit, a first transmission line, a second transmission line, a first capacitor, a second capacitor, a transistor switch, and a control circuit. Both the first and second power amplifier circuits amplify the first input signal. The first transmission line is coupled at one end to the output node of the first power amplifier circuit and at the other end to the first capacitor. The second transmission line is coupled at one end to the output node of the first power amplifier circuit and at the other end to the output node of the second power amplifier circuit. The second capacitor and the transistor switch are arranged in series between the output node of the second power amplifier circuit and the ground supply voltage. The control circuit activates the first power amplifier circuit or the second power amplifier circuit according to the mode setting signal. When the first power amplifier circuit is activated, the control circuit drives the transistor switch to turn off. On the other hand, when the second power amplifier circuit is activated, the control circuit drives the transistor switch to conduct. The first and second transmission lines include magnetic coupling regions proximate to the first and second transmission lines to induce magnetic coupling. In the magnetic coupling region, the first and second transmission lines are arranged so that the first transmission line originating from the output node side of the first power amplifier circuit is in the same direction as the second transmission line originating from the output node side of the second power amplifier circuit Extend up.

When the first power amplifier circuit is activated during use of the above configuration, magnetic coupling occurs in the magnetic coupling region to weaken the magnetic force of each transmission line. On the other hand, when the second power amplifier circuit is activated during use of the above configuration, magnetic coupling occurs in the magnetic coupling region to strengthen the magnetic force of each transmission line. As a result, the second transmission line appears short when the first power amplifier circuit is activated and appears long when the second power amplifier circuit is activated. Therefore, the above-mentioned balance problem can be solved to reduce the call current and reduce the power consumption of the high-frequency power amplifier device.

In conclusion, the representative embodiment of the present invention disclosed in this document is advantageous because it reduces the talk current in a high frequency power amplifier device.

Description of drawings

FIG. 1 is a block diagram for explaining an example configuration of a high-frequency power amplifier device according to a first embodiment of the present invention;

2A and 2B are circuit diagrams, wherein FIG. 2A is a circuit diagram for explaining in detail an example configuration of basic parts of the high-frequency power amplifier device shown in FIG. Example configurations for further detailed circuit diagrams;

3A and 3B show the operating principle of the high-frequency power amplifier device shown in FIG. 2A, wherein FIG. 3A is a diagram for explaining an example of an operation performed when a sub-path is used, and FIG. Diagram illustrating an example of what to do when using the main path;

4A to 4C show example effects of magnetic coupling during use of the subpaths of the high-frequency power amplifier devices shown in FIGS. 2A and 2B , wherein FIG. 4A is a supplementary schematic diagram for illustrating the prerequisites for such magnetic coupling, And FIGS. 4B and 4C are diagrams for explaining verification results;

5A and 5B show various characteristics exhibited during use of the high-frequency power amplifier device shown in FIGS. 2A and 2B, wherein FIG. 5A is a diagram for explaining characteristics of power-added efficiency (PAE), and 5B is a diagram for explaining the characteristics of the adjacent channel leakage ratio;

FIG. 6 is a schematic diagram related to a high-frequency power amplifier device according to a second embodiment of the present invention and illustrating an example mounting structure based on the configuration example shown in FIGS. 2A and 2B;

FIG. 7 is a schematic diagram related to a high-frequency power amplifier device according to a third embodiment of the present invention and illustrating an example mounting structure based on the configuration example shown in FIGS. 2A and 2B;

8 is a schematic diagram for explaining in detail an example of a wiring circuit board layout using the mounting structure shown in FIG. 7;

9 is a circuit diagram relating to a high-frequency power amplifier device according to a fourth embodiment of the present invention and illustrating in detail an example configuration of a second-stage power amplifier circuit portion shown in FIG. 1;

FIG. 10 is a diagram for explaining an example of a probability distribution of each output level usage frequency in a W-CDMA mobile phone;

11A to 11C illustrate the high-frequency power amplifier device studied as a premise of the present invention, wherein FIG. 11A is a diagram illustrating exemplary characteristics of the main path, and FIG. 11C is a diagram illustrating exemplary characteristics of the sub-path shown in FIG. 11A;

Fig. 12 is a supplementary schematic diagram of Figs. 11A to 11C.

detailed description

In the following embodiments, the present invention is described by dividing the present invention into a plurality of parts or embodiments where necessary for convenience. However, these parts or embodiments are not independent of each other unless explicitly stated otherwise. There is such a relationship that, for example, one part or embodiment is a modification, detailed description, or supplementary explanation of a part or the whole of another part or embodiment. In addition, in the following embodiments, when referring to the number of elements and the like (including, for example, the number of blocks, numerical values, quantities, and ranges), unless otherwise specifically specified or the number is obviously limited to the specified number in principle, the number is not limited at the specified number and can be set to a value higher or lower than the specified number.

Furthermore, in the embodiments described below, it is obvious that a component (including element steps) is not always indispensable unless otherwise specified or except for the case where the component is obviously essential in principle. Similarly, in the following embodiments, for example, when referring to the shapes of parts and the positional relationship between parts, substantially approximate or similar shapes and the like are included therein, unless otherwise specified or unless they can be conceived obviously in principle Except for the cases excluded above. The same applies to the above numerical values and ranges.

Although a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) (abbreviated as MOS transistor) is used as an example of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) (abbreviated as MIS transistor) in this embodiment, a non-oxide film as a gate transistor is not excluded. pole insulating film. Although the coupling method of the substrate potential of the MOS transistor is not particularly indicated in the drawings, it is not particularly limited as long as it allows the MOS transistor to operate normally.

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In all the drawings for explaining the embodiments, similar elements are denoted by the same reference numerals and are not described redundantly.

first embodiment

FIG. 1 is a block diagram for explaining an example configuration of a high-frequency power amplifier device according to a first embodiment of the present invention. The high-frequency power amplifier device (high-frequency power amplifier module) HPAMD shown in FIG. 1 includes, for example, a ceramic wiring circuit board (PCB). Install the high-frequency power amplifier chip HPAIC and the control chip CTLIC on the PCB. In addition, the wiring layer on the PCB is used to form the output matching circuit MNT_O. The high-frequency power amplifier device HPAMD is used for W-CDMA and TDS-CDMA (Time Division Synchronous Code Division Multiple Access), but is not particularly limited to W-CDMA and TDS-CDMA. The high-frequency power amplifier chip HPAIC is a so-called MMIC (Monolithic Microwave Integrated Circuit) and includes an input matching circuit MNT_I, a first-stage power amplifier circuit (power amplifier circuit) PA1, an intermediate-stage matching circuit MNT_S, and a second-stage power amplifier circuit PA2m , PA2s.

The input matching circuit MNT_I provides impedance matching between the external terminal (input power signal Pin) of the high frequency power amplifier device HPAMD and the input node of the first stage power amplifier circuit PA1. The first-stage power amplifier circuit PA1 receives the power supply voltage Vcc1 through the external terminal of the high-frequency power amplifier device HPAMD and amplifies a signal input from the input power signal Pin through the input matching circuit MNT_I. The middle-stage matching circuit MNT_S provides impedance matching between the output node of the first-stage power amplifier circuit PA1 serving as the first stage and the input nodes of the second-stage power amplifier circuits PA2m, PA2s serving as the second stage. The second-stage power amplifier circuits PA2m, PA2s receive the power supply voltage through the external terminals of the high-frequency power amplifier device HPAMD, have their input nodes and output nodes commonly coupled, and receive the power supply voltage from the first-stage power amplifier circuit PA1 through the intermediate-stage matching circuit MNT_S The input signal is amplified. In this instance, the second-stage power amplifier circuit PA2m or the second-stage power amplifier circuit PA2s is selected according to a control signal from the control chip CTLIC. The selected second stage power amplifier circuit is then used to perform the amplification operation.

The output matching circuit MNT_O provides impedance matching between the common output node of the second stage power amplifier circuits PA2m, PA2s and the external terminal (output power signal Pout) of the high frequency power amplifier device HPAMD. The control chip CTLIC receives the power supply voltage Vbat through the external terminal of the high-frequency power amplifier device HPAMD and, if necessary, sets the signal Vmode and the enable signal Ven to the high-frequency power amplifier chip HPAIC according to the mode input through the external terminal of the high-frequency power amplifier device HPAMD Take control. More specifically, for example, when the enable signal Ven is at a high level (activated), the control chip CTLIC provides a bias voltage to the first-stage power amplifier circuit PA1 and the second-stage power amplifier circuit PA2m (or the second-stage power amplifier circuit PA2m). circuit PA2s) (ie, activates (enables) the power amplifier circuit). When the enable signal Ven is at a low level (deactivated), the control chip CTLIC cuts off the supply of the bias voltage (ie, deactivates (disables) the power amplifier circuit). In this case, the bias voltage is supplied to the second-stage power amplifier circuit PA2m or the second-stage power amplifier circuit PA2s according to the logic level of the mode setting signal Vmode. For example, a high-frequency signal processing device (not shown) having a modulation function and the like is located upstream of the input power signal Pin, and a duplexer, antenna switch, and antenna are located downstream of the output power signal Pout. For example, the mode setting signal Vmode and the enable signal Ven are generated by a baseband processing circuit located upstream.

FIG. 2A is a circuit diagram for explaining in detail an example configuration of essential parts of the high-frequency power amplifier device shown in FIG. 1 . FIG. 2B is a circuit diagram for further detailing an example configuration of certain portions of FIG. 2A . Referring to FIG. 2A , in addition to the second-stage power amplifier circuits PA2m and PA2s and the capacitors C1 and C2 forming the middle-stage matching circuit MNT_S, the high-frequency power amplifier chip HPAIC also includes a capacitor C3. The signal output from the above-mentioned first-stage power amplifier circuit PA1 is input into the second-stage power amplifier circuit PA2m through the capacitor C1 and input into the second-stage power amplifier circuit PA2s through the capacitor C2. One end of the capacitor C3 is coupled to the output node of the second stage power amplifier circuit PA2s. The control chip CTLIC includes switching N-channel MOS transistors (NMOS transistors) MNsw. The NMOS transistor MNsw includes, for example, LDMOS (Laterally Diffused MOS). The on/off operation of the NMOS transistor MNsw is controlled by a control signal Vsw input to its gate. Its source is coupled to the ground supply voltage GND, and its drain is coupled to the other end of the capacitor C3. The control signal Vsw is generated according to the mode setting signal Vmode shown in FIG. 1 .

As shown in FIG. 2B , the second-stage power amplifier circuits PA2m, PA2s are realized by, for example, emitter-grounded npn heterojunction bipolar transistors (HBT) Q2m, Q2s. The heterojunction bipolar transistor Q2m has a larger transistor size than the heterojunction bipolar transistor Q2s, and has, for example, about 4 times the emitter size of the heterojunction bipolar transistor Q2s, although its emitter size is not particularly limited thereto. The control chip CTLIC supplies the bias current IBS2m to the base of the heterojunction bipolar transistor Q2m and supplies the bias current IBS2s to the base of the heterojunction bipolar transistor Q2s. According to the mode setting signal Vmode shown in Figure 1, the control chip CTLIC can choose whether to provide bias current IBS2m, IBS2s.

As described above, a compound semiconductor process including, for example, gallium arsenide (GaAs) and silicide (SiGe) is applied to the high-frequency power amplifier chip HPAIC, and a silicon (Si) process (CMOS process) is applied to the control chip CTLIC. Therefore, the high-frequency power amplifier chip HPAIC and the control chip CTLIC are prepared as separate semiconductor chips. However, if the power amplifier circuit can be realized by using, for example, LDMOS whose characteristics are inferior to those of HBT, the high-frequency power amplifier chip HPAIC and the control chip CTLIC can be integrated into a single semiconductor chip. In addition, the capacitor C3 can be formed in the output matching circuit MNT_O or the control chip CTLIC. However, when the capacitor C3 is formed in the high-frequency power amplifier chip HPAIC, it turns out to be advantageous because it reduces the required area and realizes a high Q value. The NMOS transistor MNsw can be configured as a bipolar transistor within the high-frequency power amplifier chip HPAIC. However, when the NMOS transistor MNsw is constructed as a MOS transistor within the control chip CTLIC, it can, for example, reduce the required area and power consumption compared to the case of using bipolar transistors.

Referring to FIG. 2A, the output matching circuit MNT_O includes transmission lines LNmn, LNsub and capacitors C4, C5. One ends of the capacitors C4 and C5 are coupled together. The other end of the capacitor C4 is coupled to the ground power supply voltage GND, and the other end of the capacitor C5 is coupled to the external terminal (output power signal Pout). One end of the transmission lines LNmn, LNsub is commonly coupled to the output node of the second-stage power amplifier circuit PA2m. The other end of the transmission line LNmn is coupled to one end of the capacitors C4 and C5. The other end of the transmission line LNsub is coupled to the output node of the second-stage power amplifier circuit PA2s (one end of the capacitor C3). In a certain area, the transmission lines LNmn, LNsub are arranged close to each other and in parallel to induce magnetic coupling (MC). Also, in this magnetic coupling region, the transmission lines LNmn, Lnsub are arranged so that the transmission line LNmn originating from the output node side of the second-stage power amplifier circuit PA2m is in the same position as the transmission line originating from the output node side of the second-stage power amplifier circuit PA2s. LNsub extends in the same direction. The configuration of this magnetic coupling portion is different from the above-described example configuration shown in FIGS. 11A to 11C .

3A and 3B show the principle of operation of the high-frequency power amplifier device shown in FIG. 2A. FIG. 3A is a diagram for explaining an example of operations performed when subpaths are used. FIG. 3B is a diagram for explaining an example of operations performed when the main path is used. First, when the power (Pout) of the external terminal is to be set at a low to middle output level, an operation is performed by using the sub-path as shown in FIG. 3A. When the sub-path is used, the above-mentioned control chip CTLIC performs control to enable the second-stage power amplifier circuit PA2s, disable the second-stage power amplifier circuit PA2m, and turn on the NMOS transistor MNsw. In this instance, the signal output from the second-stage power amplifier circuit PA2s is transmitted to one end of the transmission line LNmn (the output node side of the second-stage power amplifier circuit PA2m) through the transmission line LNsub, and then transferred to the outside through the transmission line LNmn Terminal (Pout). In this case, the NMOS transistor MNsw is turned on so that the output impedance of the second-stage power amplifier circuit PA2s (for example, tens of ohms ) into a predetermined impedance (for example, 50 ohms).

When the sub-path is used as described above, the signal (current) flowing in the transmission line LNsub and the signal (current) flowing in the transmission line LNmn coincide in the transmission direction so that the current flows in the same direction. Magnetic coupling then occurs between the magnetic flux generated by the transmission line LNmn and the magnetic flux generated by the transmission line LNsub to strengthen each magnetic flux. As a result, the total magnetic flux increase. When the current flowing in the transmission line LNsub(LNmn) is I, the inductive reactance L of the transmission line LNsub is equal to Therefore, due to the magnetic flux caused by the above-mentioned magnetic coupling The increase of is equivalent to increasing the inductive reactance L. Therefore, when sub-paths are used, magnetic coupling can be utilized thereby appearing to increase the length of the transmission line LNsub equivalently.

Next, when the power of the external terminal (Pout) is to be set at a high output level, an operation is performed by utilizing the main path as shown in FIG. 3B. When the main path is used, the control chip CTLIC described above performs control to enable the second-stage power amplifier circuit PA2m, disable the second-stage power amplifier circuit PA2s, and turn off the NMOS transistor MNsw. In this example, the signal output from the second-stage power amplifier circuit PA2m is transmitted to the external terminal (Pout), and the output signal of the second-stage power amplifier circuit PA2m is transmitted through the matching circuit formed by the transmission line LNmn, the capacitor C4, and the capacitor C5. The output impedance (for example, several ohms) is converted into a predetermined impedance (for example, 50 ohms). In this case, the NMOS transistor MNsw is turned off. Actually, however, there is an off-capacitance of the NMOS transistor MNsw as described above. Therefore, there may be a leakage path through the transmission line LNsub, the capacitor C3, and the NMOS transistor MNsw. However, when the main path is used as described above, transmitting the signal (current) flowing in the transmission line LNmn and the signal (leakage current) flowing in the transmission line LNsub in opposite directions causes the current to flow in the opposite direction. Magnetic coupling then occurs between the magnetic flux generated by the transmission line LNmn and the magnetic flux generated by the transmission line LNsub such that each magnetic flux is weakened. As a result, contrary to the case shown in FIG. 3A , the inductance L in the transmission line LNsub is reduced. Therefore, when the main path is used, the magnetic coupling can be utilized so that the length of the transmission line LNsub appears to be reduced equivalently.

Therefore, it appears to be equivalent to increasing the length of the transmission line LNsub when using the sub-path and decreasing the length of the transmission line LNsub when using the main path. This solves the balance problem described above. In other words, when sub-paths are used, the transmission line LNsub appears long to provide sufficient impedance matching. On the other hand, when the main path is used, the transmission line LNsub appears short so that power leakage through the transmission line LNsub can be reduced. On the other hand, for example when there is a certain margin of permissible length of the transmission line LNsub in terms of the characteristics of the main path (that is, when power leakage does not cause practical problems), the transmission line LNsub can be designed as Shorter when using magnetic coupling than when not using magnetic coupling. This reduces the required area.

Figures 4A to 4C show example effects of magnetic coupling during sub-paths using the high-frequency power amplifier device shown in Figures 2A and 2B. Figure 4A is a supplemental schematic illustrating the preconditions for such magnetic coupling. 4B and 4C are diagrams for explaining verification results. First, the effect of magnetic coupling is verified by comparing three different cases. More precisely, for the case where the signal in the line is transmitted in the same direction as shown in FIG. 4A (when the operation shown in FIG. 3A is performed), the signal in the line is transmitted in the opposite direction as shown in FIG. 4A The case of the signal (when the input and output destinations of the transmission line LNsub shown in FIG. 3A are interchanged) and the case of not transmitting the signal in the line in parallel (when not when using magnetic coupling) for comparison.

As a result, as shown in FIG. 4B , it has been found that the power added efficiency ( PAE) is higher. Referring to FIG. 4B , the verification was performed at a frequency of 1950 MHz and a power supply voltage Vcc2 of 3.4V. When the signals in the lines are transmitted in the same direction, the range of available output levels (Pout) is wider than when the signals in the lines are not transmitted in parallel. Therefore, the second-stage power amplifier circuit PA2s can be used more frequently than the second-stage power amplifier circuit PA2m. This reduces power consumption. Furthermore, as shown in FIG. 4C, when trying to match the output impedance Zsub with respect to the second-stage power amplifier circuit PA2s, impedance matching with respect to the target impedance is achieved when the signal in the line is transmitted in the same direction, because for the transmission line LNsub Ample amount of clockwise rotation is obtained. However, when the signal in the line is transmitted in the opposite direction, it is difficult to achieve impedance matching with respect to the target impedance because the amount of rotation is insufficient. These findings indicate that an effect of magnetic coupling occurs.

5A and 5B show various characteristics exhibited during use of the high-frequency power amplifier device shown in FIGS. 2A and 2B. FIG. 5A is a diagram for explaining characteristics of power-added efficiency (PAE). FIG. 5B is a diagram for explaining the characteristics of adjacent channel leakage ratio (ACLR). Referring to FIGS. 5A and 5B , the case of using the example configuration shown in FIGS. 2A and 2B is compared with the case in which the example configuration shown in FIGS. 11A to 11C is used while appropriately designing the length of the transmission line LNsub to be at The same behavior exists when using the main path. As shown in Figure 5A, if the same PAE exists during the use of the main path, the PAE that exists during the use of the sub-path will be different when using the example configuration shown in Figures 2A and 2B (when the signals in the line are transmitted in the same direction) Higher than when using the example configuration shown in FIGS. 11A to 11C (when the signals in the lines are not transmitted in parallel). This reduces the call current and reduces the power consumption of the high-frequency power amplifier device. Furthermore, as shown in FIG. 5B , FIGS. 2A and 2B and FIGS. 11A to 11C are not significantly different in adjacent channel leakage ratio (ACLR) representing the amount of distortion. The output level (Pout) for switching between the sub path and the main path is set as high as possible within the range within which the amount of distortion shown in FIG. 5B meets a predetermined standard and the PAE of the sub path Stay unsaturated.

As described above, the call current can typically be reduced using the high-frequency power amplifier device according to the first embodiment. The first embodiment has been described on the assumption that the high-frequency power amplifier device of W-CDMA is used because of special needs such as reduction of call current. However, it is obvious that the first embodiment is also applicable to high-frequency power amplifier devices such as GSM (Global System for Mobile Communications) and DCS (Digital Cellular System). Furthermore, the first embodiment has been described on the assumption that a single-band W-CDMA high-frequency power amplifier module is used. However, instead of making the high-frequency power amplifier chip HPAIC shown in FIG. HPAMD includes additional high-frequency power amplifier chip HPAIC to provide multi-band support.

second embodiment

A second embodiment of the present invention will now be described with reference to an exemplary mounting structure based on the configuration example shown in FIGS. 2A and 2B describing the first embodiment. 6 is a schematic diagram related to a high-frequency power amplifier device according to a second embodiment and illustrating an example mounting structure based on the configuration example shown in FIGS. 2A and 2B . The high-frequency power amplifier device shown in FIG. 6 is obtained by giving a specific form to junctions between the high-frequency power amplifier chip HPAIC and the transmission lines LNmn, LNsub in the configuration example shown in FIGS. 2A and 2B . The configuration of the circuit of the high-frequency power amplifier device shown in FIG. 6 will not be described in detail because it is the same as that shown in FIGS. 2A and 2B.

In the high-frequency power amplifier chip HPAIC, the output of the power amplifier circuit PA2m is coupled to the external terminal (electrode pad) P2m, and the output of the power amplifier circuit PA2s is coupled to the external terminal (electrode pad) P2s. A bonding area BAR1 is formed at one end of the transmission line LNmn. One end of the transmission line LNsub is coupled to the bonding area BAR1. A land BAR2 is formed at the other end of the transmission line LNsub. The external terminal P2m is coupled to the bonding region BAR1 through a plurality of bonding wires BW1. The external terminal P2s is coupled to the bonding region BAR2 through the bonding wire BW2. The external terminals P2m, P2s are arranged close to each other while the bonding area BAR1 is close to the bonding area BAR2 so that magnetic coupling occurs between the bonding wire BW1 and the bonding wire BW2.

When the main path is used in the above-mentioned configuration (when the power amplifier circuit PA2m is operating), not only magnetic coupling occurs between the transmission lines LNmn, LNsub as described above, but also between the bonding wire BW1 and the bonding wire BW1 in the same direction as the above-mentioned magnetic coupling. Magnetic coupling also occurs between wires BW2. In other words, when the main path is used, magnetic coupling occurs between the bonding wire BW1 and the bonding wire BW2 in such a manner that the magnetic force on both sides is weakened. Therefore, the difference between the apparent inductance on the transmission line LNsub side during use of the main path and the apparent inductance on the transmission line LNsub side during use of the sub-path (during operation of the power amplifier circuit PA2s) is larger than when using the inductance shown in FIGS. 2A and 2B. When constructing an example of . This further addresses the balancing issues described above.

third embodiment

A third embodiment of the present invention will now be described in conjunction with a modification of the mounting structure shown in FIG. 6 used to describe the second embodiment. 7 is a schematic diagram illustrating an example mounting structure based on the configuration example shown in FIGS. 2A and 2B , relating to a high-frequency power amplifier device according to a third embodiment of the present invention. As in the case of the high-frequency power amplifier device shown in FIG. 6, the high-frequency power amplifier device shown in FIG. Obtained by giving a specific form. The circuit configuration of the high-frequency power amplifier device shown in FIG. 7 will not be described in detail because it is the same as that shown in FIGS. 2A and 2B.

In the high-frequency power amplifier chip HPAIC, the output of the power amplifier circuit PA2m is coupled to the external terminal (electrode pad) P2m, and the output of the power amplifier circuit PA2s is coupled to the external terminal (electrode pad) P2s. A bonding area BAR1 is formed at one end of the transmission line LNmn. Unlike the high-frequency power amplifier device shown in FIG. 6, a land BAR3 is formed at one end of the transmission line LNsub, and a land BAR2 is formed at the other end. The external terminal P2m is coupled with the bonding region BAR1 through the bonding wire BW1 and further coupled with the bonding region BAR3 through the bonding wire BW3. The external terminal P2s is coupled to the bonding region BAR2 through the bonding wire BW2. The third embodiment is characterized in that one end of the transmission line LNsub (bonding area BAR3 ) is coupled to the external terminal P2m through the bonding wire BW3 instead of the bonding area BAR1 as shown in FIG. 6 . In addition, sufficient space is provided between the bonding wires BW3 and BW2 to avoid magnetic coupling.

FIG. 8 is a schematic diagram for explaining in detail an example of a wiring circuit board layout using the mounting structure shown in FIG. 7 . Referring to FIG. 8, a high frequency power amplifier chip HPAIC and a control chip CTLIC are mounted on a wiring circuit board (PCB) forming a high frequency power amplifier device HPAMD. Furthermore, transmission lines LNmn, LNsub are formed on the PCB. The PCB has a multilayer structure including, for example, ceramic dielectric layers and copper (Cu) wiring layers. The transmission lines LNmn, LNsub are formed by using a wiring layer. The wiring width of the transmission line LNmn is larger than that of the transmission line LNsub. The transmission lines LNmn, LNsub are close to and parallel to each other in a certain area. The length of the parallel portion is 1 mm or less. In the parallel section, the space between the transmission lines LNmn, LNsub is about 0.1 mm. The high frequency power amplifier device HPAMD is downsized such that its length on each side is a few millimeters. In this case, it is difficult to use λ/4 stub wiring and so on, as mentioned earlier.

As described above, when one end (bonding region BAR3) of the transmission line LNsub is coupled with the electrode pad P2m through the bonding wire BW3 during use of the configuration examples shown in FIGS. 7 and 8, the power loss during use of the main path can be made low. When the coupling destination is the bonding area BAR1. In other words, the electrode pad P2m side has lower impedance than the bonding area BAR1 side because the output impedance of the power amplifier circuit PA2m is, for example, several ohms and is converted to an impedance of, for example, 50 ohms through the transmission line LNmn or the like. When using the main path, the LNsub side of the transmission line is considered a high impedance circuit. However, when the high-impedance circuit is coupled with the lower-impedance portion, the amount of power leakage to the high-impedance circuit side is small due to the impedance ratio. Therefore, when one end of the transmission line LNsub is coupled to the electrode pad P2m side, the power consumption of the high-frequency power amplifier device can be reduced while the above-mentioned magnetic coupling effect is produced between the transmission lines LNmn, LNsub.

The configuration examples shown in FIGS. 7 and 8 do not use the magnetic coupling between the bonding wires BW1 , BW2 shown in FIG. 6 . In some cases, however, an alternative configuration may be employed in which the bond wires BW1 , BW2 are arranged close to each other in order to additionally use the magnetic coupling between the bond wires BW1 , BW2 . However, in this case, unlike the case shown in FIG. 6, for example, the routing of the transmission line LNsub must be properly determined. Therefore, it is preferable to use the configuration examples shown in FIGS. 7 and 8 from the viewpoints of, for example, ease of downsizing and impedance matching.

Fourth embodiment

In the example configuration described in connection with the previous embodiments, two different modes of operation (low to medium output level and high output level) are available by selection of the second stage power amplifier circuits PA2m, PA2s. These example configurations can be extended to example configurations where three or more different modes of operation (eg, low output level, medium output level, and high output level) are available. A fourth embodiment of the present invention will now be described in connection with an example configuration in which a high-frequency power amplifier device provides three different modes of operation. 9 is a circuit diagram relating to a high-frequency power amplifier device according to a fourth embodiment of the present invention and illustrating in detail an example configuration of relevant parts including the second-stage power amplifier circuits PA2m, PA2s shown in FIG. 1 .

As shown in FIG. 9 , each of the second-stage power amplifier circuits PA2m, PA2s generally includes a plurality of unit transistors whose emitters, bases, and collectors are commonly coupled. Each unit transistor is called a finger or the like. It can therefore be said that each of these power amplifier circuits has a multi-finger structure and the like. In order to support three different operation modes, the power amplifier circuit PA2m or PA2s divides the multi-finger structure into two groups so that the base bias voltage can be independently supplied to each group.

More specifically, the power amplifier circuit PA2m or power amplifier circuit PA2s includes 2×n heterojunction bipolar transistors (unit transistors) Q2a[1]-Q2a[n], Q2b[1] whose emitters and collectors are commonly coupled -Q2b[n]. The bases are commonly coupled with transistors Q2a[1]-Q2a[n]. The bias current IBS2a is supplied to these transistors through the control chip CTLIC shown in FIG. 1 . Similarly, the bases are commonly coupled with transistors Q2b[1]-Q2b[n]. The bias current IBS2b is supplied to these transistors through the control chip CTLIC shown in FIG. 1 . Whether to supply the bias currents IBS2a, IBS2b is independently controlled according to the mode setting signal Vmode'. The mode setting signal Vmode' is provided with three-valued information, for example, by adding 1 bit to the aforementioned mode setting signal Vmode (1 bit) having two pieces of information.

For example, if the size ratio (ratio of the number of fingers) between the power amplifier circuit PA2m and the power amplifier circuit PA2s is 4:1, PA2m can be realized when the power amplifier circuit PA2m is divided into two groups (two groups are activated) : PA2m (one group is activated): PA2s size ratio = 4:2:1. Dimension values of 4, 2 and 1 are considered to correspond to high output level, medium output level and low output level modes of operation, respectively. Selective use of these dimensions can reduce the talk current and reduce the power consumption of the high-frequency power amplifier device while maintaining the above-mentioned effect of the magnetic coupling between the transmission lines LNmn, LNsub. This also prevents the high-frequency power amplifier device from being increased in size. Meanwhile, if a scheme for realizing three different operation modes by adding another power amplifier circuit is taken as a comparative example, the high-frequency power amplifier device cannot be downsized due to, for example, an increase in the number of terminals and lines on a wiring circuit board. In addition, an appropriate method for achieving the above-mentioned magnetic coupling needs to be carefully devised. Although the fourth embodiment has been described in connection with an example configuration providing three different operation modes, four different operation modes can also be realized by dividing the power amplifier circuit PA2s into two groups as well.

Whilst the invention contemplated by the inventors has been described in terms of preferred embodiments, it should be understood that the invention is not limited to those preferred embodiments but may be extended while still falling within the scope of the appended claims various modifications.

A high frequency power amplifier device according to an embodiment of the present invention is useful especially when it is applied to a power transmitter of a W-CDMA or TDS-CDMA mobile phone. However, it is also applicable to GSM, DCS, LTE (Long Term Evolution) and other mobile phones based on various standards. Furthermore, it is applicable not only to mobile phones but also widely to various wireless devices that should preferably provide multiple output power modes and have low power consumption due to, for example, their battery driving capabilities.

Claims (18)

1. a high-frequency power amplifier device, including:

First power amplifier circuit, described first power amplifier circuit is to the first input signal It is amplified；

Second power amplifier circuit, described second power amplifier circuit is to described first input Signal is amplified；

First transmission line, described first transmission line at one end with described first power amplifier circuit Output node be coupled；

First electric capacity, described first electric capacity is coupled with the other end of described first transmission line；

Second transmission line, described second transmission line at one end with described first power amplifier circuit Output node be coupled and at the output joint of the other end and described second power amplifier circuit Point is coupled；

Second electric capacity and transistor switch, described second electric capacity and transistor switch are by arranged in series Between the output node and earthing power supply voltage of described second power amplifier circuit；And

Control circuit, described control circuit activates described first power according to mode setting signal puts Big device circuit or described second power amplifier circuit, when described first power amplifier circuit quilt Described transistor switch is driven to make it disconnect during activation and when described second power amplifier circuit Described transistor switch is driven to turn it on when being activated,

Wherein said first and second transmission lines include magnetic coupling region, in described magnetic coupling region In, described first and second transmission line layouts close to each other to cause magnetic coupling, and

Wherein, in described magnetic coupling region, arrange that described first and second transmission lines make source From described first transmission line of the output node side of described first power amplifier circuit be derived from The direction that described second transmission line of the output node side of described second power amplifier circuit is identical Upper extension.

High-frequency power amplifier device the most according to claim 1,

Wherein said first power amplifier circuit includes being amplified described first input signal The first transistor, and

Wherein said second power amplifier circuit includes transistor seconds, described transistor seconds Described first input signal is amplified and size is less than described the first transistor.

High-frequency power amplifier device the most according to claim 2,

Wherein said first and second transistors are bipolar transistors, and

Wherein said transistor switch is MIS transistor.

High-frequency power amplifier device the most according to claim 3,

Wherein formed on the first semiconductor chip described first and second power amplifier circuits and Described second electric capacity, and

On the second semiconductor chip, wherein form described transistor switch and described control circuit.

High-frequency power amplifier device the most according to claim 2,

Wherein said first power amplifier circuit includes and described the first transistor parallel coupled Third transistor, and described second power amplifier circuit includes with described transistor seconds also 4th transistor of connection coupling, and

Wherein said control circuit further according to described mode setting signal to the described 3rd and Activation and the deexcitation of four transistors are independently controlled.

6. a high-frequency power amplifier device, including:

First transmission line, described first transmission line is disposed between primary nodal point and secondary nodal point；

Second transmission line, described second transmission line is disposed between the 3rd node and fourth node；

First power amplifier circuit, described first power amplifier circuit is to the first input signal It is amplified and the signal of amplification is exported described primary nodal point；

Second power amplifier circuit, described second power amplifier circuit is to described first input Signal is amplified and the signal of amplification exports described 3rd node；

Transistor switch, described transistor switch be controlled as conducting time by impedance matching element It is coupled with described 3rd node, and discharges described 3rd node when being controlled as and disconnecting； And

Control circuit, described control circuit activates described first power according to mode setting signal puts Big device circuit or described second power amplifier circuit, when described first power amplifier circuit quilt Described transistor switch is driven to make it disconnect during activation and when described second power amplifier circuit Described transistor switch is driven to turn it on when being activated,

Wherein said first and second transmission lines are arranged to close to each other to cause magnetic coupling.

High-frequency power amplifier device the most according to claim 6,

Wherein said first power amplifier circuit includes being amplified described first input signal The first transistor, and

Wherein said second power amplifier circuit includes transistor seconds, described transistor seconds Described first input signal is amplified and size is less than described the first transistor.

High-frequency power amplifier device the most according to claim 7,

Wherein said impedance matching element is capacity cell, and

Wherein said capacity cell and described transistor switch be coupled in series in described 3rd node with Between earthing power supply voltage.

High-frequency power amplifier device the most according to claim 8,

Wherein formed on the first semiconductor chip described first and second power amplifier circuits and Described impedance matching element, and

On the second semiconductor chip, wherein form described transistor switch and described control circuit.

High-frequency power amplifier device the most according to claim 7,

Wherein said first and second transistors are bipolar transistors, and

Wherein said transistor switch is MIS transistor.

11. high-frequency power amplifier devices according to claim 7,

Wherein said first power amplifier circuit includes and described the first transistor parallel coupled Third transistor, and described second power amplifier circuit includes with described transistor seconds also 4th transistor of connection coupling, and

Wherein said control circuit further according to described mode setting signal to the described 3rd and Activation and the deexcitation of four transistors are independently controlled.

12. 1 kinds of high-frequency power amplifier devices, including:

Wiring circuit；

The one or more semiconductor chips being arranged on described wiring circuit；

First transmission line, described first transmission line is formed by the wiring layer on described wiring circuit And it is disposed between primary nodal point and secondary nodal point；

Second transmission line, described second transmission line is formed by the wiring layer on described wiring circuit And it is disposed between the 3rd node and fourth node；And

First closing line and the second closing line,

Each of wherein said one or more semiconductor chip includes:

First power amplifier circuit, described first power amplifier circuit is to the first input signal It is amplified and the signal of amplification is exported to the first pad；

Second power amplifier circuit, described second power amplifier circuit is to described first input Signal is amplified and the signal of amplification is exported to the second pad；

Transistor switch, described transistor switch be controlled as conducting time by impedance matching element It is coupled with described second pad, and discharges described second pad when being controlled as and disconnecting； And

Control circuit, described control circuit activates described first power according to mode setting signal puts Big device circuit or described second power amplifier circuit, when described first power amplifier circuit quilt Described transistor switch is driven to make it disconnect during activation and when described second power amplifier circuit Described transistor switch is driven to turn it on when being activated,

Described first pad is coupled by wherein said first closing line with described primary nodal point,

Described second pad is coupled by wherein said second closing line with described 3rd node,

Wherein said fourth node is coupled with described first pad or described primary nodal point, and

Wherein said first and second transmission lines include magnetic coupling region, in described magnetic coupling region In, described first and second transmission line layouts close to each other to cause magnetic coupling, and described One and second transmission line be disposed in described magnetic coupling region and make to be derived from described first power and put Described first transmission line of the output node side of big device circuit be derived from described second power amplification The side that described second transmission line of the output node side of device circuit is identical upwardly extends.

13. high-frequency power amplifier devices according to claim 12,

Wherein said first power amplifier circuit includes being amplified described first input signal The first transistor, and

Wherein said second power amplifier circuit includes transistor seconds, described transistor seconds Described first input signal is amplified and size is less than described the first transistor.

14. high-frequency power amplifier devices according to claim 13, wherein said first Closing line and described second closing line are arranged close to each other to cause magnetic coupling.

15. high-frequency power amplifier devices according to claim 13, farther include:

3rd closing line,

Described first pad is coupled by wherein said 3rd closing line with described fourth node.

16. high-frequency power amplifier devices according to claim 13,

Wherein said impedance matching element is capacity cell, and

Wherein said capacity cell and described transistor switch be coupled in series in described second pad with Between earthing power supply voltage.

17. high-frequency power amplifier devices according to claim 16,

Wherein formed on the first semiconductor chip described first and second power amplifier circuits with And described capacity cell,

On the second semiconductor chip, wherein form described transistor switch and described control circuit,

Wherein said first and second transistors are bipolar transistors, and

Wherein said transistor switch is MIS transistor.

18. high-frequency power amplifier devices according to claim 13,

Wherein said first power amplifier circuit includes and described the first transistor parallel coupled Third transistor, and described second power amplifier circuit includes with described transistor seconds also 4th transistor of connection coupling, and

Wherein said control circuit further according to described mode setting signal to the described 3rd and Activation and the deexcitation of four transistors are independently controlled.