CN102570784B - Power on/reset circuit and control digital circuit on/reset state method - Google Patents

Abstract

The invention discloses a power supply starting/resetting circuit and a method for controlling the starting/resetting state of a digital circuit. The power on/reset circuit comprises a voltage following module, a reverse amplification module and at least one first transistor which is connected in series in a series-overlapping mode. The voltage following module generates a first analog signal, and the potential of the first analog signal changes according to the potential of the first direct current voltage source. The reverse amplification module is used for reversing the potential logic of the first analog signal to generate a second analog signal, and the first transistor is used for adjusting the second analog signal, so that the potential of the starting/resetting signal controlled by the second analog signal is enough to correctly operate a digital circuit at the rear end.

Description

Power on/reset circuit and control digital circuit on/reset state method

technical field

The present invention discloses a power on/reset circuit and a related method for controlling the on/reset state of a digital circuit, especially a power on/reset comprising at least one transistor connected in series in a stack manner. Circuits and associated methods of controlling the on/reset state of digital circuits.

Background technique

In order to integrate more functions, general integrated circuits are mostly in the form of System-on-a-chip (SOC) and mixed-mode (mixed-mode), basically including digital circuits and analog circuits, and In addition to providing functions such as control, logic operations, and data storage, the digital circuit part also needs to include the setting of the initial condition of the integrated circuit, and the setting of the initial value of the initial condition requires a so-called open/reset signal ( Power on/Reset Signal).

Please refer to FIG. 1 and FIG. 2 , which are schematic diagrams of two integrated circuits disclosed in the prior art. The integrated circuit 100 shown in FIG. 1 includes a power on/reset circuit (Power On/Reset Circuit) 110, a voltage regulator (Regulator) 120, a power on/reset pulse generator 130, and a digital circuit 140. The power on/reset circuit 110 and the voltage regulator 120 are powered by a DC voltage source VDD. The power-on/reset circuit 110 is used to generate a start-up/reset signal to timely determine the timing of turning on or resetting the digital circuit 140; the power-on/reset pulse generator 130 will generate The start/reset signal and the power provided by the voltage regulator 120 generate a reset pulse, so that the digital circuit 140 can be started or reset according to the enable time corresponding to the start/reset signal. Similarly, the integrated circuit 200 shown in FIG. 2 includes a power-on/reset circuit 110 , a voltage regulator 120 , a power-on/reset pulse generator 230 , and a digital circuit 140 . The power on/reset pulse generator 230 is also used to generate the reset pulse according to the power provided by the voltage regulator 120 and the on/reset signal generated by the power on/reset circuit 110 to determine the digital circuit 140 is turned on or is reset. A general integrated circuit realizes the reset of the digital circuit in the manner shown in FIG. 1 or FIG. 2 .

Ideally, the voltage source VDD supplied to the integrated circuits 100 and 200 is only turned on once, and then continues to operate. However, in actual use or testing, non-ideal situations may occur, so that the power is turned on and off repeatedly. For example: the voltage source provided to the integrated circuit is turned on from the initial state, the potential of the voltage source rises from 0 volts to 3 volts, and then the voltage source is turned off, and the potential of the voltage source drops from 3 volts to 0.9 volts. When the voltage source is just turned on again, the potential of the voltage source rises from 0.9 volts to 3 volts, such an undesirable change.

Please refer to FIG. 3 , which is a schematic diagram of a power on/reset circuit 250 commonly used in the prior art for generating the above-mentioned on/reset signal. As shown in Figure 3, the power on/reset circuit 250 includes a voltage following module 310, a P-type metal oxide semiconductor transistor QS1, an N-type metal oxide semiconductor transistor QS2, and an inverter INV, wherein the voltage following module 310 uses a DC voltage Source VCC power supply. The potential of the voltage V1 generated by the voltage tracking module 310 follows the potential variation of the DC voltage source VCC. The P-type MOS transistor QS1 and the N-type MOS transistor QS2 implement the function of an inverter for the voltage V1, so that the potential of the generated voltage V2 is opposite to that of the voltage V1. Finally, the voltage V2 is converted into the start/reset signal shown in FIG. 3 through the operation of the inverter INV. For example, in the power-on/reset circuit 250, the potential of the voltage source VCC rises from 0 volts to 3 volts, and the potential of the voltage V1 will follow the rise of the voltage source VCC. When the voltage level of the voltage V1 has not risen enough to trigger the transistor In the case of an inverter composed of QS 1 and transistor QS2, the potential change of the voltage V2 is equal to the potential change of the voltage source VCC, so that the output of the inverter INV coupled thereto maintains a low voltage level of 0V at this time, which is also That is, the start/reset signal outputs a low voltage level at this time to reset the digital circuit at the back end. Then, when the voltage V1 rises enough to trigger the inverter composed of the transistor QS1 and the transistor QS2, the voltage V2 turns to a low voltage level, and the inverter INV coupled thereafter outputs a high voltage level of 3 volts to The reset of the digital circuit by the power on/reset circuit 250 is ended.

But when the potential of the voltage source VCC then drops from 3 volts to 0.9 volts and then rises to 3 volts as described above, the power on/reset circuit 250 of the prior art will no longer change the digital circuit at the back end. However, the lowest potential 0.9 volts of the voltage source VCC during this potential change process is already lower than the lowest voltage level for normal operation for general digital circuits, so that the recorded in the digital circuit The data enters into an unknown status (Unknown Status), which eventually causes the digital circuit to fail to continue normal operation. This is because the voltage V1 in the power on/reset circuit 250 follows the voltage level changed by the voltage source VCC, which is not enough to make the digital circuit continue to operate normally. The inverter formed by the transistor QS1 and the transistor QS2 triggers the transition again.

Contents of the invention

The purpose of the present invention is to provide a power-on circuit and a related method for controlling the on/reset state of a digital circuit, so that the potential of the on/reset signal can indeed turn on the digital circuit at the back end, and solve the problems in the known technology. Re-opening the digital circuit problem.

Based on the above purpose, the present invention discloses a power on/reset circuit. The power on/reset circuit includes a voltage following module, an inverse amplification module, and at least one first transistor connected in series in a cascaded manner. The voltage tracking module is coupled to a first DC voltage source. The voltage tracking module generates a first analog signal. The potential level change of the first analog signal follows the potential level change of the first DC voltage source. The reverse amplification module is used to receive the first analog signal and generate a second analog signal. The potential logic of the second analog signal is opposite to the potential logic of the first analog signal. The power on/reset circuit controls the on/reset state of the digital circuit according to the second analog signal. The inverse amplification module adjusts the second analog signal by cascading transistors.

The reverse amplification module includes a first N-type metal-oxide-semiconductor transistor and a first P-type metal-oxide-semiconductor transistor. The gate of the first NMOS transistor is coupled to an output end of the voltage tracking module to receive the first analog signal. The gate of the first PMOS transistor is coupled to the gate of the first NMOS transistor. The source of the first P-type metal oxide semiconductor transistor is coupled to a second DC voltage source. And the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor and outputs the second analog signal. The first transistor of the at least one first transistor coupled to the reverse amplification module is coupled to the source of the first NMOS transistor.

The potential of the second DC voltage source is higher than the potential of the first DC voltage source.

The power on/reset circuit further includes at least one second transistor connected in cascade, wherein one second transistor is coupled to the second DC voltage source, and another second transistor is coupled to the first A source of a P-type metal oxide semiconductor transistor.

The at least one first transistor is an N-type metal-oxide-semiconductor transistor, and the at least one second transistor is a P-type metal-oxide-semiconductor transistor.

The at least one first transistor is a P-type metal-oxide-semiconductor transistor, and the at least one second transistor is an N-type metal-oxide-semiconductor transistor.

The at least one first transistor is an npn bipolar junction transistor, and the at least one second transistor is a pnp bipolar junction transistor.

The at least one first transistor is a pnp bipolar junction transistor, and the at least one second transistor is an npn bipolar junction transistor.

The reverse amplification module includes a first N-type metal-oxide-semiconductor transistor and a first P-type metal-oxide-semiconductor transistor. The gate of the first NMOS transistor is coupled to an output end of the voltage tracking module to receive the first analog signal. The gate of the first P-type MOS transistor is coupled to the gate of the first N-type MOS transistor, and the source of the first P-type MOS transistor is coupled to a second DC A voltage source, and the drain of the first PMOS transistor is coupled to the drain of the first NMOS transistor and outputs the second analog signal. The first transistor of the at least one first transistor coupled to the reverse amplification module is coupled to the source of the first P-type metal-oxide-semiconductor transistor.

The potential of the second DC voltage source is higher than the potential of the first DC voltage source.

The power on/reset circuit further includes at least one second transistor connected in series in cascade, wherein one second transistor is coupled to the source of the first NMOS transistor.

The at least one first transistor is an N-type metal-oxide-semiconductor transistor, and the at least one second transistor is a P-type metal-oxide-semiconductor transistor.

The at least one first transistor is a P-type metal-oxide-semiconductor transistor, and the at least one second transistor is an N-type metal-oxide-semiconductor transistor.

The at least one first transistor is an npn bipolar junction transistor, and the at least one second transistor is a pnp bipolar junction transistor.

The at least one first transistor is a pnp bipolar junction transistor, and the at least one second transistor is an npn bipolar junction transistor.

The voltage following module includes a first P-type metal oxide semiconductor transistor, a second P-type metal oxide semiconductor transistor, a third P-type metal oxide semiconductor transistor, a first N-type metal oxide semiconductor transistor, a second N N-type MOS transistor, a third N-type MOS transistor, a fourth N-type MOS transistor, and a fifth N-type MOS transistor. The source of the first PMOS transistor is coupled to the first DC voltage source. The source of the second PMOS transistor is coupled to the drain and gate of the first PMOS transistor. The base of the second PMOS transistor is coupled to the base of the first PMOS transistor. The source of the third PMOS transistor is coupled to the source of the first PMOS transistor. The gate of the third PMOS transistor is coupled to the gate of the first PMOS transistor. The drain of the third PMOS transistor is coupled to the gate of the second PMOS transistor. The drain of the first NMOS transistor is coupled to the drain of the third PMOS transistor and the gate of the second PMOS transistor. The drain of the second NMOS transistor is coupled to the source of the first NMOS transistor and the gate of the second NMOS transistor, and the second NMOS transistor The source of the type metal oxide semiconductor transistor is grounded. The source of the third NMOS transistor is grounded, the gate of the third NMOS transistor is coupled to the gate of the second NMOS transistor, and the third The drain of the NMOS transistor is coupled to the gate of the first NMOS transistor. The drain of the fourth P-type MOS transistor is coupled to the drain of the third N-type MOS transistor, and the gate of the fourth P-type MOS transistor is coupled to the first Gates of two N-type metal oxide semiconductor transistors. The drain of the fifth PMOS transistor is coupled to the source of the fourth PMOS transistor, and the gate of the fifth PMOS transistor is coupled to the fourth PMOS transistor. The gate of the P-type MOS transistor, and the source of the fifth P-type MOS transistor is coupled to the source of the first P-type MOS transistor.

The power on/reset circuit further includes a current supplier and an inverting logic module. The current supplier is coupled to the first DC voltage source and used to generate a current. The inversion logic module is coupled to the inversion amplification module to receive the second analog signal, and is coupled to the current supplier to be driven by the current. The current supplier is also used to control the intensity of the current below a critical current intensity. The inversion logic module inverts the potential logic of the second analog signal to generate a turn-on/reset signal, so that the power turn-on/reset circuit controls the digital circuit through the turn-on/reset signal on/reset state.

The current supplier includes a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, and a sixth PMOS transistor. type metal oxide semiconductor transistor. The drain of the second NMOS transistor is coupled to the first DC voltage source and the gate of the second NMOS transistor. The gate of the third NMOS transistor is coupled to the gate of the second NMOS transistor. The gate of the fourth NMOS transistor is coupled to the gate of the third NMOS transistor. The gate and drain of the fifth P-type MOS transistor are coupled to the drain of the third N-type MOS transistor, and the source of the fifth P-type MOS transistor is coupled to The first DC voltage source. The gate of the sixth PMOS transistor is coupled to the gate of the fifth PMOS transistor, and the source of the sixth PMOS transistor is coupled to the first PMOS transistor. a DC voltage source. The inverting logic module includes a seventh P-type metal-oxide-semiconductor transistor and a fifth N-type metal-oxide-semiconductor transistor. The gate of the seventh PMOS transistor is coupled to the CMOS transistor. The source of the seventh PMOS transistor is coupled to the drain of the sixth PMOS transistor. The gate of the fifth NMOS transistor is coupled to the gate of the seventh PMOS transistor. The drain of the fifth NMOS transistor is coupled to the drain of the seventh PMOS transistor. The source of the fifth NMOS transistor is coupled to the drain of the fourth NMOS transistor. The base of the seventh P-type MOS transistor is coupled to the first DC voltage source, and the base of the fifth N-type MOS transistor is coupled to the fourth N-type MOS transistor. base of the transistor.

Based on the above purpose, the present invention discloses a method for controlling the on/reset state of a digital circuit. The method includes making the potential level change of the first analog signal follow the potential level change of the first DC voltage source; inverting the potential logic of the first analog signal, and increasing or decreasing the first voltage level of the inverted potential logic. the potential of the analog signal to generate a second analog signal; adjust the start condition during inversion, and adjust the second analog signal in a cascaded transistor manner; and control a turn-on/reset with the second analog signal signal, and the on/reset state of a digital circuit is controlled by the on/reset signal.

The method further includes inverting the potential logic of the second analog signal to generate the turn-on/reset signal, so as to control the turn-on/reset state of the digital circuit by the turn-on/reset signal.

According to the above technical solution, the scanning device of the present invention has at least the following advantages and beneficial effects: invert the potential logic of the first analog signal to generate the second analog signal, and use the first transistor to adjust the second analog signal so that the second analog signal The potential of the controlled turn-on/reset signal is sufficient to properly operate the back-end digital circuits.

Description of drawings

1 and 2 are schematic diagrams of two integrated circuits disclosed in the prior art.

FIG. 3 is a schematic diagram of a power on/reset circuit commonly used in the prior art.

FIG. 4 is a detailed schematic diagram of the power on/reset circuit shown in FIG. 3 disclosed according to an embodiment of the present invention.

8-13 are schematic diagrams of different embodiments of the reverse amplification module shown in FIG. 4 .

5 is a schematic diagram of shifting the voltage conversion characteristic curve of the inverting amplifying module to the right by including at least one cascaded transistor group included in the inverting amplifying module shown in FIG. 8 .

Figure 6 and Figure 7 show the waveform diagrams of the respective output on/reset signals after inputting a non-ideal voltage source to the power on/reset circuit shown in Figure 3 and the power on/reset circuit shown in Figure 4 respectively .

FIG. 14 is a schematic diagram of the operation method of the power on/reset circuit disclosed in FIGS. 4-13 .

Wherein, the reference signs are explained as follows:

100, 200 integrated circuits

250, 300 Power on/reset circuit

120 voltage regulator

130 Power On/Reset Pulse Generator

140 Digital circuit

230 Power On/Reset Pulse Generator

310 Voltage Follower Module

330 Current Provider

340 Inverting logic module

402, 404, 406, 408 steps

I1, I2, I3 Equivalent current source

C1, C2, C3 capacitors

Q11, Q12, Q13, Q14, Q15, Q16, transistor

Q17, Q18, Q21, Q22, Q31, Q32,

Q33, Q34, Q35, Q36, Q37, Q38,

Q39, Q40, QN1, QNm, QP1, QPm,

Qnpn1, Qnpnm, Qpnp1, Qpnpm,

QS1, QS2

V1, V2 Analog voltage

Vout Open/Reset Signal

TN, TP, Tnpn, Tpnp Transistor group

VDD1, VDD2, VCC DC voltage source

CM, INV Inverter

Detailed ways

Please refer to FIG. 4 , which is a schematic diagram of a power on/reset circuit 300 disclosed in the present invention. As shown in FIG. 4 , the power on/reset circuit 300 includes a voltage tracking module 310 , an inverse amplification module 320 , a current supplier 330 , and an inversion logic module 340 . Please also refer to FIG. 8 , which is a detailed schematic diagram of the reverse amplification module 320 shown in FIG. 4 according to an embodiment of the present invention. As shown in FIG. 8 , the reverse amplification module 320 includes an inverter CM and a transistor group TN.

The voltage following module 310 includes P-type metal-oxide-semiconductor transistors Q12, Q13, Q14, Q17, Q18, N-type metal-oxide-semiconductor transistors Q11, Q15, Q16 and capacitor C1, and is coupled to a DC voltage source VDD1 to form the The equivalent current source I1. The source of the PMOS transistor Q12 is coupled to the DC voltage source VDD1. The source of the PMOS transistor Q13 is coupled to the drain and gate of the PMOS transistor Q12. The base of the PMOS transistor Q13 is coupled to the base of the PMOS transistor Q12. The source of the PMOS transistor Q14 is coupled to the source of the PMOS transistor Q12. The gate of the PMOS transistor Q14 is coupled to the gate of the PMOS transistor Q12. The drain of the PMOS transistor Q14 is coupled to the gate of the PMOS transistor Q13. The drain of the NMOS transistor Q11 is coupled to the drain of the PMOS transistor Q14 and the gate of the PMOS transistor Q13 . The drain of the NMOS transistor Q15 is coupled to the source of the NMOS transistor Q11 and the gate of the NMOS transistor Q15 . The source of the NMOS transistor Q15 is grounded. The source of the NMOS transistor Q16 is grounded. The gate of the NMOS transistor Q16 is coupled to the gate of the NMOS transistor Q15. The drain of the NMOS transistor Q16 is coupled to the gate of the NMOS transistor Q11. The drain of the PMOS transistor Q17 is coupled to the drain of the NMOS transistor Q16. The gate of the PMOS transistor Q17 is coupled to the gate of the NMOS transistor Q15. The drain of the PMOS transistor Q18 is coupled to the source of the PMOS transistor Q17. The gate of the PMOS transistor Q18 is coupled to the gate of the PMOS transistor Q17. The source of the PMOS transistor Q18 is coupled to the source of the PMOS transistor Q12. In the voltage tracking module 310 , the potential variation of the analog signal V1 follows the potential variation of the DC voltage source VDD1 , that is, the potential of the turn-on/reset signal Trig1 follows the potential of the DC voltage source VDD1 as described in the prior art.

The transistor group TN includes at least one N-type metal-oxide-semiconductor transistor QN1 , . . . , QNm connected in series in a stack manner. The transistor QN1 is coupled to the CMOS transistor CM, and the source of the transistor QNm is grounded. The inverter CM includes a P-type MOS transistor Q21 and an N-type MOS transistor Q22. The gate of the NMOS transistor Q22 is coupled to the output end of the voltage tracking module 310 to receive the analog signal V1. The gate of the PMOS transistor Q21 is coupled to the gate of the NMOS transistor Q22. The source of the P-type MOS transistor Q21 is coupled to the DC voltage source VDD2, and the drain of the P-type MOS transistor Q21 is coupled to the drain of the N-type MOS transistor Q22 to output an analog signal V2, wherein the analog The potential polarity of the signal V2 is opposite to that of the analog signal V1, and the analog signal V2 is the basis for the back-end digital circuit to control its on/reset state. The drain of the transistor QN1 is coupled to the source of the NMOS transistor Q22.

The current supplier 330 includes N-type MOS transistors Q31 , Q32 , Q37 and P-type MOS transistors Q33 , Q34 . The drain of the NMOS transistor Q31 is coupled to the DC voltage source VDD1 and the gate of the NMOS transistor Q31 through the equivalent current source I2 generated by the current supplier 330 . The gate of the NMOS transistor Q32 is coupled to the gate of the NMOS transistor Q31. The gate of the NMOS transistor Q37 is coupled to the gate of the NMOS transistor Q32. The gate and the drain of the PMOS transistor Q33 are coupled to the drain of the NMOS transistor Q32. And the source of the PMOS transistor Q33 is coupled to the DC voltage source VDD1. The gate of the PMOS transistor Q34 is coupled to the gate of the PMOS transistor Q33. The source of the PMOS transistor Q34 is coupled to the DC voltage source VDD1. The current provider additionally includes three P-type metal-oxide-semiconductor transistors Q38, Q39, and Q40. The gates of the PMOS transistors Q38 , Q39 , and Q40 are coupled to each other and grounded. The source of the PMOS transistor Q38 is coupled to the DC voltage source VDD1. The drain of the PMOS transistor Q38 is coupled to the source of the PMOS transistor Q39. The drain of the PMOS transistor Q39 is coupled to the source of the PMOS transistor Q40. The drain of the PMOS transistor Q40 is coupled to the drain of the NMOS transistor Q31.

The inverting logic module 340 includes a P-type metal-oxide-semiconductor transistor Q35 and an N-type metal-oxide-semiconductor transistor Q36. The gate of the PMOS transistor Q35 is coupled to the inverter CM. The source of the PMOS transistor Q35 is coupled to the drain of the PMOS transistor Q34. The gate of the NMOS transistor Q36 is coupled to the gate of the PMOS transistor Q35. The drain of the NMOS transistor Q36 is coupled to the drain of the PMOS transistor Q35. The source of the NMOS transistor Q36 is coupled to the drain of the NMOS transistor Q37. The base of the PMOS transistor Q35 is coupled to the DC voltage source VDD1. The base of the NMOS transistor Q36 is coupled to the base of the NMOS transistor Q37. The transistors Q34 and Q35 generate an equivalent capacitance C2 at the output voltage Vout, and the transistors Q36 and Q37 generate an equivalent capacitance C3 at the output voltage Vout. The inverting logic module 340 obtains the required operating current through the transistors Q32, Q33, Q34, and Q37 included in the current supplier 330. The current supplier 330 is also used to control the operating current below the critical current intensity, so as to Generate the turn-on/reset signal Vout located at the node between the capacitors C2 and C3 as shown in Figure 4; the potential logic of the turn-on/reset signal Vout is opposite to that of the second analog signal V2, and is directly used to control the turn-on/reset of the above-mentioned digital circuit The reset state, in other words, the on/reset state of the above-mentioned digital circuit can be controlled indirectly through the second analog signal V2.

In the turn-on/reset circuit 300 shown in FIG. 4 and the reverse amplification module 320 shown in FIG. When the voltage of the node N1 rises enough to turn on the transistor Q11, the current source I1 charges the capacitor C1 through the PMOS transistors Q12 and Q13. Due to the charging of the capacitor C1 , an analog signal V1 is generated at the drain of the transistor Q13 and provided to the inverse amplification module 320 . The potential of the analog signal V1 will directly affect the potential of the analog signal V2 output by the reverse amplification module 320, and the potential of the analog signal V2 will also affect the potential of the start/reset signal Vout used to provide the back-end digital circuit . 5 is a schematic diagram of shifting the voltage conversion characteristic curve of the inverting amplifying module to the right by including at least one cascaded transistor group included in the inverting amplifying module shown in FIG. 8 .

Please refer to FIG. 5 , the transistor group TN included in the inverting amplification module 320 moves the voltage transfer characteristic curve L1 of the inverting amplifying module 320 to the right to L2 by including at least one transistor connected in series. , so that the analog signal V1 is in the process of turning off the DC voltage source VDD1 due to the power supply (for example, the potential drops from 3 volts to 0.9 volts) and then the DC voltage source VDD1 happens to be turned on again (for example, the potential rises from 0.9 volts to 3 volts again), The analog signal V2 can trigger the transition again, that is to say, the inverse amplification module 320 will send the turn-on/reset signal Vout to the digital turn-on/reset pulse generator 230 as shown in FIG. 1-2 via the inversion logic module 340 , and then generate a reset pulse to reset the digital circuit 140 shown in FIGS. 1-2 .

Please refer to FIG. 6 and FIG. 7, wherein the two figures respectively input a non-ideal voltage source VDD1 (the voltage source VDD1 continuously and repeatedly generates on and off conditions, as mentioned in the prior art) to the power on/off shown in FIG. After the reset circuit 250 and the power on/reset circuit 300 shown in FIG. 8 , respectively output the waveform diagrams of the on/reset signal Vout. Observing Figure 6, it can be known that when the potential of the non-ideal voltage source VDD1 drops from 3 volts to 0.9 volts, the turn-on/reset signal Vout also drops from 3 volts to 0.9 volts, and then directly rises from 0.9 volts to 3 volts, so There will be a problem that the turn-on/reset signal cannot effectively turn on the back-end digital circuit as described in the prior art. In contrast to FIG. 7, it can be seen that when the potential of the non-ideal voltage source VDD1 drops from 3 volts to 0.9 volts and then drops from 3 volts to 0.9 volts, the turn-on/reset signal Vout will be affected by the inverter CM and the transistor group TN. affected and temporarily pulled down to 0 volts, and then rises from 0 volts to 3 volts, so the potential of the turn-on/reset signal Vout is sufficient to enable the digital circuit at the back end to be effectively turned on once, avoiding the problem described in the prior art. Unable to successfully restart the problem.

In other embodiments of the present invention, the transistor group TN shown in FIG. 8 can be replaced by the transistor group Tnpn shown in FIG. 9, the transistor group Tpnp shown in FIG. 10, and the transistor group TP shown in FIG. 11 respectively, and Reach the same purpose as the transistor group TN shown in Figure 8; wherein the transistor group Tnpn includes at least one npn-type bipolar transistors Qnpn1, ..., Qnpnm connected in series in a cascaded manner, and the transistor group Tpnp includes at least one cascaded The pnp-type bipolar transistors Qnpn1, .

Besides, in some embodiments of the present invention, the disposition positions of the transistor groups TN, TP, Tnpn, Tpnp are not limited to be coupled to the NMOS transistor Q22. As shown in FIG. 12 , the transistor group TN is directly coupled to the P-type metal-oxide-semiconductor transistor Q21, and the drain of the transistor QN1 is coupled to the DC voltage source VDD1, and the source of the transistor QNm is coupled to the P-type metal-oxide-semiconductor transistor Q21. source. When the transistor group TN shown in FIG. 12 is replaced by the transistor group TP, Tnpn, or Tpnp, its setting method is similar to that of the transistor group TN shown in FIG. 8 , which will not be repeated here. Moreover, as shown in FIG. 13, the P-type metal-oxide-semiconductor transistor Q21 and the N-type metal-oxide-semiconductor transistor Q22 in the complementary metal-oxide-semiconductor transistor CM can also be coupled to transistor groups TP and TN respectively, and in other aspects of the present invention In an embodiment, the transistor groups TP and TN shown in FIG. 13 can also be replaced by other above-mentioned transistor groups. Therefore, other embodiments produced by replacing the transistor groups shown in FIGS. 12 and 13 with the transistor groups shown in FIGS. 8-11 should still belong to the scope of the present invention.

Please refer to FIG. 14 , which is a schematic diagram of the operation method of the power on/reset circuit disclosed in FIGS. 4-13 . As shown in Figure 14, the method includes the following steps:

Step 402: Make the potential level of the first analog signal vary to follow the potential level of the first DC voltage source.

Step 404: Invert the potential logic of the first analog signal to generate a second analog signal.

Step 406: Adjust the start condition of the inversion, so as to adjust the voltage conversion characteristic curve of the second analog signal.

Step 408 : Use potential logic of the second analog signal to generate an on/reset signal, and control the on/reset state of the digital circuit by the on/reset signal.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (20)

1. electric power starting/reset circuit, comprising:

One voltage follower module, is coupled to one first direct voltage source, and described voltage follower module produces one first analog signal, and the current potential of described the first analog signal height changes the current potential height variation of following described the first direct voltage source; And

One reverse amplification module, be used for receiving described the first analog signal and produce one second analog signal, described in the current potential logical AND of described the second analog signal, the current potential logic of the first analog signal is contrary, and described electric power starting/reset circuit is controlled the unlatching/Reset Status of a digital circuit according to described the second analog signal, the wherein said reverse amplification module utilization string transistorized mode that changes goes to adjust described the second analog signal, and described reverse amplification module comprises:

One first N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to an output of described voltage follower module to receive described the first analog signal;

One the one P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor, the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source, and the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal; And

A first transistor at least one the first transistor is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.

2. electric power starting/reset circuit as claimed in claim 1, is characterized in that:

The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.

3. electric power starting/reset circuit as claimed in claim 1, is characterized in that:

Described electric power starting/reset circuit separately comprises:

At least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to described the second direct voltage source, and separately has a transistor seconds to be coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.

4. electric power starting/reset circuit as claimed in claim 3, is characterized in that:

Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.

5. electric power starting/reset circuit as claimed in claim 3, is characterized in that:

Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.

6. electric power starting/reset circuit as claimed in claim 3, is characterized in that:

Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.

7. electric power starting/reset circuit as claimed in claim 3, is characterized in that:

Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.

8. electric power starting/reset circuit as claimed in claim 1, is characterized in that:

Described voltage follower module comprises:

One the one P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to described the first direct voltage source;

One the 2nd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to drain electrode and the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the base stage of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of a described P type MOS (metal-oxide-semiconductor) transistor;

One the 3rd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;

One first N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor and the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;

One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the source ground of described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its source ground, the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor;

One the 4th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor; And

One the 5th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.

9. electric power starting/reset circuit as claimed in claim 1, is characterized in that:

Described electric power starting/reset circuit separately comprises:

One electric current supply device, is coupled to described the first direct voltage source, and is used for producing an electric current; And

One inverted logic module, be coupled to described reverse amplification module to receive described the second analog signal, and be coupled to described electric current supply device to be driven by described electric current, the intensity that described electric current supply device is also used for controlling described electric current is below a critical current intensity, and described inverted logic module is reversed the current potential logic of described the second analog signal to produce one unlatching/reset signal, makes described electric power starting/reset circuit control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.

10. electric power starting/reset circuit as claimed in claim 9, is characterized in that:

Described electric current supply device comprises:

One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the grid of described the first direct voltage source and described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 4th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor;

One the 5th P type MOS (metal-oxide-semiconductor) transistor, its grid and drain electrode are coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source; And

One the 6th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source;

Described inverted logic module comprises:

One the 7th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to described reverse amplification module, and the source electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor; And

One the 5th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor, the drain electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 4th N-type MOS (metal-oxide-semiconductor) transistor; And

The base stage of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source, and the base stage of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.

11. 1 kinds of electric power starting/reset circuits, comprising:

One voltage follower module, is coupled to one first direct voltage source, and described voltage follower module produces one first analog signal, and the current potential of described the first analog signal height changes the current potential height variation of following described the first direct voltage source; And

One reverse amplification module, be used for receiving described the first analog signal and produce one second analog signal, described in the current potential logical AND of described the second analog signal, the current potential logic of the first analog signal is contrary, and described electric power starting/reset circuit is controlled the unlatching/Reset Status of a digital circuit according to described the second analog signal, the wherein said reverse amplification module utilization string transistorized mode that changes goes to adjust described the second analog signal, and described reverse amplification module comprises:

One first N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to an output of described voltage follower module to receive described the first analog signal;

One the one P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor, the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to one second direct voltage source, and the drain electrode of a described P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and exports described the second analog signal; And

A first transistor at least one the first transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.

12. electric power starting/reset circuits as claimed in claim 11, is characterized in that:

The current potential of described the second direct voltage source is higher than the current potential of described the first direct voltage source.

13. electric power starting/reset circuits as claimed in claim 11, is characterized in that:

Described electric power starting/reset circuit separately comprises:

At least one is with the string transistor seconds that repeatedly mode is connected, and wherein a transistor seconds is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor.

14. electric power starting/reset circuits as claimed in claim 13, is characterized in that:

Described at least one the first transistor is N-type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is P type MOS (metal-oxide-semiconductor) transistor.

15. electric power starting/reset circuits as claimed in claim 13, is characterized in that:

Described at least one the first transistor is P type MOS (metal-oxide-semiconductor) transistor, and described at least one transistor seconds is N-type MOS (metal-oxide-semiconductor) transistor.

16. electric power starting/reset circuits as claimed in claim 13, is characterized in that:

Described at least one the first transistor is npn type bipolar junction transistor, and described at least one transistor seconds is pnp type bipolar junction transistor.

17. electric power starting/reset circuits as claimed in claim 13, is characterized in that:

Described at least one the first transistor is pnp type bipolar junction transistor, and described at least one transistor seconds is npn type bipolar junction transistor.

18. electric power starting/reset circuits as claimed in claim 11, is characterized in that:

Described voltage follower module comprises:

One the one P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to described the first direct voltage source;

One the 2nd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to drain electrode and the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the base stage of described the 2nd P type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of a described P type MOS (metal-oxide-semiconductor) transistor;

One the 3rd P type MOS (metal-oxide-semiconductor) transistor, its source electrode is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of a described P type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;

One first N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd P type MOS (metal-oxide-semiconductor) transistor and the grid of described the 2nd P type MOS (metal-oxide-semiconductor) transistor;

One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the first N-type MOS (metal-oxide-semiconductor) transistor and the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the source ground of described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its source ground, the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor, and the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the first N-type MOS (metal-oxide-semiconductor) transistor;

One the 4th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor; And

One the 5th P type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the source electrode of described the 4th P type MOS (metal-oxide-semiconductor) transistor, the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the grid of described the 4th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to the source electrode of a described P type MOS (metal-oxide-semiconductor) transistor.

19. electric power starting/reset circuits as claimed in claim 11, is characterized in that:

Described electric power starting/reset circuit separately comprises:

One electric current supply device, is coupled to described the first direct voltage source, and is used for producing an electric current; And

One inverted logic module, be coupled to described reverse amplification module to receive described the second analog signal, and be coupled to described electric current supply device to be driven by described electric current, the intensity that described electric current supply device is also used for controlling described electric current is below a critical current intensity, and described inverted logic module is reversed the current potential logic of described the second analog signal to produce one unlatching/reset signal, makes described electric power starting/reset circuit control the unlatching/Reset Status of described digital circuit by described unlatching/reset signal.

20. electric power starting/reset circuits as claimed in claim 19, is characterized in that:

Described electric current supply device comprises:

One second N-type MOS (metal-oxide-semiconductor) transistor, its drain electrode is coupled to the grid of described the first direct voltage source and described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 3rd N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the second N-type MOS (metal-oxide-semiconductor) transistor;

One the 4th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor;

One the 5th P type MOS (metal-oxide-semiconductor) transistor, its grid and drain electrode are coupled to the drain electrode of described the 3rd N-type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source; And

One the 6th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 5th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source;

Described inverted logic module comprises:

One the 7th P type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to described reverse amplification module, and the source electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 6th P type MOS (metal-oxide-semiconductor) transistor; And

One the 5th N-type MOS (metal-oxide-semiconductor) transistor, its grid is coupled to the grid of described the 7th P type MOS (metal-oxide-semiconductor) transistor, the drain electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 7th P type MOS (metal-oxide-semiconductor) transistor, and the source electrode of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the drain electrode of described the 4th N-type MOS (metal-oxide-semiconductor) transistor; And

The base stage of described the 7th P type MOS (metal-oxide-semiconductor) transistor is coupled to described the first direct voltage source, and the base stage of described the 5th N-type MOS (metal-oxide-semiconductor) transistor is coupled to the base stage of described the 4th N-type MOS (metal-oxide-semiconductor) transistor.