CN102569405B - Tunneling transistor with quasi-coaxial cable structure and forming method of tunneling transistor - Google Patents

Abstract

The present invention provides a tunneling transistor with a quasi-coaxial cable structure and a method for forming the same. The tunneling transistor includes: a semiconductor substrate with a first doping type, and the semiconductor substrate is a source region or a drain region; A vertical semiconductor column with a second doping type on the semiconductor substrate, the semiconductor column is a drain region or a source region; a channel region formed on the semiconductor substrate and surrounding the sidewall of the semiconductor column and a gate structure formed on the semiconductor substrate surrounding the sidewall of the channel region. The tunneling transistor according to the embodiment of the present invention can increase the integration degree of the TFET device and improve the driving capability of the TFET device.

Description

Tunneling transistor with quasi-coaxial cable structure and method of forming same

technical field

The invention relates to the technical field of semiconductor design and manufacture, in particular to a tunneling transistor with a quasi-coaxial cable structure and a forming method thereof.

Background technique

For a long time, in order to obtain higher chip density, faster working speed and lower power consumption. The feature size of Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) has been continuously scaling down in accordance with the so-called Moore's law, and their operating speeds are getting faster and faster. At present, it has entered the range of nanoscale. However, a serious challenge that comes with it is the short channel effect, such as subthreshold voltage drop (Vtroll-off), drain-induced barrier lowering (DIBL), source-drain punch through, etc. The off-state leakage current of the device is significantly increased, resulting in performance degradation.

At present, in order to reduce the negative impact brought by the short channel effect, various improvement measures have been proposed, among which the tunneling field effect transistor (Tunneling field effect transistor, TFET) is the most prominent. Since the MOSFET device is in the subthreshold state, the device is weak inversion, and thermionic emission is the main conduction mechanism at this time. Therefore, the subthreshold slope of the MOSFET is limited to 60mV/dec at room temperature. Compared with the traditional MOSFET, on the one hand, because the active region of the tunneling field effect transistor device is essentially a tunneling junction, the tunneling field effect transistor has weaker or even no short channel effect; at the same time, the tunneling field effect transistor The main current mechanism of the field effect transistor is band-to-band tunneling. In the subthreshold region and saturation region, the drain current has an exponential relationship with the applied gate-source voltage, so the tunneling field effect transistor has Lower subthreshold slope, and the current is almost independent of temperature.

The fabrication process of the tunneling field effect transistor is compatible with the traditional complementary metal-oxide-semiconductor field effect transistor (CMOSFET) process. The structure of the TFET transistor is based on a metal-oxide-semiconductor gate-controlled p-i-n diode, as shown in FIG. 1 , which is a typical n-channel TFET in the prior art. Specifically, the N-type channel TFET includes a P-type doped source region 1000' and an N-type doped drain region 2000', the source region and the drain region are separated by a channel region 3000', and the gate The stack 4000' includes a gate dielectric layer and a gate electrode over the channel region.

In the off state of the TFET device, that is, when no gate voltage is applied, the junction formed between the source region 1000' and the drain region 2000' is a reverse-biased diode, and the potential barrier established by the reverse-biased diode is larger than the usual complementary The potential barrier established by the type MOSFET, therefore, leads to a greatly reduced subthreshold leakage current and direct tunneling current of the TFET device even when the channel length is very short. When a voltage is applied to the gate of the TFET, the channel region 3000' of the device generates an electron channel under the action of the field effect. Once the electron concentration in the channel degenerates, the source region 1000' and the channel region 3000' A tunneling junction will be formed between them, and the tunneling current generated by the tunneling will pass through the tunneling junction. From the point of view of the energy band, this tunneling field effect transistor based on the gated P-I-N diode structure adjusts the tunnel length of the PN junction formed between the source region 1000' and the channel region 3000' by controlling the gate voltage .

The shortcoming of existing TFET device is: along with the reduction of the feature size of TFET device, the cross-sectional area of horizontal tunneling between source region and channel region reduces, causes TFET device performance to degrade; In addition, the existing horizontal structure TFET devices restrict the further improvement of its integration.

Contents of the invention

The object of the present invention is to solve at least one of the above-mentioned technical defects, especially to solve or avoid the above-mentioned defects of TFET devices.

In order to achieve the above object, the present invention proposes a tunneling transistor with a quasi-coaxial cable structure, which is characterized in that it includes: a semiconductor substrate with a first doping type, and the semiconductor substrate is a source region or a drain A region; a vertical semiconductor column with a second doping type formed on the semiconductor substrate, the semiconductor column being a drain region or a source region; formed on the semiconductor substrate, surrounding the sidewall of the semiconductor column a channel region; and a gate structure formed on the semiconductor substrate and surrounding sidewalls of the channel region.

In one embodiment of the present invention, the material of the semiconductor column includes: one of Ge, SiGe, or III-V group materials, these semiconductor materials can not only form a heterojunction, but also have a small band gap, which is beneficial to Increase the tunneling probability of the TFET.

In one embodiment of the present invention, the channel region is epitaxially formed, and the thickness of the channel region is less than 10 nm, so that the tunneling path of the TFET can be effectively reduced.

In one embodiment of the present invention, the top of the channel region is lower than the top of the semiconductor pillar, the top of the gate structure is lower than or flush with the top of the channel region, and the source of the TFET The top of the region and the gate are set at different levels to avoid the interconnection of the vias (ie, the source contact and the gate contact) at the top of the source region and the gate, which is beneficial to reduce the process difficulty of manufacturing the source contact and the gate contact .

In one embodiment of the present invention, if the semiconductor pillar is used as the source region and the semiconductor substrate is used as the drain region: then when the semiconductor pillar is heavily doped with P type, the channel region is P-type Weakly doped, N-type weakly doped or intrinsic, when the semiconductor substrate is N-type heavily doped, an N-type tunneling field effect transistor is formed; when the semiconductor column is N-type heavily doped, the trench The channel region is N-type weakly doped, P-type weakly doped or intrinsic, and when the semiconductor substrate is P-type heavily doped, a P-type tunneling field effect transistor is formed. If the semiconductor column is used as the drain region and the semiconductor substrate is used as the source region, then when the semiconductor column is heavily doped with P type, the channel region is weakly doped with P type and weakly doped with N type. Or intrinsically, when the semiconductor substrate is N-type heavily doped, a P-type tunneling field effect transistor is formed; when the semiconductor column is N-type heavily doped, the channel region is N-type weakly doped, P-type weak doping or intrinsic, when the semiconductor substrate is P-type heavily doped, an N-type tunneling field effect transistor is formed.

Another aspect of the present invention also proposes a method for forming a tunneling transistor with a quasi-coaxial cable structure, including the following steps: providing a semiconductor substrate, and performing a first type of doping on the semiconductor substrate to form a source region or a drain region; forming a vertical semiconductor column on the semiconductor substrate, and performing second-type doping on the semiconductor column to form a columnar drain region or source region; forming a channel region around the sidewall of the semiconductor column; surrounding the semiconductor column The sidewall of the channel region forms a gate structure.

In one embodiment of the present invention, forming the vertical semiconductor pillars includes: growing semiconductor nanowires or nanobelts on the semiconductor substrate to form the vertical semiconductor pillars. The semiconductor pillars formed by growing nanowires or nanoribbons can further form a double gate or gate-all-around structure on it, which is beneficial to increase the control ability of the gate to the channel region, increase the effective electric field, and increase tunneling. probability.

In one embodiment of the present invention, the material of the semiconductor column includes: one of Ge, SiGe, or III-V group materials, these semiconductor materials can not only form a heterojunction, but also have a small band gap, which is beneficial to Increase the tunneling probability of the TFET.

In one embodiment of the present invention, forming the source region, the drain region and the channel region includes: performing N-type heavy doping on the semiconductor substrate to form the source region or the drain region; Performing P-type heavy doping to form the columnar drain region or source region, and performing P-type weak doping, N-type weak doping or intrinsic doping on the channel region to form the channel region; or, Performing P-type heavy doping on the semiconductor substrate to form the source region or drain region, performing N-type heavy doping on the semiconductor pillar to form the pillar-shaped drain region or source region, and The channel region is weakly doped with P type, weakly doped with N type or intrinsic to form the channel region. If the semiconductor column is used as the source region and the semiconductor substrate is used as the drain region, the first doping state constitutes an N-type tunneling field effect transistor, and the second doping state constitutes a P-type tunneling field effect transistor. ; If the semiconductor column is used as the drain region and the semiconductor substrate is used as the source region, then the first doping state constitutes a P-type tunneling field effect transistor, and the second doping state constitutes an N-type tunneling field effect transistor. transistor.

In one embodiment of the present invention, forming the channel region includes the following steps: forming the channel layer on the semiconductor substrate and the surface of the semiconductor pillar; forming a first mask on the channel layer layer, the top of the first mask layer is lower than the top of the semiconductor pillar, so as to expose part of the channel layer formed on the top of the semiconductor pillar; etch the exposed part of the channel layer; remove the first a mask layer; and removing the channel layer formed on the semiconductor substrate, so that the channel layer surrounding the sidewall of the semiconductor column is formed as a channel region, the channel region The top is lower than the top of the semiconductor pillar. In a preferred embodiment of the present invention, a channel layer is epitaxially grown on the surface of the semiconductor substrate and the semiconductor column, and the thickness of the channel layer formed by epitaxial growth can reach less than 10 nm, thereby effectively reducing the Tunneling path of TFET.

In one embodiment of the present invention, forming the gate structure includes the following steps: forming a gate dielectric layer on the semiconductor substrate, the channel region, and the surface of the semiconductor column; forming a second gate dielectric layer on the gate dielectric layer Two mask layers, the top of the second mask layer is lower than or flush with the top of the channel region, so as to expose part of the gate dielectric layer formed on the top of the semiconductor pillar and the top of the channel region; Etching the exposed part of the gate dielectric layer; removing the second mask layer, so that the remaining gate dielectric layer is formed as a gate dielectric; region and the surface of the semiconductor pillar to form a gate layer; a third mask layer is formed on the gate layer, and the top of the third mask layer is substantially flush with the top of the gate dielectric to expose the part of the gate layer at the top of the semiconductor pillar, the top of the channel region, and the top of the gate dielectric; etching the exposed part of the gate layer; removing the third mask layer; The gate layer on the semiconductor substrate, so that the gate layer surrounding the sidewall of the channel region is formed as a gate.

In one embodiment of the present invention, the first mask layer, the second mask layer and the third mask layer are formed by depositing high-density plasma oxide.

The present invention provides a tunneling transistor with a quasi-coaxial cable structure and its forming method. On the one hand, a vertical three-dimensional structure is formed by forming a source region or a drain region, a channel region, and a gate structure on the drain region or the source region TFET, so as to improve the integration of TFET devices; on the other hand, the source region or drain region, channel region, and gate structure are arranged in the horizontal direction as a coaxial cable structure, and the circular tunneling from the source region to the channel region Compared with the ordinary planar tunneling cross section, the tunneling cross-sectional area is greatly increased, and the control ability of the gate to the channel region is significantly enhanced, thereby improving the driving ability of the TFET device.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

FIG. 1 is a structural diagram of a typical n-type tunneling field effect transistor in the prior art;

2 is a perspective view of a TFET structure with a quasi-coaxial cable structure according to an embodiment of the present invention;

Fig. 3 is the sectional view of the TFET structure with quasi-coaxial cable structure shown in Fig. 2;

4-12 are structural cross-sectional views of each step of the method for forming a TFET structure with a quasi-coaxial cable structure according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

The following disclosure provides many different embodiments or examples for implementing different structures of the present invention. To simplify the disclosure of the present invention, components and arrangements of specific examples are described below. Of course, they are only examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in different instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and/or arrangements discussed. In addition, various specific process and material examples are provided herein, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials. Additionally, configurations described below in which a first feature is "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may include additional features formed between the first and second features. For example, such that the first and second features may not be in direct contact.

2 and 3 are respectively a perspective view and a cross-sectional view of a TFET structure with a quasi-coaxial cable structure according to an embodiment of the present invention. As shown in Figures 2 and 3, a TFET with a quasi-coaxial cable structure according to an embodiment of the present invention includes: a semiconductor substrate 100 with a first doping type, and the semiconductor substrate 100 is the source or drain region of the TFET A vertical semiconductor column 200 with a second doping type formed on the semiconductor substrate 100, the semiconductor column 200 is the drain region or source region of the TFET; a ditch formed on the semiconductor substrate 100 surrounding the sidewall of the semiconductor column 200 channel region 300 ; and a gate structure 400 formed on the semiconductor substrate 100 and surrounding the sidewall of the channel region 300 . It should be noted that, in each embodiment of the present invention, the semiconductor substrate 100 is used as the drain region, and the semiconductor pillar 200 is used as the source region (for simplicity, the drain region is marked as 100 in FIGS. 2 and 3 , and the source region is marked as 200) as an example, the tunneling transistor structure with a quasi-coaxial cable structure obtained by exchanging source and drain regions is also included in the protection scope of the present invention. That is to say, the TFET according to the embodiment of the present invention, viewed from the horizontal direction, includes a three-layer coaxial cable structure, the inner layer is the source region 200, the middle layer is the channel region 300, and the outer layer is the gate structure 400; See, the source region 200 in the inner layer, the channel region 300 in the middle layer, and the drain region 100 at the bottom of the two constitute a quasi-coaxial cable structure, wherein the drain region 100 is equivalent to the outer layer of the quasi-coaxial cable structure. In addition, since the channel region 300 is in the shape of a circular column and surrounds the sidewall of the semiconductor column 200, the tunneling cross-section from the inner layer source region 200 to the channel region 300 of the TFET structure is a circular tunneling cross-section. Planar tunneling cross-section, the tunneling cross-sectional area is greatly increased, and the control ability of the gate to the channel region is significantly enhanced, thereby improving the driving ability of the TFET device.

In the embodiment of the present invention, the material of the semiconductor pillar 200 may include one of Ge, SiGe, or III-V group materials. These semiconductor materials can not only form a heterojunction, but also have a small forbidden band width, which is beneficial to increase the TFET. The tunneling probability of .

The material of the semiconductor substrate 100 may include semiconductor materials such as silicon, germanium, diamond, silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Furthermore, the substrate 100 may optionally include epitaxial layers, which may be altered by stress to enhance its performance, and may also include silicon-on-insulator (SOI) structures. In this embodiment, silicon is used as the substrate, that is, the material of the drain region 100 is silicon; the channel region 300 can be a material known to those skilled in the art that is suitable as a channel region, such as silicon; the material of the gate structure 400 Can be polysilicon or metal.

In the embodiment of the present invention, the channel region 300 can be formed by epitaxy, and the thickness of the channel region can reach less than 10 nm. Since the tunneling path of the TFET is from the source region 200 to the channel region 300, a smaller thickness of the channel region can effectively reduce the tunneling path of the TFET.

In the embodiment of the present invention, preferably, the top of the channel region 300 is lower than the top of the semiconductor pillar 200, the top of the gate structure 400 is lower than or flush with the top of the channel region 300, by connecting the source region and the gate of the TFET The tops of the poles are arranged on different levels to avoid interconnection of the via holes (ie source contacts and gate contacts) at the top of the source region and the gate, which is beneficial to reduce the process difficulty of manufacturing source contacts and gate contacts.

In the embodiment of the present invention, for an N-type TFET, the source region 200 (semiconductor column 200) is heavily doped P-type, the channel region 300 is weakly doped P-type, weakly N-type doped or intrinsic, and the drain region 100 (Semiconductor substrate 100) is N-type heavily doped; for P-type TFET, the source region 200 (semiconductor column 200) is N-type heavily doped, and the channel region 300 is N-type weakly doped, P-type weakly doped or Intrinsically, the drain region 100 (semiconductor substrate 100 ) is heavily doped with P type.

4-12 are structural cross-sectional views of each step of the method for forming a TFET structure with a quasi-coaxial cable structure according to an embodiment of the present invention. It should be noted that, in the embodiment of the present invention, the formation method is described by taking the formation of an N-type TFET as an example, and the formation method of the P-type TFET may refer to the following steps, which will not be repeated here. A forming method according to an embodiment of the present invention includes the following steps.

Step S101 : providing a semiconductor substrate 100 , and performing a first type of doping on the semiconductor substrate 100 to form a source region or a drain region. The material of the semiconductor substrate 100 may include semiconductor materials such as silicon, germanium, diamond, silicon carbide, gallium arsenide, indium arsenide or indium phosphide. Furthermore, the substrate 100 may optionally include epitaxial layers, which may be altered by stress to enhance its performance, and may also include silicon-on-insulator (SOI) structures. In this embodiment, silicon is used as the substrate, and the silicon substrate 100 is heavily doped with N type to form the drain region 100 .

Step S102 : forming a vertical semiconductor column 200 on the semiconductor substrate 100 , and performing second type doping on the semiconductor column 200 to form a columnar drain region or source region, as shown in FIG. 4 . The material of the semiconductor pillar 200 may include one of Ge, SiGe, or group III-V materials. These semiconductor materials can not only form a heterojunction, but also have a small forbidden band width, which is beneficial to increase the tunneling probability of the TFET. In this embodiment, the material of the semiconductor pillar 200 is Ge. The semiconductor column 200 can be formed by a photolithography process. In a preferred embodiment of the present invention, semiconductor nanowires or nanoribbons (such as Ge nanowires or nanoribbons) can be grown on the semiconductor substrate 100 to form the vertical semiconductor column 200, and then The semiconductor pillar 200 is heavily doped with P type to form the source region 200 . The semiconductor column 200 formed by growing nanowires or nanoribbons can further form a double gate or a ring gate (gate-all-around) structure on it, which is conducive to increasing the control ability of the gate to the channel region, increasing the effective electric field, and increasing the tunneling efficiency. wear probability.

Step S103 : forming a channel region 300 around the sidewall of the semiconductor pillar 200 . Specifically, the following steps may be included:

(3-1) A channel layer 302 is formed on the surface of the semiconductor substrate 100 and the semiconductor pillar 200 , as shown in FIG. 5 . In a preferred embodiment of the present invention, the channel layer 302 is epitaxially grown on the surface of the semiconductor substrate 100 and the semiconductor column 200, the thickness of the channel layer formed by epitaxy can reach less than 10nm, and the smaller thickness of the channel region can effectively reduce the Tunneling paths for small TFETs. In this embodiment, the material of the channel layer 302 may be silicon; the channel layer 302 may be P-type weakly doped, N-type weakly doped or intrinsic.

(3-2) Forming a first mask layer 304 on the channel layer 302, the top of the first mask layer 304 is lower than the top of the semiconductor pillar 200, to expose part of the channel layer 302 formed on the top of the semiconductor pillar 200, As shown in Figure 6. Specifically, the first mask layer 304 may be formed by depositing a high density plasma (HDP) oxide. Since the thickness of the first mask layer 304 determines the height of the finally formed channel region 300, in this embodiment, preferably, the top of the first mask layer 304 is lower than the top of the semiconductor pillar 200, so that the formed The top of the channel region 300 is lower than the top of the source region 200 .

(3-3) Etching the exposed part of the channel layer 302 , for example, the material silicon of the channel layer 302 may be selectively etched.

(3-4) The first mask layer 304 is removed.

(3-5) Remove the channel layer 302 formed on the semiconductor substrate 100, so that the channel layer 302 surrounding the sidewall of the semiconductor column 200 is formed as a channel region 300, and the top of the channel region is lower than the semiconductor column 200 at the top, as shown in Figure 7. In this embodiment, isotropic dry etching, such as reactive plasma etching, can be used to simultaneously remove the same thickness of the channel layer 302 located on the semiconductor substrate 100 and surrounding the side walls of the semiconductor pillar 200, This thickness is equal to the thickness of the channel layer 302 on the semiconductor step 306 . It should be pointed out that when the channel layer 302 on the semiconductor substrate 100 is removed, the height of the channel layer 302 surrounding the sidewall of the semiconductor pillar 200 will also be damaged, but the etched height is only The loss is less than 10 nm, which is much smaller than the height of the channel region 300, so the loss can be ignored.

Step S104 : forming a gate structure 400 around the sidewall of the channel region 300 . In this example, the gate structure 400 may include a gate dielectric 402 and a gate 404 . Forming the gate dielectric 402 and the gate 404 may specifically include the following steps:

(4-1) Form a gate dielectric layer 401 on the surface of the semiconductor substrate 100 , the channel region 300 , and the semiconductor pillar 200 , as shown in FIG. 8 . The material of the gate dielectric layer 401 can be a high-k dielectric material, such as hafnium-based materials, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium oxide Titanium (HfTiO), hafnium zirconium oxide (HfZrO), combinations thereof and/or other suitable materials. The deposition of the gate dielectric layer 401 can be formed by a conventional deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), atomic layer deposition (ALD), plasma Enhanced Atomic Layer Deposition (PEALD) or other methods.

(4-2) Form a second mask layer on the gate dielectric layer, the top of the second mask layer is lower than the top of the channel region 300 to expose the part of the gate formed on the top of the semiconductor column 200 and the channel region 300 Dielectric layer 401. The second mask layer can be formed with reference to the method for forming the first mask layer 304 . Similarly, since the thickness of the second mask layer determines the height of the finally formed gate structure 400, in this embodiment, preferably, the top of the second mask layer is lower than or flush with the top of the channel region 300 , so that the top of the formed gate structure 400 is lower than the top of the channel region 300 .

(4-3) Etching the exposed part of the gate dielectric layer 401 , for example, the high-k dielectric material of the gate dielectric layer 401 may be selectively etched.

(4-4) The second mask layer is removed, so that the remaining gate dielectric layer 401 is formed as a gate dielectric 402 , as shown in FIG. 9 .

(4-5) Form a gate layer 403 on the surface of the semiconductor substrate 100 , the gate dielectric 402 , the channel region 300 , and the semiconductor pillar 200 , as shown in FIG. 10 . The material of the gate layer 403 can be polysilicon, and the deposition of the gate layer 403 can be formed by a conventional deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), pulsed laser deposition (PLD), Atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD) or other methods.

(4-6) Form a third mask layer on the gate layer 403, the top of the third mask layer is substantially flush with the top of the gate dielectric 402, to expose the top of the semiconductor column 200, the top of the channel region 300 and the A portion of the gate layer 403 on top of the gate dielectric 402 . The third mask layer can be formed with reference to the method for forming the first mask layer 304 .

(4-7) Etching the exposed part of the gate layer 403 , for example, the material of the gate layer 403 may be selectively etched polysilicon.

(4-8) The third mask layer is removed.

(4-9) The gate layer 403 formed on the semiconductor substrate 100 is removed, so that the gate layer 403 surrounding the sidewall of the channel region 300 is formed as a gate 404 , as shown in FIG. 11 . In this embodiment, isotropic dry etching, such as reactive plasma etching, may be used to remove the gate layer 403 formed on the semiconductor substrate 100 .

In the embodiment of the present invention, after step S104 , forming a via hole and filling metal on top of the gate 404 and the source region 200 as the gate contact 405 and the source region contact 407 , as shown in FIG. 12 . Since the embodiment of the present invention arranges the source region and the top of the gate of the TFET at different levels, it can avoid the interconnection of the via holes (ie, the source contact and the gate contact) at the top of the source region and the gate due to process errors. The problem is beneficial to reduce the process difficulty of manufacturing the source contact and the gate contact.

Embodiments of the present invention provide a tunneling transistor with a quasi-coaxial cable structure and a method for forming the same. On the one hand, a source region or a drain region, a channel region, and a gate structure are formed on the drain region or the source region to form a vertical structure. Three-dimensional structure of TFET, so as to improve the integration of TFET devices; Compared with the ordinary planar tunneling cross section, the tunneling cross section greatly increases the tunneling cross section, thereby improving the performance of the TFET device.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims (11)

1. a tunneling transistor with accurate coaxial cable structure, is characterized in that, comprising:

The Semiconductor substrate with the first doping type, described Semiconductor substrate is source region or drain region;

Be formed on the vertical semiconductor post with the second doping type in described Semiconductor substrate, described semiconductor column is drain region or source region;

Be formed in described Semiconductor substrate, around the channel region of described semiconductor column sidewall; With

Be formed in described Semiconductor substrate, around the grid structure of described channel region sidewall, wherein, the top of described channel region is lower than the top of described semiconductor column, the top of described grid structure lower than or flush in the top of described channel region.

2. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that, the material of described semiconductor column comprises: Ge, SiGe or III-V family material.

3. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that, described channel region is that extension forms, and the thickness of described channel region is less than 10nm.

4. the tunneling transistor with accurate coaxial cable structure as claimed in claim 1, is characterized in that:

Described semiconductor column is the heavy doping of P type, and described channel region is P type weak doping, N-type weak doping or intrinsic, and described Semiconductor substrate is N-type heavy doping; Or

Described semiconductor column is N-type heavy doping, and described channel region is N-type weak doping, P type weak doping or intrinsic, and described Semiconductor substrate is the heavy doping of P type.

5. a formation method with the tunneling transistor of accurate coaxial cable structure, is characterized in that, comprises the following steps:

Semiconductor substrate is provided, described Semiconductor substrate is carried out to first kind doping to form source region or drain region;

In described Semiconductor substrate, form vertical semiconductor post, described semiconductor column is carried out to Second Type doping with the pillared drain region of shape or source region;

Sidewall around described semiconductor column forms channel region;

Sidewall around described channel region forms grid structure, wherein,

Forming described channel region comprises:

In described Semiconductor substrate and described semiconductor column surface, form channel layer;

On described channel layer, form the first mask layer, the top of described the first mask layer is lower than the top of described semiconductor column, to expose the part channel layer that is formed on described semiconductor column top;

The described part channel layer that etching exposes;

Remove described the first mask layer; With

Removal is formed on the described channel layer in described Semiconductor substrate, so that be looped around the described channel layer of described semiconductor column sidewall, forms channel region, and the top of described channel region is lower than the top of described semiconductor column.

6. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, it is characterized in that, forming described vertical semiconductor post comprises: growing semiconductor nano wire or nanobelt in described Semiconductor substrate, and to form described vertical semiconductor post.

7. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, the material of described semiconductor column comprises: Ge, SiGe or III-V family material.

8. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, forms described source region, drain region and channel region and comprises:

Described Semiconductor substrate is carried out to N-type heavy doping to form described source region or drain region, described semiconductor column is carried out to the heavy doping of P type to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region; Or

Described Semiconductor substrate is carried out to the heavy doping of P type to form described source region or drain region, described semiconductor column is carried out to N-type heavy doping to form drain region or the source region of described column, and P type weak doping, N-type weak doping or intrinsic are carried out to form described channel region in described channel region.

9. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, in described Semiconductor substrate and described semiconductor column surface extension, forms described channel layer, and the thickness of described channel layer is less than 10nm.

10. the formation method with the tunneling transistor of accurate coaxial cable structure as claimed in claim 5, is characterized in that, forms described grid structure and comprises:

On described Semiconductor substrate, described channel region, described semiconductor column surface, form gate dielectric layer;

On described gate dielectric layer, form the second mask layer, the top of described the second mask layer lower than or flush in the top of described channel region, to expose the part gate dielectric layer that is formed on described semiconductor column top and top, described channel region;

The described part gate dielectric layer that etching exposes;

Remove described the second mask layer, so that remaining described gate dielectric layer forms gate medium;

On described Semiconductor substrate, described gate medium, described channel region, described semiconductor column surface, form grid layer;

On described grid layer, form the 3rd mask layer, the top of described the 3rd mask layer flushes in the top of described gate medium substantially, to expose the described grid layer of part that is formed on described semiconductor column top, top, described channel region and described gate medium top;

The described part of grid pole layer that etching exposes;

Remove described the 3rd mask layer; With

Removal is formed on the described grid layer in described Semiconductor substrate, so that be looped around the described grid layer of described channel region sidewall, forms grid.

The formation method of 11. tunneling transistors with accurate coaxial cable structure as described in claim 5 or 10, is characterized in that, by deposit high density plasma oxide to form described the first mask layer, the second mask layer and the 3rd mask layer.

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