CN102569071B - Gallium Nitride Transistor Fabrication Method - Google Patents

Abstract

The invention relates to a method for manufacturing a gallium nitride transistor, which comprises a preparation step, an opening forming step, an ion distribution step, a dielectric layer forming step, a source/drain electrode deposition step and a grid electrode deposition step.

Description

Gallium Nitride Transistor Fabrication Method

technical field

The invention relates to a method for manufacturing a gallium nitride transistor, in particular to a method for manufacturing an enhancement mode (E-mode) gallium nitride transistor. the

Background technique

Referring to FIG. 1 is a conventional gallium nitride transistor structure, including a substrate 11, a first polycrystalline gallium nitride film 121, an aluminum gallium nitride polycrystalline film 122 formed on the surface of the substrate 11 in sequence, and A semiconductor layer 12 of a second gallium nitride polycrystalline film 123, a dielectric layer 13 formed on the top surface of the semiconductor layer 12, a gate 14 formed on the top surface of the dielectric layer 13, and formed on the top surface of the dielectric layer 13 respectively A source 15 and a drain 16 on both sides of the dielectric layer 13 . the

In the gallium nitride transistor, since the first gallium nitride polycrystalline film 121 and the aluminum gallium nitride polycrystalline film 122 in the structure of the semiconductor layer 12 will generate a large amount of polarized charges to form a two-dimensional electron gas (2DEG), The transistor needs to operate in the depletion mode. The transistor operated in the depletion mode is generally called a normal on transistor. Since the threshold voltage of the normally on transistor is negative, therefore, in When the gate is at zero bias, the transistor will still conduct current, which will cause additional power loss; in addition, when the aforementioned GaN transistor is applied to a high-power circuit system, since the high-power circuit system needs to operate at an extremely high bias voltage Operating in an environment is prone to transient pulse voltages. If the critical voltage of a transistor is not high enough, it will also cause abnormal conduction of high-power components, causing component malfunctions and affecting the stability of the system. the

In order to improve the previous gallium nitride transistors so that they have the characteristics of high threshold voltage, high voltage resistance, high output power and enhanced operation, US Patent No. US7655962 discloses a barrier layer under the AlGaN channel, using the barrier layer The polarized charge empties the charge of the channel, and at the same time uses a deep recessed gate structure (deep recessed gate), so that the transistor is not turned on at zero bias, and becomes an enhancement transistor; in addition, in the US 2007/0295993 publication Patent No. 1 discloses a CF4 plasma treatment method, which allows fluorine ions to enter the charge of the depleted channel in the AlGaN channel, so that the transistor does not conduct at zero bias, and becomes an enhancement transistor; however, the aforementioned deep recessed gate The electrode structure must be introduced into the surface etching, which will easily increase the density of the surface state of the transistor, and easily affect the current characteristics and reliability of the transistor; and the use of CF4 plasma treatment, although it can be introduced into the element by fluorine ions To improve the threshold voltage, however, limited by the diffusion ability of fluorine ions, the range of the threshold voltage raised by CF4 plasma treatment is at most +0.9V, which still cannot meet the demand. the

Therefore, how to provide a gallium nitride transistor with high threshold voltage, high voltage resistance, high output power and enhanced operation characteristics under the condition of maintaining the reliability of the gallium nitride transistor device is one of the continuous development directions of those in the technical field. one. the

It can be seen that the above-mentioned existing gallium nitride transistor obviously still has inconveniences and defects in the method and use, and further improvement is urgently needed. In order to solve the above-mentioned problems, relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time. Therefore, how to create a new method of manufacturing GaN transistors has also become a problem. Targets that are currently in great need of improvement in the industry. the

Contents of the invention

The purpose of the present invention is to overcome the defects of the existing GaN transistors and provide a new manufacturing method for GaN transistors. The technical problem to be solved is to provide an enhanced transistor with high critical voltage. The method of formulating gallium nitride transistors is very suitable for practical use. the

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A method for manufacturing a gallium nitride transistor according to the present invention includes a preparatory step of preparing a light-emitting element, the light-emitting element has a substrate, and a semiconductor polycrystalline layer formed on the substrate, and the semiconductor polycrystalline layer is The crystal layer contains N-type gallium nitride-based semiconductor material; an opening forming step is to form a first covering layer made of insulating material on the surface of the semiconductor polycrystalline layer, and a first covering layer formed on the surface of the first covering layer The second cover layer, and the second cover layer defines an opening that exposes part of the surface of the first cover layer; an ion distribution step, using ion distribution from the opening downward to the semiconductor polycrystalline P-type ion distribution is performed on the semiconductor polycrystalline layer, and a doped region is formed in the semiconductor polycrystalline layer, and then the first and second covering layers are removed to expose the semiconductor polycrystalline layer; a dielectric layer is formed in the semiconductor polycrystalline layer. A dielectric layer made of high dielectric constant material is deposited on the semiconductor polycrystalline layer; a source/drain electrode deposition step is used to remove the structure of the dielectric layer corresponding to the two sides of the doped region to the The semiconductor polycrystalline layer is exposed, and then metal is deposited on the exposed semiconductor polycrystalline layer to form a source and a drain on both sides of the doped region; and a gate deposition step, on the dielectric layer The fabrication of the GaN transistor can be completed by depositing metal on the predetermined surface to form a gate. the

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures. the

The aforementioned method for manufacturing a GaN transistor, wherein the semiconductor polycrystalline layer has a first GaN polycrystalline film, an AlGaN polycrystalline film, and a second GaN polycrystalline film formed upwardly from the substrate in sequence. GaN polycrystalline film. the

In the aforementioned method for manufacturing GaN transistors, the depth of the doped region formed in the ion distribution step is not greater than one-half of the thickness of the second GaN polycrystalline film. the

The above-mentioned fabrication method of gallium nitride transistor, which also includes a plasma treatment step before the ion distributing step, is to make fluorine ions enter the aluminum nitride through the opening by means of plasma treatment Gallium polycrystalline film. the

In the aforementioned method for manufacturing a gallium nitride transistor, the first covering layer is selected from silicon dioxide and silicon nitride, and has a thickness between 50-150 nm.

The aforementioned method for manufacturing a GaN transistor, wherein the dielectric layer is made of materials selected from Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , CeO ₂ , HfAlO, TiO ₂ , and ZrO ₂ .

Compared with the prior art, the present invention has obvious advantages and beneficial effects. As can be seen from the above, in order to achieve the above object, the present invention provides a method for manufacturing a gallium nitride transistor, comprising a preparation step, an opening forming step, an ion distribution step, a dielectric layer forming step, a source/drain electrode deposition step, and a gate deposition step. The preparation step is to firstly prepare a light-emitting element, the light-emitting element has a substrate, and a semiconductor polycrystalline layer formed on the substrate, and the semiconductor polycrystalline layer contains N-type GaN-based semiconductor material. The opening forming step is to form a first covering layer made of insulating material on the surface of the semiconductor polycrystalline layer, and a second covering layer formed on the surface of the first covering layer, and the second covering layer The layer defines an opening that exposes a portion of the surface of the first covering layer. The step of ion distribution is to perform P-type ion distribution on the semiconductor polycrystalline layer from the opening to form a doped region in the semiconductor polycrystalline layer in the form of ion distribution, and then the first and second masks The capping layer is removed, exposing the semiconductor polycrystalline layer. The dielectric layer forming step is to deposit a dielectric layer made of high dielectric constant material on the semiconductor polycrystalline layer. The source/drain deposition step is to remove the structure of the dielectric layer corresponding to the two sides of the doped region by lithography to expose the semiconductor polycrystalline layer, and then deposit metal on the exposed semiconductor polycrystalline layer , forming a source and a drain on both sides of the doped region. The gate deposition step is to deposit metal on the predetermined surface of the dielectric layer to form a gate, and then the gallium nitride transistor can be completed. the

With the above-mentioned technical solution, the manufacturing method of the gallium nitride transistor of the present invention has at least the following advantages and beneficial effects: a P-type doped region is directly formed in the semiconductor polycrystalline layer by means of ion distribution, and a P-N junction is obtained, The threshold voltage can be increased, and a dielectric layer is formed on the doped region of the semiconductor polycrystalline layer, so that an enhanced gallium nitride transistor with high threshold voltage and low leakage current can be obtained. the

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings. the

Description of drawings

Figure 1 is a schematic diagram of a conventional gallium nitride transistor;

Fig. 2 is a schematic structural view illustrating a gallium nitride transistor made by a preferred embodiment of the present invention;

Fig. 3 is a flowchart illustrating this preferred embodiment of the present invention;

Fig. 4 is a schematic flow chart, assisting in explaining steps 31-33 of Fig. 3;

Fig. 5 is a schematic flow chart, assisting to illustrate the steps 34-35 of Fig. 3;

FIG. 6 is a schematic flowchart to assist in explaining step 36 in FIG. 3 . the

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the specific implementation methods, methods and steps of the manufacturing method of the gallium nitride transistor proposed according to the present invention will be described below in conjunction with the accompanying drawings and preferred embodiments. , features and their effects are described in detail below. the

Referring to FIG. 2 , a preferred implementation side of a fabrication method of a GaN transistor according to the present invention can be used to fabricate a GaN transistor as shown in FIG. 2 . the

The GaN transistor includes a substrate 21 , a semiconductor polycrystalline layer 22 , a dielectric layer 23 , and an electrode unit 24 . the

The substrate 21 can be made of transparent or opaque insulating material, such as sapphire, silicon, or silicon carbide, because the materials of the substrate 21 and the semiconductor polycrystalline layer 22 are selected for this technology It is well known to those in the art and is not the focus of the present invention, so no further description will be given. the

In this embodiment, the substrate 21 is made of sapphire, the semiconductor polycrystalline layer 22 is made of N-type gallium nitride semiconductor material, and has a first gallium nitride formed upwardly from the surface of the substrate 21 (GaN) polycrystalline film 221, an aluminum gallium nitride (AlGaN) polycrystalline film 222, a second gallium nitride polycrystalline film 223, and one from the second gallium nitride polycrystalline film 223 top surface The p-type doped region 224 is formed downward of the predetermined region. the

The dielectric layer 23 is formed on a predetermined area on the top surface of the second gallium nitride polycrystalline film 223 and covers the p-type doped region 224, and is made of a high dielectric constant material, which can make the aluminum gallium nitride polycrystalline The carriers and charges of the film 222 increase, and the bias voltage (positive value) of the gate 243 is raised. The high dielectric constant material suitable for this preferred embodiment of the present invention is Al ₂ O ₃ , HfO ₂ , La ₂ O ₃ , CeO ₂ , HfAlO, TiO ₂ , ZrO ₂ .

The electrode unit 24 is made of conductive material, has a source electrode 241, a drain electrode 242 formed on the top surface of the gallium nitride polycrystalline film 223, and located on both sides of the dielectric layer 23, and a drain electrode 242 formed on the dielectric layer 23. Layer 23 is remote from the gate 243 on the surface of the doped region 224 . the

Since the gallium nitride material itself has n-type characteristics with electrons as multiple carriers, the p-n junction (p-n junction) between the p-type doped region 224 and the second gallium nitride polycrystalline film 223 The formed built-in voltage can be used to increase the threshold voltage of the GaN transistor, and the dielectric layer 23 formed on the doped region 224 can be used to further increase the threshold voltage of the GaN transistor and reduce it. Leakage current, to obtain a high critical voltage, and can improve the transistor's drain output current (drain output current), and transfer conductance (transconductance) and other characteristics, and can be more suitable for the next generation of high-performance high-voltage drive and control circuits system enhancement GaN transistors. the

The above-mentioned GaN transistor can be more clearly understood with the following description of the preferred embodiment of the fabrication method of the GaN transistor of the present invention. the

Referring to FIG. 3 , the preferred embodiment of the manufacturing method of the GaN transistor of the present invention includes the following six steps. the

Referring to FIG. 4 , firstly, a preparation step 31 is performed to prepare a light-emitting element 2a. the

In the preparation step 31 , a light emitting device 2 a having a substrate 21 and a semiconductor polycrystalline layer 22 formed on the substrate 21 is firstly prepared. the

In detail, the light-emitting element 2a is a general GaN transistor. In this embodiment, the substrate 21 is made of sapphire, and the semiconductor polycrystalline layer 22 has a first layer formed sequentially from the surface of the substrate 21. A three-layer structure of a GaN polycrystalline film 221 , an AlGaN polycrystalline film 222 , and a second GaN polycrystalline film 223 . the

Then an opening forming step 32 is performed to form a first covering layer 225 defining an opening 226 on the semiconductor polycrystalline layer 22 . the

The step 32 is to form a silicon dioxide, nitrogen A first covering layer 225 made of silicon, aluminum oxide and other insulating materials, and then a second covering layer 225a made of photoresist material is coated on the surface of the first cover layer 225. The photoresist material can be selected from Positive-type photoresist or negative-type photoresist, since the selection of the type of photoresist material is well known in the art and is not the focus of this technology, no further description is given. Next, the second covering layer is lithographically The predetermined structure of 225 a is removed, so that part of the surface of the first covering layer 225 is exposed, and an opening 226 is defined. the

It is worth mentioning that the first covering layer 225 is used to control the depth of subsequent ion distribution. When the thickness of the first covering layer 225 is too thick, the ions cannot enter the semiconductor polycrystalline layer 22 to achieve doping. Conversely, when the thickness of the first covering layer 225 is insufficient, the implanted ions will pass through the area to be implanted, and the PN junction cannot be formed. Preferably, the thickness of the first covering layer 225 Not less than 50nm, more preferably, the thickness of the first covering layer 225 is between ^50-150nm .

Continuing to refer to FIG. 4 , an ion distribution step 33 is performed to form a p-type doped region 224 in the semiconductor polycrystalline layer 22 . the

The step 33 is to perform p-type ion distribution on the second gallium nitride polycrystalline film 223 downward through the opening 226 in the way of ion distribution, and form a p-type doped ion in the second gallium nitride polycrystalline film 223. impurity region 224 , and then remove the remaining second covering layer 225 a and the first covering layer 225 to expose the second GaN polycrystalline film 223 . the

Specifically, the distributed ions in step 33 are selected from ions that can form a p-type gallium nitride junction, such as magnesium ions and boron ions. 223 for P-type ion distribution. the

It is worth mentioning that when the formed p-type doped region 224 is too deep, it will affect the formation of a two-dimensional electron gas (2DEG) by the second GaN polycrystalline film 223/AlGaN polycrystalline film 222 channel, and when the depth of the p-type doped region 224 is too shallow, its performance in raising the turn-on voltage is insufficient. Preferably, the depth of the p-type doped region 224 is not greater than the second One-half of the thickness of the gallium nitride polycrystalline film 223 . the

Referring to FIG. 5 , a dielectric layer forming step 34 is performed to form a dielectric layer 23 on the semiconductor polycrystalline layer 22 . the

Then a source/drain deposition step 35 is performed to form a source 241 and a drain 242 on the semiconductor polycrystalline layer 22. the

5, in detail, the step 35 is to first form a photoresist layer 100 made of photoresist material on the dielectric layer 23, and the dielectric layer 23 corresponds to the p-type doped The structures on both sides of the impurity region 224 are removed until the surface of the second gallium nitride polycrystalline film 223 is exposed, and then metal 24a is deposited on the exposed semiconductor polycrystalline layer 22, and then the remaining photoresist layer 100 And correspondingly, the metal 24 a deposited on the photoresist layer is removed, and a source 241 and a drain 242 are formed on both sides of the p-type doped region 224 . the

Referring to FIG. 6 , finally a gate deposition step 36 is performed to form a gate 243 on the dielectric layer 23 . the

In detail, step 36 is to form a photoresist layer 200 on the surface of the dielectric layer 23 and the source electrode 241 and drain electrode 242, and then use the photolithography method to correspond the photoresist layer 200 to the p-type doped region 224 is removed until the dielectric layer 23 is exposed, and then metal 24a is deposited on the exposed dielectric layer 23, and finally the remaining photoresist layer 200 and the metal 24a deposited on the photoresist layer 200 are deposited After removal, a gate 243 is formed on the dielectric layer 23 to complete the fabrication of the GaN transistor 2 . the

In addition, it is worth mentioning that the preferred embodiment of the fabrication method of the gallium nitride transistor of the present invention may further include a plasma treatment step before the ion distribution step 33, first using carbon tetrafluoride (CF4 ) plasma, introducing fluorine ions into the AlGaN polycrystalline film 222 through the opening 226 , which can further increase the current output of the GaN transistor 2 and increase the turn-on voltage of the GaN transistor 2 . the

To sum up, the present invention uses ion distribution to directly form a p-type doped region in the GaN polycrystalline film with n-type characteristics to obtain a p-n junction, and the built-in through the p-n junction Voltage, increase the threshold voltage of the gallium nitride transistor so that it can operate in the enhancement mode, the process is simple and easy to control, unlike the general need to use an additional p-type polycrystalline layer to form a p-n junction, so there will be no The problem of polycrystalline junction defects occurs; it will not cause damage to the surface of the component due to the use of etching and digging process, increase the defect density, or cannot be adjusted to a higher level by plasma treatment At the same time, the present invention is supplemented with a dielectric layer made of high dielectric constant material to further increase the critical voltage and reduce the leakage current of the transistor, which helps to reduce the power consumption of the component during standby and reduce the component Applied to the complexity of the circuit, an enhanced gallium nitride transistor more suitable for next-generation high-performance high-voltage driving and control circuit systems can be obtained, so the purpose of the present invention can indeed be achieved. the

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but as long as they do not depart from the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention. the

Claims (3)

1. a manufacture method for gallium nitride transistor, is characterized in that: comprise

One preparation process, prepare a light-emitting component, this light-emitting component has a substrate, and one is formed on the substrate, multichip semiconductor crystal layer containing n type gallium nitride based semiconductor material, this multichip semiconductor crystal layer has the one first gallium nitride polycrystalline film, the aluminium gallium nitride alloy polycrystalline film that are sequentially upwards formed by this substrate, and one second gallium nitride polycrystalline film;

One opening forming step, prior to this multichip semiconductor crystal layer surface formed one be made up of insulating material first cover layer, and one be formed at this first hide clad surface second cover layer, and this second covers layer and defines one and make this first opening covering layer segment surface exposure;

One plasma treatment step makes fluorine ion enter in this aluminium gallium nitride alloy polycrystalline film via this opening in plasma treatment mode;

One ion implantation step, in ion implantation mode, from being somebody's turn to do, Open Side Down carries out P type ion implantation to this second gallium nitride polycrystalline film, the doped region that a degree of depth is not more than 1/2nd of this second gallium nitride polycrystalline film thickness is formed downwards in this second gallium nitride polycrystalline film, cover layer by this first and second afterwards to remove, this multichip semiconductor crystal layer is exposed;

One dielectric layer forming step, deposits the dielectric layer that one deck is made up of high dielectric constant material on this multichip semiconductor crystal layer;

One source/drain deposition step, in lithography mode by this dielectric layer to the structure of both sides, doped region should removing to this multichip semiconductor crystal layer and expose, then in the multichip semiconductor crystal layer plated metal that this exposes, one source pole and a drain electrode is formed in these both sides, doped region; And

One gate deposition step, the predetermined surface plated metal in this dielectric layer forms a grid, can complete the making of this gallium nitride transistor.

2. the manufacture method of gallium nitride transistor as claimed in claim 1, is characterized in that: described first covers layer is selected from silicon dioxide, silicon nitride, and thickness is between 50-150nm.

3. the manufacture method of gallium nitride transistor as claimed in claim 1, is characterized in that: described dielectric layer is selected from Al ₂o ₃, HfO ₂, La ₂o ₃, CeO ₂, HfAlO, TiO ₂, ZrO ₂for material.