CN102567778B - Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates - Google Patents
Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates Download PDFInfo
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Abstract
The invention discloses a radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates. The coding circuit comprises a counter unit, a coding mode selecting circuit, a coding state machine, a coding output control circuit and a byte coding control circuit, wherein the counter unit is used for receiving a system coding clock signal and outputting a counting signal to the coding mode selecting circuit; the coding mode selecting circuit is respectively connected with a double-speed selecting signal, a single and double subcarrier selecting signal and a rate selecting signal and used for outputting a counting signal for distinguishing multiple coding modes to the coding state machine; the coding state machine is used for receiving bit information from the byte coding control circuit and outputting a control signal to the coding output control circuit; and the coding output control circuit is connected with an analog front end of an RFID tag chip. The multiple coding modes are supported by the coding circuit, so that the area of the chip is reduced, the power consumption of a system is reduced, and the circuit is simple in structure, high in stability and convenient to maintain.
Description
Technical field
The present invention relates to REID, especially a kind of RFID label chip coding circuit.
Background technology
REID is RFID, is a kind of non-contacting, the communication technology of recognition target object automatically.In order to realize the reliable data transmission between reader and label chip, different its coding methods of RFID technology is also different, as the chip that meets ISO/IEC 15693 agreements adopts pulse position coding and Manchester's cde, the chip that meets ISO/IEC 14443 agreements adopts Manchester's cde and modified miller coding.The present invention is by the coding circuit for meeting ISO/IEC 15693 agreements.
There are six kinds of coding modes from label chip (VICC) to reader (VCD): single subcarrier high speed, single subcarrier low speed, twin subcarrier high speed, twin subcarrier low speed, the two high speeds of single subcarrier and the two low-speed modes of single subcarrier.Each communication can be selected any coded system, if VICC coding circuit adopts a coding circuit to every kind of pattern, so must 6 coding circuits, and will greatly increase like this area and the power consumption of VICC.
Because single subcarrier and twin subcarrier adopt different frequencies to encode, the former adopts fc/32 at coded data frequency; The latter's coded data frequency adopts fc/32 and two frequencies of fc/28, and this just brings difficulty, general way all to need respectively single subcarrier and twin subcarrier to be encoded for coding, therefore at least needs two independently coding circuits.
Summary of the invention
The technical problem to be solved in the present invention is: the invention provides a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate, this coding circuit can be encoded to multiple different mode.
In order to solve the problems of the technologies described above, the technical solution adopted in the present invention is:
The present invention adopts the design concept of low-power consumption small size, only needs a coding circuit, just can select coding to six kinds of different coding modes.The present invention supports the RFID label chip coding circuit of single twin subcarrier and high low rate, comprise counter unit, coding mode is selected circuit, encoding state machine, coding output control circuit and byte code control circuit, described counter unit receiving system encoded clock signal is also exported count signal and is selected circuit to coding mode, described coding mode is selected circuit to be connected with respectively double speed and is selected signal, single twin subcarrier selects signal and speed to select signal, described coding mode selects circuit to export the count signal that is used for distinguishing Multi-encoding pattern to encoding state machine, described encoding state machine also receives from the bit information of byte code control circuit and exports control signal to coding output control circuit, described coding output control circuit is connected with the AFE (analog front end) of RFID label chip.
Be further used as preferred embodiment, described counter unit comprises the first counter and the second counter, clock signal of system is connected with the input end of the first counter and the second counter respectively with rear with coding enable signal phase, the reset terminal of described first, second counter is also connected with the counter reset signal from encoding state machine, and the count signal of described first, second counter output is transferred to respectively the input end of described coding mode selection circuit.
Be further used as preferred embodiment, described coding output control circuit input end is connected with respectively system clock the first fractional frequency signal, system clock the second fractional frequency signal, coding enable signal and single twin subcarrier and selects signal, and control end receives the control signal from the output of encoding state machine.
Be further used as preferred embodiment, described coding output control circuit comprises one or three input nand gates, system clock the first fractional frequency signal, coding enable signal and single twin subcarrier select signal to be connected with a MUX through described three input nand gates, another input end of described MUX is connected with one or two input nand gates, described two input nand gate Yi road signals are from system clock the second fractional frequency signal, another Lu Weidan twin subcarrier select after signal negate with coding enable signal phase or after the signal that obtains, the input signal of the selection control end of described MUX is the control signal from the output of encoding state machine.
Be further used as preferred embodiment, described byte code control circuit adopts position coding, receives from the subcarrier count signal of encoding state machine and exports postamble output control signal to encoding state machine.
Be further used as preferred embodiment, described encoding state machine is exported control signal switching state according to count signal and the described postamble of the described difference Multi-encoding pattern of selecting circuit from coding mode.
Be further used as preferred embodiment, the state of described encoding state machine comprises frame head state, data mode and postamble state, and the switching of described frame head state is corresponding with the switching head and the tail of postamble state.
Be further used as preferred embodiment, described coding mode selection circuit is supported Multi-encoding pattern-coding, comprises single subcarrier high speed, single subcarrier low speed, the two high speeds of single subcarrier, the two low speed of single subcarrier, twin subcarrier high speed, twin subcarrier low speed.
The invention has the beneficial effects as follows: RFID label chip coding circuit of the present invention adopts coding mode to select circuit to realize the selection coding to Multi-encoding pattern, save chip area, reduced system power dissipation, and realized the multi-mode switching of frame head in coding circuit, data and postamble by an encoding state machine, circuit structure is simple, stability is high and be convenient to maintenance.
Brief description of the drawings
Below in conjunction with accompanying drawing, the specific embodiment of the present invention is described further:
Fig. 1 is the functional-block diagram of RFID label chip coding circuit embodiment of the present invention;
Fig. 2 is the physical circuit schematic diagram of output control circuit embodiment of encoding in coding circuit of the present invention;
Fig. 3 is the state transition graph of encoding state machine embodiment in coding circuit of the present invention.
Embodiment
The invention provides a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate, this coding circuit can carry out to six kinds of coded systems the coding of frame format, and coding result is exported to chip analog front.
With reference to Fig. 1, coding circuit of the present invention comprises counter unit 1, coding mode is selected circuit 2, encoding state machine 3, coding output control circuit 5 and byte code control circuit 4, counter unit 1 receiving system encoded clock signal clk_encoder also exports count signal cnt28, cnt32 selects circuit 2 to coding mode, described coding mode is selected circuit 2 to be connected with respectively double speed and is selected signal fast_inv_read, single twin subcarrier selects signal sub_carrier_flag and speed to select signal data_rate_flag, described coding mode selects circuit 2 to export the count signal that is used for distinguishing Multi-encoding pattern to encoding state machine 3, described encoding state machine 3 also receives from the bit information cnt_bit of byte code control circuit 4 and exports control signal dou_r to coding output control circuit 5, described coding output control circuit 5 is connected with the AFE (analog front end) of RFID label chip and outupt coded signal dout.
Further, described counter unit 1 comprises the first counter 11 and the second counter 12, system coding clock signal clk_encoder be clock signal of system clk with coding enable signal tx_en through with door I10 phase and after output.In the time that coding enable signal tx_en is low level, I10 is output as low level with door, and at this moment system coding clock signal clk_encoder is invalid, and this gated clock can not work coding circuit in the time not encoding request, can reduce the power consumption of chip.System coding clock signal clk_encoder, as the work clock of the first counter 11 and the second counter 12, is connected to the input end of clock of the first counter 11 and the second counter 12.Coding enable signal tx_en is connected to the input end that enables of the first counter 11 and the second counter 12, in the time that coding enables, makes its work, in the time not encoding request, closes counter.The reset signal of the first counter 11 and the second counter 12 is cnt_clr, in the time there is state transition in encoding state machine 3, encoding state machine 3 enables cnt_clr signal, and the first counter 11 and the second counter 12 are resetted, thereby can utilize these two counters again to count at next state.
Before introducing coding mode selection circuit 2, first introduce six kinds of coding modes that the present invention mentions:
Concerning single subcarrier fast mode, its frame head (SOF) comprises three parts: non-modulation times 56.64 μ s, frequency are that 24 pulses, the logical one of fc/32 (423.75kHz) starts with non-modulation times 18.88 μ s, are then that frequency is 8 pulses of fc/32 (423.75kHz).
Concerning single subcarrier low-speed mode, three parts of its frame head (SOF) are respectively 4 times of single subcarrier fast mode time, the non-modulation time of Part I is 226.56 μ s, Part II is 96 pulses, it is the non-modulation time of 75.52 μ s that Part III logical one starts, and is then 32 pulses.
The time of single subcarrier double speed mode SOF be separately the high low-speed mode time 1/2nd.
The frame head (SOF) of twin subcarrier fast mode also comprises three parts: 24 pulses, 9 pulses of logical one taking frequency as fc/28 that 27 pulses, the frequency that frequency is fc/28 is fc/32 start, and is then that frequency is 8 pulses of fc/32.The time of three parts of twin subcarrier low-speed mode SOF is 4 times of twin subcarrier fast mode, then be that frequency is 32 pulses of fc/32 respectively: 96 pulses, 36 pulses of logical one taking frequency as fc/28 that 108 pulses, the frequency that frequency is fc/28 is fc/32 start.
The postamble (EOF) of above-mentioned six kinds of patterns is to be that head and the tail are corresponding with frame head (SOF) separately, and the Part I of their SOF is that the Part III of EOF, the Part III of SOF are the Part I of EOF.
VICC adopts position coding to the data encoding of VCD.Concerning single subcarrier pattern, taking frequency as fc/32,8 (fast mode) or 32 (low-speed mode) pulses of (about 423.75kHz) start logical zero, are then non-modulating time 256/fc(fast modes) or 1024/fc(low-speed mode).It is 4 (two fast modes) or 16 pulses that (two low-speed mode) frequency is fc/32 that the logical zero of single subcarrier double speed mode starts, and is then the two low-speed modes of non-modulating time 128/fc (two fast mode) or 512/fc().To twin subcarrier, logical zero 8 (fast mode) or 32 (low-speed mode) pulses taking frequency as fc/32 start, and are then that frequency is 9 (fast mode) or 36 (low-speed mode) pulses of fc/28.The logical zero of logical one and each self mode is corresponding, and the Part I of logical zero is the Part II of logical one, and its Part II is the Part I of logical one.
Described coding mode selects output SOF_12_NUM, SOF_34_NUM, DATA_01, CNT_NUM, CNT_DATA, the cnt of circuit 2 to connect the input end of encoding state machine, and these output signals are all the message count signals for distinguishing various coding modes.Wherein, SOF_12_NUM is for distinguishing single twin subcarrier frame head the first, the subcarrier count value of the high low-speed mode of Part II, and SOF_34_NUM is the subcarrier count value for selecting the high low-speed mode of single twin subcarrier frame head Part III.DATA_01 is the count value for selecting single twin subcarrier data encoding speed.CNT_NUM, CNT_DATA are for the count value of the waveform that aligns.Cnt is used for the count value of the types of subcarrier of selecting various coding modes, can be cnt32 or cnt28.Selecting signal fast_inv_read when double speed is that high level and single twin subcarrier signal sub_carrier_flag are while being low level, if when speed selects signal data_rate_flag to be " 1 ", select the two fast modes of single subcarrier, SOF_12_NUM value is that 12, SOF_34_NUM value is 4; If when speed selects signal data_rate_flag to be " 0 ", select single secondary double wave low-speed mode that carries, SOF_12_NUM value is that 48, SOF_34_NUM value is 16.In the time that double speed selects signal fast_inv_read and single twin subcarrier signal sub_carrier_flag to be all low level, if when speed selects signal data_rate_flag to be high level, select single subcarrier fast mode, SOF_12_NUM value is that 24, SOF_34_NUM value is 8; If when speed selects signal data_rate_flag to be low level, select single subcarrier low-speed mode, SOF_12_NUM value is that 96, SOF_34_NUM value is 32.Selecting signal fast_inv_read when double speed is that low level and single twin subcarrier are while selecting signal sub_carrier_flag to be high level, if when speed selects signal data_rate_flag to be high level, select twin subcarrier fast mode, SOF_12_NUM value is that 27, SOF_34_NUM value is 9; If when speed selects signal data_rate_flag to be low level, select twin subcarrier low-speed mode, SOF_12_NUM value is that 108, SOF_34_NUM value is 36.
Described encoding state machine 3 input ends connect the output terminal of coding mode selection circuit 2.Encoding state machine 3 is output as control signal dout_r, counter reset signal cnt_clr, frame end-of-encode signal tx_over, byte code end signal tx_empty, subcarrier count signal fs_num.At each state of encoding state machine 3, in the time that cnt count down to 7, subcarrier count signal fs_num adds 1.With reference to Fig. 3, when encoding state machine 3 is during in SOF_1 state, whether the value that judges subcarrier count signal fs_num is SOF_12_NUM, if subcarrier count signal fs_num value is SOF_12_NUM, (this signal is postamble output control signal to postamble output control signal eof_start, be after data encoding completes, this signal is set to high level, postamble EOF starts output) while being CNT_NUM for the value of low level and cnt, state machine jumps to SOF_2 state, otherwise just always in SOF_1 state, until condition meets.When encoding state signal encoder_state value is SOF_2, be that encoding state machine 3 is in the time of SOF_2 state, judge whether subcarrier count signal fs_num is SOF_12_NUM, whether cnt is CNT_NUM, if condition meets, and eof_start is low level, state transition is to SOF_3, otherwise wait is always until condition is satisfied.When in SOF_3 state, judge whether subcarrier count signal fs_num is SFO_34_NUM, and whether cnt is CNT_NUM, if condition meets and eof_start is that low level state jumps to SOF_4.At SOF_4 state, start to load coded data tx_data.When encoding state machine 3 is during in data encoding state, data bit information is exported to dout_r, as the control signal of coding output control circuit 5.When encoding state machine 3 is during in data encoding state DATA_1, judge whether subcarrier count signal fs_num is DATA_01, and whether cnt is CNT_DATA, if meet, jump to data encoding state DATA_2.At data encoding state DATA_2, judge whether the data bit information cnt_bit that byte code control circuit 4 is exported is 7, if 7 represent that the data encoding of a byte completes, send byte code end signal tx_empty, notice sends next byte code data, in the next clock period, byte code control circuit 4 judges whether data loading signal tx_load is high level, if high level is received code data, if low, send postamble output control signal eof_start to encoding state machine 3, represent that frame data have encoded, encoding state machine turns to SOF_4, start to send postamble EOF information.Postamble EOF is just in time contrary with the data of frame head SOF, as previously mentioned, the Part I of SOF is that the Part III of EOF, the Part III of SOF are the Part I of EOF, therefore encoding state machine 3 frame head SOF and postamble EOF state switch just in time head and the tail correspondence, thereby have saved power consumption and the chip area of system.When state encoding machine 3 executes by backward after the state conversion of postamble EOF, proceed to OVER state, represent frame end-of-encode, send frame end-of-encode signal tx_over, further proceed to IDLE state and wait for next frame data encoding.
With reference to Fig. 2, described coding output control circuit 5 input ends are connected with respectively system clock the first fractional frequency signal clk28, system clock the second fractional frequency signal clk32, coding enable signal tx_en and single twin subcarrier and select signal sub_carrier_flag, and control end receives the control signal dou_r exporting from encoding state machine 3.Described coding output is controlled electricity 5 and is comprised one or three input nand gate I1, system clock the first fractional frequency signal clk28, coding enable signal tx_en and single twin subcarrier select signal sub_carrier_flag to be connected with a MUX through described three input nand gate I1, another input end of described MUX is connected with one or two input nand gate I4, described two input nand gate I4 mono-road signals are from system clock the second fractional frequency signal clk32, another Lu Weidan twin subcarrier select after signal sub_carrier_flag negate with coding enable signal tx_en phase or after the signal that obtains, the input signal of the selection control end of described MUX is the control signal dou_r exporting from encoding state machine 3.The output signal of MUX is output as coded data dout after phase inverter I5.In the time that single twin subcarrier selects signal sub_carrier_flag to be low level, when control signal dout_r is low level, coding output dout does not have modulation intelligence; When control signal dout_r is high level, coding output dout output system clock the second fractional frequency signal clk32.In the time that single twin subcarrier selects signal sub_carrier_flag to be high level, when control signal dout_r is high level, coding output dout output system clock the second fractional frequency signal clk32; In the time that control signal dout_r is low level, coding output dout is system clock the first fractional frequency signal clk28.
Byte code control circuit of the present invention 4 adopts position coding, receives from the subcarrier count signal fs_num of encoding state machine 3 and exports postamble output control signal eof_start to encoding state machine 3.Described encoding state machine 3 is according to the count signal of the described difference Multi-encoding pattern from coding mode output circuit 2 and described postamble output control signal eof_start switching state.
Multi-encoding pattern-coding is supported in coding circuit support of the present invention, comprises single subcarrier high speed, single subcarrier low speed, the two high speeds of single subcarrier, the two low speed of single subcarrier, twin subcarrier high speed, twin subcarrier low speed.The first counter cnt28 quits work under single subcarrier pattern, the first counter cnt28 and the second counter cnt32 time-sharing work under twin subcarrier pattern, save the coding power consumption of system, and frame head SOF of the present invention and postamble EOF realize under the different conditions job order of same encoding state machine, head and the tail are corresponding, saved the area of chip.
More than that better enforcement of the present invention is illustrated, but the invention is not limited to described embodiment, those of ordinary skill in the art can also make all equivalent variations or replacement under the prerequisite without prejudice to spirit of the present invention, and the distortion that these are equal to or replacement are all included in the application's claim limited range.
Claims (7)
1. support the RFID label chip coding circuit of single twin subcarrier and high low rate for one kind, comprise counter unit (1), coding mode is selected circuit (2), encoding state machine (3), coding output control circuit (5) and byte code control circuit (4), described counter unit (1) receiving system encoded clock signal (clk_encoder) is also exported count signal (cnt28, cnt32) select circuit (2) to coding mode, it is characterized in that: described coding mode is selected circuit (2) to be connected with respectively double speed and selected signal (fast_inv_read), single twin subcarrier selects signal (sub_carrier_flag) and speed to select signal (data_rate_flag), described coding mode selects circuit (2) to export the count signal that is used for distinguishing Multi-encoding pattern to encoding state machine (3), described encoding state machine (3) also receives from the bit information (cnt_bit) of byte code control circuit (4) and exports control signal (dou_r) to coding output control circuit (5), described coding output control circuit (5) is connected with the AFE (analog front end) of RFID label chip, described coding mode selects circuit (2) to support Multi-encoding pattern-coding, comprise that single subcarrier at a high speed, single subcarrier low speed, single subcarrier is at a high speed two, the two low speed of single subcarrier, twin subcarrier at a high speed, twin subcarrier low speed.
2. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 1, it is characterized in that: described counter unit (1) comprises the first counter (11) and the second counter (12), clock signal of system (clk) is connected with the input end of the first counter (11) and the second counter (12) respectively with rear with coding enable signal (tx_en), described first, the second counter (11, 12) reset terminal is also connected with from the counter reset signal of encoding state machine (3) (cnt_clr), described first, count signal (the cnt28 of the second counter output, cnt32) be transferred to respectively described coding mode and select the input end of circuit (2).
3. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 1, it is characterized in that: described coding output control circuit (5) input end is connected with respectively system clock the first fractional frequency signal (clk28), system clock the second fractional frequency signal (clk32), coding enable signal (tx_en) and single twin subcarrier and selects signal (sub_carrier_flag), and control end receives the control signal (dou_r) from encoding state machine (3) output.
4. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 3, it is characterized in that: described coding output control circuit (5) comprises one or three input nand gates (I1), system clock the first fractional frequency signal (clk28), coding enable signal (tx_en) and single twin subcarrier select signal (sub_carrier_flag) to be connected with a MUX through described three input nand gates (I1), another input end of described MUX is connected with one or two input nand gates (I4), described two input nand gates (I4) Yi road signal is from system clock the second fractional frequency signal (clk32), another Lu Weidan twin subcarrier select after signal (sub_carrier_flag) negate with coding enable signal (tx_en) mutually or after the signal that obtains, the input signal of the selection control end of described MUX is the control signal (dou_r) from encoding state machine (3) output.
5. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 1, it is characterized in that: described byte code control circuit (4) adopts position coding, receive from the subcarrier count signal (fs_num) of encoding state machine (3) and export postamble output control signal (eof_start) to encoding state machine (3).
6. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 5, is characterized in that: described encoding state machine (3) is exported control signal (eof_start) switching state according to count signal and the described postamble of the described difference Multi-encoding pattern of selecting circuit (2) from coding mode.
7. a kind of RFID label chip coding circuit of supporting single twin subcarrier and high low rate according to claim 6, it is characterized in that: the state of described encoding state machine (3) comprises frame head state, data mode and postamble state, the switching of described frame head state is corresponding with the switching head and the tail of postamble state.
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| CN201110450409.XA CN102567778B (en) | 2011-12-29 | 2011-12-29 | Radio frequency identification (RFID) tag chip coding circuit for supporting single and double subcarriers and high and low rates |
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| CN103647558A (en) * | 2013-12-03 | 2014-03-19 | 北京中电华大电子设计有限责任公司 | Manchester encoder circuit |
| EP3121755B1 (en) * | 2015-07-21 | 2019-03-13 | STMicroelectronics International N.V. | Radio-frequency identification transponder and method for data transmission by means of radio-frequency identification technology |
| CN113837342B (en) * | 2021-11-26 | 2022-04-26 | 广州智慧城市发展研究院 | Encoding method, device, equipment and storage medium of electronic tag |
| CN114386553B (en) * | 2022-01-10 | 2024-05-24 | 中国电子科技集团公司第五十四研究所 | Reverse link coding method of ultrahigh frequency RFID tag |
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| CN1788293A (en) * | 2003-06-05 | 2006-06-14 | 摩托罗拉公司 | Subcarrier in an organic RFID semiconductor |
| CN101299644A (en) * | 2008-06-13 | 2008-11-05 | 深圳市远望谷信息技术股份有限公司 | Antenna channel detection method based on six-port circuit |
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| EP2195880A4 (en) * | 2007-09-24 | 2013-02-13 | Cooper Tire & Rubber Co | Automatic antenna tuner system for rfid |
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| CN1788293A (en) * | 2003-06-05 | 2006-06-14 | 摩托罗拉公司 | Subcarrier in an organic RFID semiconductor |
| CN101299644A (en) * | 2008-06-13 | 2008-11-05 | 深圳市远望谷信息技术股份有限公司 | Antenna channel detection method based on six-port circuit |
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Inventor after: Wang Deming Inventor after: Li Jing Inventor after: Zhang Jun Inventor after: Ding Yi Inventor after: Hu Jianguo Inventor before: Wang Deming Inventor before: Li Jing Inventor before: Zhang Jun Inventor before: Ding Yi Inventor before: Hu Jianguo Inventor before: Tan Hongzhou |
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| TR01 | Transfer of patent right |
Effective date of registration: 20170704 Address after: 510000, No. 1399, Baiyun Avenue, Baiyun District, Guangdong, Guangzhou Patentee after: GUANGZHOU NANLING AUTOMOBILE CO.,LTD. Address before: 510800 Guangdong province Guangzhou City Huadu District days Road 88 block A No. 6 Patentee before: Guangzhou Sysur Microelectronics, Inc. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20141022 |