CN102567556A - Verifying method and verifying device for debugging-oriented processor - Google Patents
Verifying method and verifying device for debugging-oriented processor Download PDFInfo
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- CN102567556A CN102567556A CN201010607233XA CN201010607233A CN102567556A CN 102567556 A CN102567556 A CN 102567556A CN 201010607233X A CN201010607233X A CN 201010607233XA CN 201010607233 A CN201010607233 A CN 201010607233A CN 102567556 A CN102567556 A CN 102567556A
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Abstract
The invention relates to a verifying method and a verifying device for a debugging-oriented processor, wherein a streamline technology is adopted in the processor. The verifying method for the debugging-oriented processor comprises the following steps: capturing feature information which is generated when an instruction passes through each level of the streamline of the processor, wherein the feature information is capable of representing the function executing situation of each level of the streamline; simulating the feature information which is generated when the instruction passes through each level of the streamline of the processor, according to an expected model of the processor; and comparing the captured feature information with the simulated feature information, if the two are different, reporting an error and an error reason.
Description
Technical field
The present invention relates to processor checking field, particularly a kind of processor verification method and Authentication devices towards debugging.
Background technology
Along with the development of processor pipeline technology, the raising of processor complexity, the checking of processor become maximum link consuming time in the processor design gradually, and the time that is used to verify can account for more than 70% of processor design cycle.How to improve the efficient of checking, shortening proving period is a great challenge.
In the processor checking of prior art; When finding that mistake is then debugged; Because wrong can only instruction the last stage-promptly the afterbody at processor pipeline embodies; The wrong place of discovery so the checking personnel have no alternative but to comply-be the location of mistakes forward step by step of streamline afterbody, this causes the debug process mechanicalness very high, and the length that expends time in.In addition, The Application of Technology such as out of order execution of the superscale difficulty of more having aggravated processor debugging work.
Therefore, need a kind of processor verification environment of robotization to replace checking personnel machinery and checking work consuming time, make it possible to be positioned at fast the mistake that occurs in the proof procedure, find error reason and assist the checking personnel to correct mistakes.
Summary of the invention
In order to address the above problem, the invention provides towards the processor verification method and the Authentication devices of debugging, wherein said processor adopting pipelining.
According to an aspect of the present invention; A kind of processor verification method towards debugging is provided; Comprise: grasp the characteristic information of instruction through being produced during each grade in the streamline of processor, wherein said characteristic information can characterize the function executing situation of each grade of streamline; According to the expection model of processor, simulate the characteristic information of said instruction through producing during each grade in the processor pipeline; And the characteristic information that is grasped and the characteristic information of being simulated compared, if take place inconsistently, then quote mistake and error reason.
In an embodiment of said method, also comprise: for numbering is set in the instruction that gets into processor, said numbering gets into processor pipeline along with instruction and preserves in each level of streamline; Wherein when grasping characteristic information, grasp numbering; And wherein said simulation and comparison step all are directed against with the corresponding instruction of said numbering and carry out.
According to a further aspect in the invention; A kind of processor Authentication devices towards debugging is provided; Comprise: grabbing device; The characteristic information that is produced when being used for grasping each grade of streamline through processor of instruction, wherein said characteristic information can characterize the function executing situation of each grade of streamline; Analogue means is used for the expection model according to processor, simulates the characteristic information of said instruction through producing during each grade in the processor pipeline; Comparison means is used for the characteristic information that is grasped and the characteristic information of being simulated are compared, if take place inconsistently, then quotes mistake and error reason.
In an embodiment of said method, also comprise: numbering device, be used to the instruction that gets into processor numbering is set, said numbering gets into processor pipeline along with instruction and preserves in each level of streamline; Wherein said grabbing device grasps numbering when grasping characteristic information; And wherein said analogue means and said comparison means all are directed against with the corresponding instruction of said numbering and operate.
The present invention has the following advantages.
1, can significantly reduce the processor debugging difficulty.
2, can significantly reduce the processor error debug time.
3, can reduce the processor R&D cycle.
Description of drawings
Fig. 1 illustrates the present invention and can be applicable to example processor wherein.
Fig. 2 illustrates the processor verification method towards debugging according to an embodiment of the invention.
Fig. 3 illustrates the processor verification method towards debugging according to another embodiment of the invention.
Fig. 4 illustrates according to an embodiment of the invention towards the processor Authentication devices of debugging and the processor of being verified.
Fig. 5 illustrates the processor that according to another embodiment of the invention processor Authentication devices and quilt towards debugging are verified.
Embodiment
Before the present invention was described further, the inventor hoped that some notions that this paper is occurred make an explanation.The processor pipeline that the present invention is mentioned; Be meant following technology: the instruction process process of processor is split as the experimental process process; Each subprocess all can be effectively in other subprocess executed in parallel of its special function Duan Shangyu; Thereby accelerated instruction execution speed, entire process device instruction process process is called streamline here, and each subprocess that is wherein comprised is called pipeline stages.
Below in conjunction with accompanying drawing and specific embodiment the present invention is described in further detail.
Fig. 1 illustrates the present invention and can be applicable to example processor wherein.
In Fig. 1, processor 100 adopts pipelinings, and its streamline is divided into Pyatyi, comprises getting finger, deciphering, launch, write back, submit to.
Get finger: i.e. instruction fetch, for example from the instruction fetch of storer (not shown) for execution.
Decoding: being also referred to as decoding, is the instruction that becomes the instruction of being got " translation " desired type, for example operational order, steering order (branch's redirect), access instruction, privileged instruction or the like.
Emission: be about to transmitting instructions to functional part.Instruction is by emission the time; Dissimilar instructions is launched in the different functions parts and operates; Be launched in the fixed point functional part such as the fixed point instruction, floating point instruction is launched in the floating-point feature, and access instruction is launched in the memory access functional part.
Write back: complete result is write back ad-hoc location with specific format.For example if operational order then need be returned operation result, like rd=ra+rb, what when writing back, will return is to write back useful signal and operation result rd; If access instruction, as returning the memory access result, like load rd, imm (rb), what then return is to write back useful signal and memory access rd as a result.If the processor that order is carried out then directly writes back to register file (not having presentation stage).If the processor of out of order execution then need write back to earlier and reset the preface buffer zone, write back to register file in presentation stage.
Submit to: submission needs the processor content of modification.Here " need revise processor content " with write back in " complete result " be identical in the ordinary course of things, except for some instructions, for example control type instruction, the result who writes back not necessarily needs submission.
To those skilled in the art; It should be understood that; The mode of processor pipeline classification given here and the number of pipeline stages only are exemplary; According to needs of different applications; The processor pipeline classification of different modes and the pipeline stages of different numbers are possible, the three class pipeline of for example " getting finger-decoding-execution ", " getting finger-decoding-execution-memory access-write-back " five-stage pipeline, " get finger-decoding-calculating operation and count address-fetch operand-execution command-write operation number " six level production lines or the like.The present invention is equally applicable to so different processor pipeline classification.
Whether processor verification method and the Authentication devices towards debugging according to the present invention depends on following principle: instruct through each grade of streamline the time, can to produce information, can decision instruction make a mistake during through this grade through gathering customizing messages in this information.Such customizing messages is called characteristic information at this, and characteristic information is chosen by the checking personnel as required.Each level can have own corresponding characteristic information, and for example, for the streamline of processor shown in Figure 1, the characteristic information of getting finger is instruction itself, the instruction of promptly being got; The characteristic information of decoding is the instruction type after the translation; The characteristic information of emission is the functional part that transmitting instructions is arrived and the operand of instruction, and the operand of instruction is meant the data that need Attended Operation, such as an addition add rd, ra, the rb operation, ra and rb be need addition when launching two source operands; The characteristic information that writes back is complete instruction results; The characteristic information of submitting to is the processor content that needs modification.
Below describe according to processor verification method and the Authentication devices towards debugging of the present invention to Fig. 2-5.
Fig. 2 illustrates the processor verification method 200 towards debugging according to an embodiment of the invention.
Describe below in conjunction with 100 pairs of these methods 200 of processor.This method starts from step 201, grasps the characteristic information of instruction through being produced during each grade in the streamline of processor.In step 202,, simulate the characteristic information of said instruction through producing during each grade in the processor pipeline according to the expection model of processor.The expection model here is the model that the processor deviser sets up for processor to be verified in advance, is intended to be used to simulate correct comparison information.In step 203, characteristic information that is grasped and the characteristic information of being simulated are compared, then if take place inconsistent; Then quote mistake and error reason; Here error reason refers to processor pipeline which rank of makes a mistake, and for example for processor 100, takes place inconsistent if relatively the time, learn writing back level; Then stop emulation, quote mistake and error reason and be that to write back the result incorrect.
Instruction described above comprises the instruction that needs are submitted to and under the conjecture execution pattern, needs the instruction of branch's cancellation.For the former, it is carried out above each step successively; For the latter, do not compare, the instruction meeting is carried out down always, up to being cancelled.
Than traditional verification method, this method can help the checking personnel to find wrong more specifically place, makes that the checking personnel can be from place more specifically-be that concrete pipeline stages begins debugging, even can debug and directly provide wrong place.
Fig. 3 illustrates the processor verification method 300 towards debugging according to another embodiment of the invention.
Same 100 pairs of these methods 300 of associative processor describe.Said method starts from step 301, and numbering is set in the instruction that be to get into processor, and for example 1000, this numbering can get into streamline along with instruction, preserves in each level of streamline.
Then in step 302, grasp instruction through the characteristic information that produced during each grade in the streamline of processor and grasp numbering simultaneously, for example be 1000 in the numbering of this extracting.
In step 303, according to the expection model of processor, to numbering 1000 corresponding instructions, simulate the characteristic information of said instruction through being produced during each grade in the processor pipeline.The expection model here is the model that the processor deviser sets up for processor in advance, is intended to be used to simulate correct comparison information.
Then in step 304; To the instruction that is encoded to 1000; The characteristic information that is grasped and the characteristic information of being simulated are compared,, then quote mistake and error reason if take place inconsistently; Be similar to method 200, error reason refers to processor pipeline equally which rank of makes a mistake here.
Be similar to method 200, instruction described above comprises the instruction that needs are submitted to and under the conjecture execution pattern, needs the instruction of branch's cancellation.For the former, it is carried out above each step successively; For the latter, do not compare, carry out but leave to instruct, up to being cancelled always.
This method 300 is especially useful for the processor of the out of order execution command of checking.This is because be that numbering has been set in the instruction that gets into processor, and said numbering can be discerned the execution flow process of specific instruction in the processor of out of order execution command, thereby helps to locate fast the mistake that takes place in the out of order execution processor.
Fig. 4 illustrates according to of the present invention towards the processor Authentication devices 400 of debugging and the processor of being verified 100.
Instruction described above comprises the instruction that needs are submitted to and under the conjecture execution pattern, needs the instruction of branch's cancellation.For the former, said apparatus 401-403 carries out corresponding operating to it; For the latter, comparison means 403 does not compare it, but leaves that it is carried out down always, up to being cancelled.
Use this processor Authentication devices 400 can obtain and method 200 similar benefits, repeat no more at this.
Be similar to equipment 400, instruction described above comprises the instruction that needs are submitted to and under the conjecture execution pattern, needs the instruction of branch's cancellation.For the former, said apparatus 501-504 carries out corresponding operating to it; For the latter, comparison means 504 does not compare it, but leaves that it is carried out down always, up to being cancelled.
Use this processor Authentication devices 500 can obtain and method 300 similar benefits, repeat no more at this.
Through the description of the foregoing description, advantage of the present invention is tangible.The present invention can reduce the complexity of processor checking, reduces the processor proving time, and accurately the mistake in the location processor design shortens processor proving period and R&D cycle.
It should be understood that embodiments of the invention can implement by software, hardware or by the combination of software and hardware.With regard to this point, should be noted that any of logic flow among the figure can representation program step or logical circuit, piece and the function of interconnection or the combination of program step and logical circuit, piece and function.
What should explain at last is: above embodiment is the unrestricted technical scheme of the present invention in order to explanation only; Although the present invention is specified with reference to the foregoing description; Those of ordinary skill in the art is to be understood that: still can make amendment or be equal to replacement the present invention; And do not break away from the spirit and scope of the present invention, and accompanying claims is intended to contain these modifications that fall into spirit and scope of the invention or is equal to replacement.
Claims (9)
- One kind towards the debugging processor verification method, wherein said processor adopting pipelining, said method comprises the steps:Grasp the characteristic information of instruction through being produced during each grade in the streamline of processor, wherein said characteristic information can characterize the function executing situation of each grade of streamline;According to the expection model of processor, simulate the characteristic information of said instruction through producing during each grade in the processor pipeline; AndThe characteristic information that is grasped and the characteristic information of being simulated are compared,, then quote mistake and error reason if take place inconsistently.
- 2. the processor verification method towards debugging according to claim 1 also comprises:For numbering is set in the instruction that gets into processor, said numbering gets into processor pipeline along with instruction and preserves in each level of streamline;Wherein when grasping characteristic information, also grasp numbering; And whereinSaid simulation and comparison step all are directed against with the corresponding instruction of said numbering and carry out.
- 3. the processor verification method towards debugging according to claim 1 and 2, wherein, the instruction under the conjecture execution pattern, carrying out branch's cancellation does not compare step.
- 4. the processor verification method towards debugging according to claim 1 and 2, wherein said error reason ranges the position of processor pipeline.
- One kind towards the debugging the processor Authentication devices, wherein said processor adopting pipelining, said equipment comprises:Grabbing device, the characteristic information that is produced when being used for grasping each grade of streamline through processor of instruction, wherein said characteristic information can characterize the function executing situation of each grade of streamline;Analogue means is used for the expection model according to processor, simulates the characteristic information of said instruction through producing during each grade in the processor pipeline;Comparison means is used for the characteristic information that is grasped and the characteristic information of being simulated are compared, if take place inconsistently, then quotes mistake and error reason.
- 6. the processor Authentication devices towards debugging according to claim 5 also comprises:Numbering device is used to the instruction that gets into processor numbering is set, and said numbering gets into processor pipeline along with instruction and preserves in each level of streamline;Wherein said grabbing device grasps numbering when grasping characteristic information; And whereinSaid analogue means and said comparison means all are directed against with the corresponding instruction of said numbering and operate.
- 7. according to claim 5 or 6 described processor Authentication devices towards debugging, wherein said numbering device is meant ream weight sequencing counter.
- 8. according to claim 5 or 6 described processor Authentication devices towards debugging, wherein, for the instruction that under the conjecture execution pattern, need carry out branch's cancellation, said comparison means does not operate on it.
- 9. according to claim 5 or 6 described processor Authentication devices towards debugging, wherein said error reason ranges the position of processor pipeline.
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| CN110515754B (en) * | 2018-05-22 | 2021-01-26 | 深圳云天励飞技术有限公司 | Debugging system and method of neural network processor |
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Application publication date: 20120711 |