CN102546089B - Method and device for implementing cycle redundancy check (CRC) code - Google Patents

Abstract

The present invention relates to a method and device for implementing a cyclic redundancy check (CRC) code. The implementation method includes: preprocessing information codes input in parallel, and obtaining valid data bits; CRC codes obtained from the previous CRC parallel calculation Select the current effective CRC register bit; perform at least one XOR operation on the effective data bit and the current effective CRC register bit to obtain a new CRC code. The present invention achieves the effect of parallel CRC processing of arbitrary bit width information codes through data bit preprocessing and CRC register bit feedback processing, and improves the computing performance of the CRC generation and verification system, and satisfies the high-speed CRC data processing requirements In this way, logic resources are greatly saved, implementation costs are reduced, and flexibility and compatibility are improved.

Description

Method and device for realizing cyclic redundancy check CRC code

technical field

The invention relates to the communication field, in particular to a method and device for realizing a cyclic redundancy check (CRC) code.

Background technique

For reliable transmission in communication systems, people use error control technology, the most commonly used of which is cyclic redundancy check (CyclicRedundancyCheck, CRC).

The CRC principle is based on linear coding theory. The k-bit information code sequence to be transmitted by the sending end will generate an r-bit check code (CRC code) according to certain rules, and attach it to the information code to form a (k+r) bit transmission sequence. The receiving end checks according to the CRC code generation rules to determine whether there is an error in the transmission process.

For example, the k-bit binary information code sequence to be transmitted is D={d[k-1]d[k-2]...d[1]d[0]}, shift the sequence D to the left by r bits, and divide by one (r+1)-bit generator polynomial, get r-bit remainder R={r[r-1]r[r-2]...r[1]r[0]}, use remainder R as sequence D CRC code, generate the sending sequence M={d[k-1]d[k-2]...d[1]d[0]r[r-1]r[r-2]...r[1] r[0]}.

In practical applications, the implementation methods of CRC include serial computing and parallel computing. The serial calculation circuit is composed of a linear feedback shift register and an XOR operation logic. Features: bit by bit calculation, input 1 bit information code per clock cycle. After k clock cycles, the CRC code is obtained. Taking CRC-32 as an example, the serial computing circuit is shown in Figure 1.

A typical parallel computing circuit is composed of XOR operation logic and CRC register feedback circuit. It is characterized by dividing the information code into several data blocks with a length of n (1≤n≤k) bits, and inputting n-bit information codes in each clock cycle. According to the logical relational expression deduced from the change relationship between each linear feedback shift register and the input information code in the serial calculation method, the CRC code of the n-bit information code is calculated each time, by The final CRC code of the entire to-be-sent information code is calculated in clock cycles. The disadvantage is that the calculation width of the CRC calculation circuit is fixed. When it is necessary to support CRC calculation of arbitrary length information codes, n-way CRC parallel calculation logic is required. Figure 2 is a typical CRC parallel computing circuit structure.

However, in the prior art, the CRC serial calculation can only calculate 1-bit information code each time, which is inefficient and cannot meet the requirements of CRC generation and verification processing for high-speed data transmission. Although the CRC parallel calculation speed is fast, the parallel calculation of the prior art corresponds to different logical relations and the bit width n is also different, so the fixed calculation bit width of one CRC parallel calculation logic cannot be applied to CRC parallel calculations of other bit widths . For example, if an n-bit parallel circuit calculates the CRC code of a k-bit information code, the condition must be met: k can be divisible by n, that is (k%n=0). If the divisibility condition is not satisfied, the information code bit width of the last calculation input is (k%n), and the range is (1~n-1), and the n-bit parallel calculation logic circuit cannot calculate the final CRC code. Therefore, to calculate the CRC code of any long information code, n sets of logic circuits with parallel bit widths of (1~n) are required. However, with the continuous improvement of the data transfer rate, the CRC parallel calculation bit width is also increasing. When the calculation bit width n is large, the resource consumption is very large, and the switching control circuit between logic circuits with different calculation bit widths becomes more and more complicated.

Contents of the invention

The main purpose of the present invention is to provide a method and device for realizing a cyclic redundancy check CRC code, aiming at making the process of implementing the check CRC code occupy less resources and improve its performance.

The present invention provides a kind of implementation method of cyclic redundancy check CRC code, comprises the following steps:

According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the parallel input information codes are reshaped to obtain data blocks;

Select valid data bits from the data block according to the maximum parallel computing bit width of the CRC parallel computing circuit or the CRC parallel computing logical relationship corresponding to the parallel computing bit width this time;

Select the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation;

Perform at least one XOR operation on the valid data bits and the current valid CRC register bits to obtain a new CRC code;

The above plastic processing includes:

According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the high bits of the parallel input information code are zero-filled or cleared, and the parallel input information code is shaped into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, where n is the maximum parallel computing bit width, and Vn is the current parallel computing bit width.

Preferably, when the bit width of the parallel input information code is equal to the maximum parallel computing bit width n, the shaping process can also directly transparently transmit the parallel input information code, and the shaped data block is still the input information code.

Preferably, the above-mentioned step of selecting the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation is specifically:

According to the register bit coefficient corresponding to the bit width of this parallel calculation, the current effective CRC register bit is selected from the CRC code obtained by the previous CRC parallel calculation.

Preferably, the above-mentioned valid data bits and the current valid CRC register bits are subjected to at least one XOR operation, and the step of obtaining a new CRC code further includes:

Judging whether the information code input in parallel is the last data input, if so, record the new CRC code as the final CRC code; otherwise return to perform preprocessing on the information code input in parallel, and obtain its valid data bits A step of.

The present invention also provides a device for implementing a cyclic redundancy check (CRC) code, comprising:

The shaping unit is used to perform shaping processing on the information code input in parallel according to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width to obtain a data block;

The selection unit is used to select valid data bits from the data block according to the maximum parallel computing bit width of the CRC parallel computing circuit or according to the CRC parallel computing logic relation corresponding to the parallel computing bit width of this time;

The CRC register feedback selection module is used to select the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation;

An XOR operation module, configured to perform at least one XOR operation on the effective data bits and the current effective CRC register bits to obtain a new CRC code;

The shaping processing performed by the above-mentioned shaping unit is specifically as follows:

According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the high bits of the parallel input information code are zero-filled or cleared, and the parallel input information code is shaped into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, where n is the maximum parallel computing bit width, and Vn is the current parallel computing bit width.

Preferably, when the bit width of the parallel input information code is equal to the maximum parallel calculation bit width of the circuit, the shaping process can also directly transparently transmit the parallel input information code, and the shaped data block is still the input information code.

Preferably, the above-mentioned CRC register feedback selection module is specifically configured to: select the currently effective CRC register bit from the CRC code obtained by the previous CRC parallel calculation according to the register bit coefficient corresponding to the bit width required for this current calculation.

Preferably, the implementation device of the above-mentioned cyclic redundancy check CRC code also includes:

The loop module is used to judge whether the information code input in parallel is the last data input, if so, record the new CRC code as the final CRC code; otherwise return to execute the preprocessing of the information code input in parallel, and Steps to get its valid data bits.

The implementation method and device of the cyclic redundancy check CRC code of the present invention, through data bit preprocessing and CRC register bit feedback processing, achieve the effect of parallel CRC processing of any bit width information code, thereby solving the problem of the prior art string The row circuit can only calculate one bit of information code per clock cycle, while the parallel circuit calculates the problem of fixed bit width, large logic, and complex control. Moreover, the present invention can also improve the computing performance of the CRC generation and verification system, greatly save logic resources, reduce implementation costs, and improve flexibility and compatibility while meeting the requirements of high-speed CRC data processing.

Description of drawings

Fig. 1 is the structural representation of the serial computing circuit of CRC code in the prior art;

Fig. 2 is the structural representation of the typical parallel computing circuit of CRC code in the prior art;

Fig. 3 is a schematic flow chart of an embodiment of an implementation method of a cyclic redundancy check (CRC) code in the present invention;

Fig. 4 is the schematic flow chart of data bit pretreatment in the implementation method of cyclic redundancy check CRC code of the present invention;

Fig. 5 is a schematic flow chart of another embodiment of the implementation method of the cyclic redundancy check CRC code of the present invention;

Fig. 6 is a structural schematic diagram of an embodiment of a device for implementing a cyclic redundancy check (CRC) code in the present invention;

FIG. 7 is a schematic structural diagram of a data bit preprocessing module in an embodiment of a device for implementing a cyclic redundancy check (CRC) code in the present invention;

FIG. 8 is a schematic structural diagram of another embodiment of a device for implementing a cyclic redundancy check (CRC) code according to the present invention.

The realization of the purpose of the present invention, functional characteristics and advantages will be further described in conjunction with the embodiments and with reference to the accompanying drawings.

Detailed ways

The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

The invention provides a method and device for realizing a cyclic redundancy check CRC code, which can support the calculation of the CRC code of an information code with arbitrary calculation bit width.

FIG. 3 is a schematic flowchart of an embodiment of a method for implementing a cyclic redundancy check (CRC) code in the present invention.

The implementation method of the cyclic redundancy check CRC code of the present embodiment comprises the following steps:

Step S10, preprocessing the information code input in parallel, and obtaining its effective data bits;

Step S11, selecting the current effective CRC register bit from the CRC code obtained by the previous CRC parallel calculation;

Step S12 , performing at least one XOR operation on the valid data bits and the current valid CRC register bits to obtain a new CRC code.

The implementation method of the cyclic redundancy check CRC code in this embodiment, through data bit preprocessing and CRC register bit feedback processing, has achieved the effect of parallel CRC processing of arbitrary bit width information codes, thereby solving the problem of prior art serial The circuit can only calculate one bit of information code per clock cycle, while the parallel circuit calculates the problem of fixed bit width, large logic, and complex control. Moreover, the present invention can also improve the computing performance of the CRC generation and verification system, greatly save logic resources, reduce implementation costs, and improve flexibility and compatibility while meeting the requirements of high-speed CRC data processing.

With reference to Fig. 4, above-mentioned step S10 specifically comprises:

Step S101, according to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, perform shaping processing on the information code input in parallel to obtain a data block;

Assuming that the information code sequence is d[k-1:0], and the CRC code of the Vn-bit information code needs to be calculated at this time, then the current input information code is d[Vn-1:0], and d[Vn-1 :0] is shaped into a data block whose bit width is equal to the maximum computing bit width n of the CRC parallel computing circuit. The data block structure is that the low Vn bit is the input information code, and the high (n-Vn) bit is 0, that is, {(n-Vn)’b0, d[Vn-1:0]}.

Step S102, according to the parallel calculation bit width of the CRC parallel calculation circuit or the logical relational expression corresponding to the parallel calculation bit width this time, select valid data from the data block {(n-Vn)'b0, d[Vn-1:0]} bit.

The above shaping processing mainly includes the following two implementation methods:

The first type, if the data input bit width is a variable value, according to this parallel calculation bit width Vn, perform zero padding or clearing operations on the high bits, and reshape the parallel input information code into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, where n is the maximum parallel computing bit width of the circuit, and Vn is the parallel computing bit width of this time; then, according to the data bit coefficient d_dex_n[n-1 corresponding to the maximum computing bit width :0] Select valid data bits from the shaped data block. In the implementation, the selection unit can use the selector to directly select the current effective CRC register bit, or use c_dex_Vn[r-1:0] as the filter coefficient, do the dot multiplication operation with crc[r-1:0], or other methods to finally Selects the currently valid CRC register bit.

The second type, if the data input bit width is equal to the maximum parallel calculation bit width n of the circuit, and the current calculation bit width is Vn, then the input information code can also be directly transparently transmitted without padding or clearing operations, and the reshaped The data block is still the input information code d[n-1:0]; then select valid data bits from the reshaped data block according to the data bit coefficient d_dex_Vn[n-1:0] corresponding to the calculated bit width Vn.

Of course, if the data input bit width is other cases, other methods can also be used to shape the input information code into {(n-Vn)'b0, d[Vn-1:0]} data blocks, and calculate the bit width according to the maximum The corresponding data bit coefficient selects valid data bits. If the input information code is subjected to shaping processing in the transparent transmission mode, effective data bits are selected according to the data bit coefficient corresponding to the current calculated bit width Vn.

The above step S11 is specifically: according to the register bit coefficient c_dex_Vn[r-1:0] corresponding to the bit width Vn of this calculation, from the r-bit CRC code crc[r-1:0] of the CRC calculation result of the last input data Select the currently valid CRC register bits involved in this calculation. In the implementation, the selection unit can use the selector to directly select the current effective CRC register bit, or use c_dex_Vn[r-1:0] as the filter coefficient, do the dot multiplication operation with crc[r-1:0], or other methods to finally Selects the currently valid CRC register bit.

In the above step S12, at least one XOR operation is performed on the valid data bits and the current valid CRC register bits to obtain a new CRC code, and the new CRC code is updated to the CRC register. In this embodiment, the valid data bits and the current effective CRC register bits can be XORed at least once to obtain a new CRC code; or the valid data bits can be firstly XORed at least once to obtain the valid data bits XOR or the result, and then at least one XOR operation is performed on the effective data bit XOR result and the current effective CRC register bit to obtain a new CRC code. The number of XOR operations can be determined according to specific situations, and is not limited here.

Fig. 5 is a schematic flowchart of another embodiment of the method for implementing a cyclic redundancy check (CRC) code according to the present invention.

On the basis of the above-mentioned embodiments, the implementation method of the cyclic redundancy check CRC code in this embodiment also includes after the above-mentioned step S12:

Step S13, judging whether the information code input in parallel is the last data input, if yes, execute step S14; otherwise, return to execute step S10;

Step S14, record the above-mentioned new CRC code as the final CRC code, and end the process.

When it is judged that the information code input in parallel is not the last data input, return to step S10 and perform CRC parallel calculation in a loop until the data input is completed, and then record the obtained CRC code as the final CRC code.

FIG. 6 is a schematic structural diagram of an embodiment of a device for implementing a cyclic redundancy check (CRC) code according to the present invention.

The implementation device of the cyclic redundancy check CRC code in this embodiment includes:

Data bit preprocessing module 10, used to preprocess the information codes input in parallel, and obtain its effective data bits;

The CRC register feedback selection module 11 is used to select the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation;

The XOR operation module 12 is configured to perform at least one XOR operation on the effective data bits and the current effective CRC register bits to obtain a new CRC code.

With reference to Fig. 7, above-mentioned data bit preprocessing module 10 specifically comprises:

The shaping unit 101 is used to perform shaping processing on the information code input in parallel according to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width to obtain a data block;

The selection unit 102 is configured to select valid data bits from the data block according to the maximum calculation bit width of the CRC parallel calculation circuit or the CRC parallel calculation logic relation corresponding to the current parallel calculation bit width.

Suppose, the information code sequence is d[k-1:0], and when the CRC code of the Vn bit information code needs to be calculated, then the current input information code is d[Vn-1:0], and the shaping unit 101 converts d[ Vn-1:0] is shaped into a data block whose bit width is equal to the maximum computing bit width n of the CRC parallel computing circuit. The data block structure is that the low Vn bit is the input information code, and the high (n-Vn) bit is 0, that is, {(n-Vn)’b0, d[Vn-1:0]}. The selection unit 102 then calculates the data bit coefficient d_dex_n[n-1:0] of the CRC parallel calculation logic relation corresponding to the maximum calculation bit width n from the shaped n-bit data block {(n-Vn)'b0, d[Vn -1:0]} to select valid data bits involved in XOR calculation. In another method, if the bit width of the input information code is equal to the maximum parallel computing bit width of the circuit, the input information code is d[n-1:0], and the shaping unit 101 transparently transmits the input information code, that is, the shaped data block is d[ n-1:0]. The selection unit 102 selects valid data from d[n-1:0] to participate in the XOR calculation according to the data bit coefficient d_dex_Vn[n-1:0] of the CRC parallel calculation logic relation corresponding to the current calculation bit width Vn bit.

The shaping processing performed by the shaping unit 101 mainly includes the following two implementation methods:

The first type, if the data input bit width is a variable value, according to this parallel calculation bit width Vn, perform zero padding or clearing operations on the high bits, and reshape the parallel input information code into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, where n is the maximum computing bit width of the CRC parallel computing circuit, and Vn is the parallel computing bit width of this time; then, according to the data bit coefficient d_dex_n corresponding to the maximum computing bit width, it is reshaped Select valid data bits in subsequent data blocks. In the implementation, the selection unit can use the selector to directly select the current effective CRC register bit, or use c_dex_Vn[r-1:0] as the filter coefficient, do the dot multiplication operation with crc[r-1:0], or other methods to finally Selects the currently valid CRC register bit.

The second type, if the data input bit width is equal to the maximum parallel calculation bit width n of the circuit, and the current calculation bit width is Vn, then the input information code does not perform zero padding or zero clearing operations, and is directly transparently transmitted, and the shaped data block It is still the input information code d[n-1:0]; then select valid data bits from the reshaped data block according to the data bit coefficient d_dex_Vn[n-1:0] corresponding to the current calculated bit width Vn.

Of course, if the data input bit width is other cases, other methods can also be used to shape the input information code into {(n-Vn)'b0, d[Vn-1:0]} data blocks, and calculate the bit width according to the maximum The corresponding data bit coefficient selects valid data bits. If the input information code is subjected to shaping processing in the transparent transmission mode, effective data bits are selected according to the data bit coefficient corresponding to the current calculated bit width Vn.

Since the valid data bits participating in the XOR operation when the calculation bit width is n include all valid data bits when the calculation bit width is (1˜n−1). The data bit coefficient when the calculation bit width is Vn (Vn≤n) is the low Vn bit of the data bit coefficient when the calculation bit width is n. That is, d_dex_n[n-1:0]={(n-Vn)'b0,d_dex_Vn[Vn-1:0]}. Therefore, the different values of d_dex_Vn can be obtained from the data bit coefficient d_dex_n corresponding to the maximum calculation bit width according to Vn, then the data bit preprocessing module 10 only needs to save the d_dex_n value during the data processing process, instead of saving all n different data bit coefficients d_dex_Vn, thus saving storage space.

The CRC register feedback selection module 11 can directly select its current effective CRC register bit through the selector, and can also perform dot multiplication operation with crc[r-1:0] by using c_dex_Vn[r-1:0] as the filter coefficient , or other methods to finally select the current effective CRC register bit. In addition, since the calculation bit width n is greater than or equal to the CRC register bit width r, the CRC register bit coefficient c_dex[r-1:0] is equal to the highest r bits of the data bit coefficient d_dex[n-1:0], that is, c_dex[r- 1:0]=d_dex[n-1:n-r]. When the calculation bit width n is smaller than the CRC register bit width r, the CRC register bit coefficient c_dex[r-1:0] is equal to the n-bit data bit coefficient plus (r-n) bit 0, that is, c_dex[r-1:0]={d_dex [n-1:0], (r-n)'b0}. Therefore, the different values of c_dex_Vn can be obtained from the data bit coefficient d_dex_n corresponding to the maximum calculation bit width according to the Vn value, then the CRC register feedback selection module 11 only needs to save the value of d_dex_n during the processing, without saving all n different register bit coefficients c_dex_Vn, Further save storage space.

The XOR operation module 12 can be realized by direct XOR or other XOR logic methods, and performs at least one XOR operation with the above-mentioned effective data bit and the above-mentioned current effective CRC register bit to obtain a new CRC code, and the new CRC code Update to CRC register. In this embodiment, the valid data bits and the current effective CRC register bits can be XORed at least once to obtain a new CRC code; or the valid data bits can be firstly XORed at least once to obtain the valid data bits XOR or the result, and then at least one XOR operation is performed on the effective data bit XOR result and the current effective CRC register bit to obtain a new CRC code. The number of XOR operations can be determined according to specific situations, and is not limited here.

The implementation device of the cyclic redundancy check CRC code in this embodiment, through the processing of the data bit preprocessing module 10 and the CRC register bit feedback selection module 11, can achieve the effect of parallel CRC processing of any bit width information code, thereby solving the problem of The serial circuit in the prior art can only calculate one bit of information code per clock cycle, while the parallel circuit calculates the problem of fixed bit width, large logic and complex control. Moreover, the present invention can also improve the computing performance of the CRC generation and verification system, greatly save logic resources, reduce implementation costs, and improve flexibility and compatibility while meeting the requirements of high-speed CRC data processing.

FIG. 8 is a schematic structural diagram of another embodiment of a device for implementing a cyclic redundancy check (CRC) code according to the present invention.

On the basis of the foregoing embodiments, the implementation device of the cyclic redundancy check CRC code in this embodiment also includes:

Loop module 13, is used for judging whether the information code of described parallel input is last data input, is then described new CRC code is recorded as final CRC code; Otherwise carries out parallel input by data bit preprocessing module 10 The step of preprocessing the information code and obtaining its valid data bits.

When the loop module 13 judges that the above-mentioned parallel input information code is not the last data input, then through the above-mentioned data bit preprocessing module 10, the CRC parallel calculation is performed in a loop, until after the data input ends, the obtained CRC code is recorded as the final CRC code.

The above is only a preferred embodiment of the present invention, and does not limit the scope of its patents. Any equivalent structure or equivalent process transformation made by using the description of the present invention and the contents of the accompanying drawings is directly or indirectly used in other related technical fields. All are included in the scope of patent protection of the present invention in the same way.

Claims (8)

1. an implementation method of cyclic redundancy check CRC code, is characterized in that, comprises the following steps: According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the parallel input information codes are reshaped to obtain data blocks; Select valid data bits from the data block according to the maximum parallel computing bit width of the CRC parallel computing circuit or the CRC parallel computing logical relationship corresponding to the parallel computing bit width this time; Select the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation; Perform at least one XOR operation on the valid data bits and the current valid CRC register bits to obtain a new CRC code; The shaping process includes: According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the high bits of the parallel input information code are zero-filled or cleared, and the parallel input information code is shaped into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, reshape d[Vn-1:0] into a data block whose bit width is equal to the maximum computing bit width n of the CRC parallel computing circuit; where n is the maximum parallel computing bit width, Vn is the bit width of this parallel calculation, (n-Vn)'b0 means that the high (n-Vn) bit is 0, and d[Vn-1:0] means the information code input this time. 2. The method according to claim 1, characterized in that, when the parallel input information code bit width is equal to the maximum parallel computing bit width n, the shaping process can also directly transparently transmit the parallel input information code, then the data after shaping The block is still the input information code. 3. The method according to claim 1, wherein the step of selecting the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation is specifically: According to the register bit coefficient corresponding to the bit width of this parallel calculation, the current effective CRC register bit is selected from the CRC code obtained by the previous CRC parallel calculation. 4. according to the method described in any one in claim 1 to 3, it is characterized in that, described valid data bit and described current valid CRC register bit are carried out at least one XOR operation, after obtaining the step of new CRC code Also includes: Judging whether the information code input in parallel is the last data input, if so, record the new CRC code as the final CRC code; otherwise return to perform preprocessing on the information code input in parallel, and obtain its valid data bits A step of. 5. A realization device of cyclic redundancy check CRC code, is characterized in that, comprises: The shaping unit is used to perform shaping processing on the information code input in parallel according to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width to obtain a data block; The selection unit is used to select valid data bits from the data block according to the maximum parallel computing bit width of the CRC parallel computing circuit or the CRC parallel computing logic relation corresponding to the parallel computing bit width of this time; The CRC register feedback selection module is used to select the current effective CRC register bit from the CRC code obtained by the last CRC parallel calculation; An XOR operation module, configured to perform at least one XOR operation on the effective data bits and the current effective CRC register bits to obtain a new CRC code; The shaping processing performed by the shaping unit is specifically: According to the maximum parallel computing bit width of the CRC parallel computing circuit and the current parallel computing bit width, the high bits of the parallel input information code are zero-filled or cleared, and the parallel input information code is shaped into n-bit {(n-Vn)' b0, d[Vn-1:0]} data block, reshape d[Vn-1:0] into a data block whose bit width is equal to the maximum computing bit width n of the CRC parallel computing circuit; where n is the maximum parallel computing bit width, Vn is the bit width of this parallel calculation, (n-Vn)'b0 means that the high (n-Vn) bit is 0, and d[Vn-1:0] means the information code input this time. 6. The device according to claim 5, wherein when the bit width of the parallel input information code is equal to the maximum parallel computing bit width of the circuit, the shaping process can also directly transparently transmit the parallel input information code, and the shaped data The block is still the input information code. 7. The device according to claim 5, wherein the CRC register feedback selection module is specifically used to: calculate the register bit coefficient corresponding to the bit width according to the needs of this time, and obtain the CRC code obtained from the previous CRC parallel calculation Select the currently valid CRC register bit. 8. The device according to any one of claims 5 to 7, further comprising: The loop module is used to judge whether the information code input in parallel is the last data input, if so, record the new CRC code as the final CRC code; otherwise return to execute the preprocessing of the information code input in parallel, and Steps to get its valid data bits.