CN102546071B - Clock synchronization method and system - Google Patents
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
- H04J3/0661—Clock or time synchronisation among packet nodes using timestamps
- H04J3/0667—Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
- H04J3/0697—Synchronisation in a packet node
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Abstract
An embodiment of the invention provides a clock synchronization method, which includes of acquiring the transmission time T1 of synchronous messages after receiving the synchronous messages; recording the clock count T2 of a local crystal oscillator when the synchronous messages arrive; sending delay correction application messages, recording the clock count T3 of the local crystal oscillator when in sending of the delay correction application messages and starting counting of a synchronous Ethernet clock; receiving the time T4 for main clock equipment to receive the delay correction application messages after receiving delay correction application response messages; computing transmission delay according to the T1, the T2, the T3 and the T4, and computing the main clock equivalence of the T3 according to the T1, the T2, the T3 and the transmission delay; summing the main clock equivalence of the T3 and the current counting value of the synchronous Ethernet clock, and finally regulating clock output according to the summing results. The invention further provides a clock synchronization system. By the clock synchronization method and the clock synchronization system in the technical scheme, complexity of clock synchronization is reduced, convergence rate is increased and cost is saved.
Description
Technical field
The present invention relates to wireless communication technology field, relate in particular to a kind of clock synchronizing method and system of wireless communication system.
Background technology
Clock Synchronization Technology is the basic fundamental of communication system.The object of clock synchronous is that the time of guaranteeing transmitting terminal and receiving terminal acts in agreement, to realize correct, reliable communication.Along with the development of information technology, more and more higher to the requirement of time synchronized.Current most of TDD (Time Division Duplexing, time division duplex) communication technology of pattern, as TD-SCDMA, CDMA2000, WiMAX etc., and the LTE system of researching and developing and disposing, often need the whole network to keep precise time or Phase synchronization between eating dishes without rice or wine, conventionally frequency stability requires within ± 0.05ppm, and phase accuracy is at least within the scope of ± 5 μ s.For realizing clock synchronous, the common practice of prior art is to adopt based on GPS and OCXO (the base station clock extracting mode of OCXO (OvenControlled Crystal Oscillator, constant-temperature crystal oscillator oscillator).Which receives by being arranged on the gps signal receiving system of each base station the clock signal that satellite sends, then in base station side, carry out reaction type regression algorithm, the 1pps signal of the original output of GPS and OCXO outputting base station synchronizing signal are carried out to high frequency phase demodulation, carry out realizing the whole network after statistical filtering synchronous.Yet the base station clock extracting mode based on GPS and OCXO need to set up and safeguard gps antenna and corresponding indoor forwarding unit, base station clock plate adopts high-precision voltage-controlled OCXO, and whole clock synchronous process is complicated, convergence rate is slow, and cost is higher.In addition, because gps signal effect is subject to weather effect larger, in harsh weather situation, easily cause step-out between system base-station, occur higher cutting off rate.
Summary of the invention
Because the problem that the clock synchronizing method of prior art exists, the goal of the invention of the embodiment of the present invention is to provide a kind of new clock synchronizing method and system, with reduce the clock synchronous process of prior art complexity, improve the problem that synchronous convergence rate is slow, workout cost is higher.
The clock synchronizing method that the embodiment of the present invention provides comprises:
Receive the synchronization message that clock equipment sends, resolve synchronization message, obtain the synchronization message transmitting time T1 that synchronization message comprises; The clock count T2 of local crystal oscillator while recording synchronization message arrival;
To clock equipment forward delay interval, proofread and correct solicitation message, the clock count T3 of local crystal oscillator when record sends this application message, and start the counting to synchronous Ethernet clock;
Receive time delay is proofreaied and correct application response message, and resolution response message is obtained the clock equipment that response message comprises and received the time T 4 that solicitation message is proofreaied and correct in time delay;
According to T1, T2, T3 and T4 calculated transmission delay, according to T1, T2, T3 and transmission delay, calculate the master clock equivalence value of T3;
The count value of the master clock equivalence value of T3 and synchronous Ethernet clock is carried out to summation operation, according to summation operation result, adjust clock output.
Preferably, according to T1, T2, T3 and T4 calculated transmission delay, specifically comprise: by T2 and T4 sum, deduct T1 and T3 sum, with subtract each other result divided by 2 to obtain transmission delay; The master clock equivalence value that calculates T3 according to T1, T2, T3 and transmission delay specifically comprises: by T1 and transmission delay sum, add that the difference of T3 and T2 is to obtain the master clock equivalence value of T3.
Preferably, according to the T1 of adjacent twice and T2, calculate frequency deviation, with this frequency deviation, be multiplied by respectively T2 and/or T3 to revise T2 and/or T3, described T1 according to adjacent twice and T2 calculate frequency deviation and specifically comprise: by the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency deviation.
Preferably, when receiving the synchronization message of clock equipment transmission, start timer, when timer reaches Preset Time, to clock equipment forward delay interval, proofread and correct solicitation message.
Further preferably, described Preset Time scope is 2
mto 2
m+1, described M is that clock equipment is proofreaied and correct solicitation message Desired Min Tx Interval according to the time delay of its data disposal ability indication.
The embodiment of the present invention also provides a kind of clock system.This system comprises: the first acquiring unit, the first record cell, the second record cell, clock count unit, second acquisition unit, the first computing unit and adjustment unit, wherein:
Described the first acquiring unit, for after receiving the synchronization message of clock equipment transmission, resolves synchronization message, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Described the first record cell, the clock count T2 of local crystal oscillator while arriving for recording synchronization message;
Described the second record cell, for recording the clock count T3 of local crystal oscillator when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described clock count unit, for starting the counting to synchronous Ethernet clock when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described second acquisition unit, for proofread and correct resolution response message after application response message at receive time delay, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time delay;
Described the first computing unit, for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Described adjustment unit, for exporting according to the master clock equivalence value of T3 and the current count value sum adjustment clock to synchronous Ethernet clock.
Preferably, described the first computing unit deducts T1 and T3 sum by T2 and T4 sum, with subtract each other result divided by 2 to obtain transmission delay; By T1 and transmission delay sum, add that the difference of T3 and T2 is to obtain the master clock equivalence value of T3.
Preferably, described system also comprises the second computing unit and amending unit, and the second computing unit calculates frequency deviation for T1 and the T2 according to adjacent twice; Described amending unit is for frequency deviation being multiplied by respectively to T2 and/or T3 to revise T2 and/or T3, described the second computing unit by the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency deviation.
Preferably, described system also comprises timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, to clock equipment forward delay interval, proofreaies and correct solicitation message.
Preferably, the scope of described Preset Time is 2
mto 2
m+1, described M is that clock equipment is proofreaied and correct solicitation message Desired Min Tx Interval according to the time delay of its data disposal ability indication.
The embodiment of the present invention parses T1, T4 respectively from synchronization message and time delay correction application response message, when arriving, synchronization message records the clock count T2 of local crystal oscillator, when proofreading and correct solicitation message, records forward delay interval the clock count T3 of local crystal oscillator, and start and count when sending solicitation message, by T1, T2, T3 and T4, calculate the master clock equivalence value of T3, according to this equivalence value and synchronous Ethernet clock current count value sum, adjust clock output.Compared with prior art, the embodiment of the present invention obtains after the corresponding time from synchronization message and time delay application response message, in conjunction with local crystal oscillator counting, by simple operation, obtain the master clock equivalence value of T3, then according to the clock count sum of equivalence value and synchronous ethernet, adjust output clock, thereby realized clock synchronous, owing to having avoided loaded down with trivial details calculating, the convergence rate of clock synchronous is accelerated.And the embodiment of the present invention utilizes existing synchronous ethernet that clock is provided, do not need to build in advance a large amount of gps antennas and indoor forwarding unit, do not need crystal oscillator equipment to carry out particular restriction, save the GPS of operator deployment cost, thereby reduced cost.In addition, the embodiment of the present invention is utilized synchronous ethernet and is not adopted GPS, has the place of network can transmit clock, and clock synchronous process is no longer subject to weather effect, has solved in harsh weather situation between system base-station easy step-out, has occurred the problem of high cutting off rate.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the clock synchronous of prior art;
Fig. 2 is the flow chart of an embodiment of the method for the present invention;
Fig. 3 (a) is the flow chart of an example of embodiment described in Fig. 2;
Fig. 3 (b) is the hardware module figure of example described in Fig. 3;
Fig. 4 is the composition frame chart of system embodiment of the present invention.
Embodiment
The embodiment of the present invention provides a kind of new clock synchronizing method and corresponding system, the method and system parse T1 from synchronization message and time delay correction application response message, T4, when arriving, synchronization message records the clock count T2 of local crystal oscillator, when proofreading and correct solicitation message, records forward delay interval the clock count T3 of local crystal oscillator, and start and count when sending solicitation message, pass through T1, T2, T3 and T4 calculate the master clock equivalence value of T3, according to this equivalence value and synchronous Ethernet clock current count value sum, adjust clock output, thereby realized clock synchronous process by simple calculating, owing to having avoided loaded down with trivial details computing, improved the convergence rate of clock synchronous, owing to not adopting GPS and OCXO, do not need to carry out antenna installation and indoor equipment is purchased, reduced cost, clock synchronous process is no longer subject to weather effect.
For ease of understanding technical scheme of the present invention and technical characterictic, below the principle of clock synchronous of first brief prior art, then in conjunction with drawings and Examples of the present invention, the present invention is described in detail.
IEEE-USA (IEEE) started standard synchronous protocol accurate time synchronization protocol (the Precision Time Protocol for commercial measurement and control application in 2000, be called for short PTP agreement, claim again 1588 agreements) develop, for meeting the specific demand of the applications such as commercial measurement and control, as distributed environment, microsecond or submicrosecond precision, without applications such as management.Growing along with from other application synchronisation requirement, IEEE, on the 1588v1 basis of issue in 2002, has developed enhancing characteristic version, and IEEE 1588TM-2008, is called for short 1588v2.1588v2 can meet the demand of various fields to frequency and time synchronized such as comprising measurement and control, industrial automation, military affairs and telecommunication system.1588 networkings adopt master-slave mode topological structure, for the base station in end, conventionally only realize the ordinary clock (ordinary clock) of slave pattern in agreement.
Referring to accompanying drawing 1, the figure shows the principle of clock synchronous.Time synchronization process is mutual by PTP protocol message, slave (from) end calculates transmission delay (Delay) and the time migration (Offset) with respect to master clock, utilize this transmission delay and time migration to revise gradually local clock, finally approach master clock.The system of PTP agreement clock synchronous mechanism comprises a master clock and a plurality of from clock, time synchronized is mainly by the information that comprises the time in transmit leg and recipient is beaten to timestamp, and recipient, according to timestamp, calculates the time deviation of master clock and time delay that temporal information is transmitted in network realizes.PTP protocol definition four kinds of type of messages, comprise Sync (synchronization message), FollowUp (following message), DelayReq (time delay correction solicitation message) and DelayResp (time delay adjustment application response message).The difference of master-salve clock mainly consists of at the transmission delay Delay of network clock jitter Offset and packets of information.PTP agreement clock synchronous mechanism is mainly divided into two stages, offset correction and time delay calibration phase.
In the offset correction stage, i.e. in the A stage in figure, first by master clock, at T1, constantly send Sync message to from clock, in Sync message, comprise a timestamp, the scheduled time that data are sent has been described.What comprise due to synchronization message is to estimate to send the time rather than truly to send the time, and the Sync message time of sending really sends after measured in FollowUp message subsequently.From clock one side, record the real time of reception T2 of Sync message, by T1 and T2, can calculate the time deviation T_ms:T_ms=T2-T1 with respect to master clock from clock.Can be proofreaied and correct from clock by this time deviation, but the result of calculating thus includes temporal information, in network, transmit the time delay causing, therefore also need to carry out time delay correction.
At time delay calibration phase, i.e. B stage in figure.First by sending DelayReq information from clock to master clock, from clock log, send time T 3, master clock is recorded the correct time T4 of reception, and this time is turned back to from clock by DelayResp, from clock, by these two Time Calculation, goes out network delay T_sm=T4-T3.Obtain thus offset=(T_ms-T_sm)/2, Delay=(T_ms+T_sm)/2.After calculating offset and Delay, can revise accordingly local clock time.
As described in aforementioned, for realizing clock synchronous, prior art is carried out clock synchronous based on above-mentioned principle by GPS and OCXO, and this mode exists shortcomings.For this reason, the embodiment of the present invention provides a kind of clock synchronizing method.Referring to accompanying drawing 2, the figure shows the flow chart of one embodiment of the present of invention, the clock synchronizing method of the present embodiment comprises:
Step S201: receive the synchronization message that clock equipment sends, resolve synchronization message, obtain the synchronization message transmitting time T1 that this synchronization message comprises; The clock count T2 of local crystal oscillator while recording synchronization message arrival;
For realizing clock synchronous, clock equipment can regularly or periodically send synchronization message, includes the transmitting time T1 that clock equipment sends this synchronization message in synchronization message, and this T1 is the standard time.Base station side receives after synchronization message, and synchronization message is resolved, and obtains the T1 that synchronization message comprises.When base station side receives synchronization message, (when synchronization message reaches) records the clock count T2 of local crystal oscillator, and this T2 is from clock time, with respect to master clock, has skew.Here it should be noted that: clock equipment no matter, or from clockwork, all by clock pulse is counted to get to the time, T1, T2 exist with the form of clock pulse quantitative value.
Step S202: to clock equipment forward delay interval, proofread and correct solicitation message, the clock count T3 of local crystal oscillator when record sends this application message, and start the counting to synchronous Ethernet clock;
Base station receives after synchronization message, to proofread and correct solicitation message to clock equipment forward delay interval, here it should be noted that forward delay interval proofreaies and correct solicitation message and can carry out in any moment after receiving synchronization message, but in practical application, the time delay existing in order to reserve relevant device itself, the present invention preferably sets a timer, and when the Preset Time of timer arrives, just forward delay interval is proofreaied and correct solicitation message.When sending this application message, need to carry out record to local crystal oscillator clock counting T3, and start the counting to synchronous Ethernet clock.Here start and can be undertaken by the mode of interrupting ethernet clock counting, when sending time delay correction solicitation message, produce an interruption, by this interrupt notification, carry out clock count.
Step S203: receive time delay is proofreaied and correct application response message, resolves and obtains the clock equipment that this response message comprises and receive the time T 4 that solicitation message is proofreaied and correct in time delay;
Base station side is proofreaied and correct after solicitation message to clock equipment forward delay interval, clock equipment will be proofreaied and correct application response message to base station side return time delay, this response message comprises the time T 4 that clock equipment receives time delay adjustment application, and base station side therefrom parses this time T 4 after obtaining response message.
Step S204: according to T1, T2, T3 and T4 calculated transmission delay, calculate the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
After obtaining T1, T2, T3 and T4 according to abovementioned steps, can be according to these four amount calculated transmission delay delay, the mode of concrete calculated transmission delay is a lot, it between different modes, is only the difference in operational formula, the embodiment of the present invention preferably deducts T1 and T3 sum by T2 and T4 sum, the result that use is subtracted each other is again divided by 2 to obtain transmission delay delay, and formula is: delay=[(T2+T4)-and (T1+T3)]/2.Obtain transmission delay delay, can be according to calculate the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay, this master clock equivalence value is the standard time of master clock corresponding to the T3 moment, the concrete account form of equivalence value is also a lot, and the present invention preferably calculates according to following formula: T3 standard time=T1+delay+ (T3-T2) constantly.
Step S205: the master clock equivalence value of T3 and synchronous Ethernet clock current count value are carried out to summation operation, adjust clock output according to summation operation result.
In step S202, start the counting to synchronous Ethernet clock, when calculating the master clock equivalence value of T3, can stop the counting to ethernet clock pulse.Then with the master clock equivalence value of T3, add synchronous Ethernet clock current count value, this summed result has reflected the synchronised clock with master clock.Because clock signal is sent by the form of pulse, obtain after above-mentioned summed result, by this result, adjust the outgoing position of pulse, obtain thus precision clock.
The present embodiment parses T1, T4 from synchronization message and time delay adjustment application response message, when arriving, synchronization message records the clock count T2 of local crystal oscillator, when proofreading and correct solicitation message, records forward delay interval the clock count T3 of local crystal oscillator, and start and count when sending solicitation message, by T1, T2, T3 and T4, calculate the master clock equivalence value of T3, according to this equivalence value and synchronous Ethernet clock current count value sum, adjust clock output.Compared with prior art, the present embodiment obtains after the corresponding time from synchronization message and DELAY RESPONSE message, in conjunction with local crystal oscillator counting, by simple operation, can obtain the master clock equivalence value of T3, then according to the clock count sum of equivalence value and synchronous ethernet, adjust output clock, thereby realized clock synchronous, owing to having avoided loaded down with trivial details calculating, the convergence rate of clock synchronous is accelerated.And the present embodiment utilizes existing synchronous ethernet that clock is provided, do not need to build in advance a large amount of gps antennas and indoor forwarding unit, adopt common crystals equipment, save the GPS of operator deployment cost, thereby reduced cost.In addition, the present embodiment utilizes synchronous ethernet and does not adopt GPS, has the place of network can transmit clock, and clock synchronous process is no longer subject to weather effect, has solved in harsh weather situation between system base-station easy step-out, has occurred the problem of high cutting off rate.
In above-described embodiment, T2, T3 are by the clock count of local crystal oscillator is recorded and obtained, in practical application, because local crystal oscillator exists frequency difference conventionally and between synchronous ethernet recovered clock, more accurate in order to obtain synchronised clock result, need to compensate T2, T3, the mode of compensation is first to calculate frequency deviation, utilizes this frequency deviation to revise as adjusting the former T2 of factor pair, T3.Frequency deviation calculates according to following formula:
coeff_freq＝(T1
cur-T1
prev)/(T2
cur-T2
prev)
In formula: coeff_freq is frequency deviation, T1
cur, T2
curfor the current T1 obtaining and T2, T1
prev, T2
prevfor T1 and the T2 last time obtaining.Calculate and with this coefficient, be multiplied by respectively T2 after frequency deviation and T3 can realize the correction to T2, T3.It should be noted that: normal conditions should all be revised T2 and T3, but only to wherein any one is adjusted and does not also hinder goal of the invention of the present invention.
Above-described embodiment calculates after frequency deviation coeff_freq and transmission delay delay, can be directly used in and calculate T3 master clock equivalence value constantly, but in actual applications, the present invention preferably carries out filtering processing to above-mentioned two amounts, so that level and smooth exceptional value, the temperature drift of compensation crystal oscillator.
The synchronization message that above-described embodiment sends in reception clock equipment and forward delay interval are proofreaied and correct between solicitation message does not have limiting time interval, and even now does not hinder the realization of goal of the invention of the present invention.But, in actual application, in view of the problem of implementation of base station-side hardware and the data-handling capacity of clock equipment, more difficultly accomplish after receiving synchronization message to send solicitation message at once, conventionally the two exists and postpones, even if phase sequence seamless connection before and after two operations, also may not be more accurate for the calculating of synchronised clock.Therefore, the present invention preferably sets a timer, and this timer starts when receiving the synchronization message of clock equipment transmission, and when the Preset Time of timer arrives, base station side is proofreaied and correct solicitation message to clock equipment forward delay interval.The Preset Time here can rule of thumb be set, and also can set according to the indication of clock equipment.Clock equipment is according to the data-handling capacity of self, to sending Desired Min Tx Interval delay_req_interval (M) from clock, the DELAY RESPONSE message delay_resp that this delay_req_interval value sends by clock equipment arrives from clockwork, from clockwork, according to this transmission interval, send adjustment when the next transmission delay solicitation message, the Preset Time of timer is arranged on to 2
delay_req_intervalto 2
delay_req_interval+1within scope.
In order to be illustrated more clearly in Delay Synchronization method of the present invention, with an instantiation, describe below.Referring to accompanying drawing 3 and Fig. 4, Fig. 3 shows the flow chart of this example, and Fig. 4 shows the hardware module structure chart of this example.The clock synchronous process of this example specifically comprises:
Step S301: initialization PHY and PTP protocol process module.PHY refers to physical layer, and the bottom of OSI refers to the chip with external signal interface here.
Step S302:PHY extracts synchronised clock from synchronous ethernet, and by PLL module (PhaseLocked Loop, phase-locked loop), the Ethernet synchronised clock of extraction is outputed to FPGA.
Whether step S303:PHY detects synchronization message Sync and arrives.
Step S304: if Sync message detected, the clock count T2 by PHY, local crystal oscillator being produced is inserted into the extended field of Sync message packet, the message that is equipped with T2 timestamp is submitted to the PTP protocol process module of CPU; When Sync message being detected, start timer.CUP is the functional unit that moves PTP agreement, PTP agreement is processed, and this unit comprises a plurality of functional layers, and PTP protocol process module is a submodule in CPU.
Step S305:PTP protocol process module parses T1 and the laggard row cache of T2, and calculates t_ms and frequency deviation coeff_freq, utilizes frequency deviation correction T2.T_ms represents that master clock arrives the time delay from clock, t_ms=T2-T1: frequency deviation coeff_freq=(T1
cur-T1
prev)/(T2
cur-T2
prev), the result after T2 is multiplied by frequency deviation is as new T2 buffer memory.
Step S306: whether the Preset Time that judges timer arrives, if arrived, performs step S307;
Step S307:PHY calls the call back function forward delay interval correction solicitation message delay_req that is registered to network driver; When sending delay_req message, PHY produces interrupt notification FPGA, by FPGA, synchronous Ethernet clock is counted.
After step S308:delay_req message is sent completely, the clock count producing from local crystal oscillator by call back function obtains the transmitting time T3 that sends delay_req message, and T3 is delivered to PTP protocol process module.
Step S309:PHY detects after the time delay calibration response message delay_resp message of master clock, passes to PTP protocol process module, by this module, parses the time T 4 that master clock receives delay_req message from response message;
Step S310:PTP protocol process module calculates t_sm according to T3 and T4, utilizes t_ms, t_sm to calculate propagation delay time delay and T3 master clock equivalence value corresponding to the moment.T_sm represents the time delay from clock to master clock, t_sm=T4-T3; T3 master clock equivalence value=T1+delay+ (T3-T2) constantly.In this step, also can proofread and correct T3.
Step S311: the T3 calculating master clock equivalence value is constantly configured to FPGA, to FPGA is setup time: T1+ (T3-T2) * coeff_freq+Delay;
Step S312: stop FGPA counting, record t_fpga now, the T3 equivalence value that is configured to FGPA is added to this count value t_fpga, the result after addition is as the benchmark of 1pps output time.
Describe embodiment of the method for the present invention above in detail, correspondingly, the present invention also provides a kind of system of clock synchronous.Referring to accompanying drawing 4, native system embodiment 400 comprises: the first acquiring unit 401, the first record cell 402, the second record cell 403, clock count unit 404, second acquisition unit 405, the first computing unit 406 and adjustment unit 407, wherein:
Described the first acquiring unit 401, for resolving synchronization message after the synchronization message receiving clock equipment transmission, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Described the first record cell 402, the clock count T2 of local crystal oscillator while arriving for recording synchronization message;
Described the second record cell 403, for recording the clock count T3 of local crystal oscillator when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described clock count unit 404, for starting the counting to synchronous Ethernet clock when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described second acquisition unit 405, for proofread and correct resolution response message after application response message at receive time delay, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time delay;
Described the first computing unit 406, for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Described adjustment unit 407, for adjusting clock output according to the summation of the master clock equivalence value of T3 and synchronous Ethernet clock current count value.
The course of work of native system embodiment is: the synchronization message transmitting time T1 that this synchronization message comprises is resolved and obtained to the first acquiring unit 401 after the synchronization message that receives clock equipment transmission; The clock count T2 of local crystal oscillator when the first record cell 402 records synchronization message arrival; Then when proofreading and correct solicitation message to clock equipment forward delay interval, by the second record cell 403, recorded the clock count T3 of local crystal oscillator, and trigger the counting that clock count unit 404 starts synchronous Ethernet clock; At receive time delay, proofread and correct after application response message, by second acquisition unit 405, resolve and obtain the clock equipment that this response message comprises and receive the time T 4 that solicitation message is proofreaied and correct in time delay; Next, the first computing unit 406, according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay; Adjustment unit 407 is adjusted clock output according to the summation of the master clock equivalence value of T3 and synchronous Ethernet clock current count value.
Native system embodiment parses T1, T4 from synchronization message and time delay adjustment application response message, when arriving, synchronization message records the clock count T2 of local crystal oscillator, when proofreading and correct solicitation message, records forward delay interval the clock count T3 of local crystal oscillator, and start and count when sending solicitation message, by T1, T2, T3 and T4, calculate the master clock equivalence value of T3, according to this equivalence value and synchronous Ethernet clock current count value sum, adjust clock output.Compared with prior art, native system embodiment obtains after the corresponding time from synchronization message and DELAY RESPONSE message, in conjunction with local crystal oscillator counting, by simple operation, can obtain the master clock equivalence value of T3, then according to the clock count sum of equivalence value and synchronous ethernet, adjust output clock, thereby realized clock synchronous, owing to having avoided loaded down with trivial details calculating, the convergence rate of clock synchronous is accelerated.And the present embodiment utilizes existing synchronous ethernet that clock is provided, do not need to build in advance a large amount of gps antennas and indoor forwarding unit, adopt common crystals equipment, save the GPS of operator deployment cost, thereby reduced cost.In addition, the present embodiment utilizes synchronous ethernet and does not adopt GPS, has the place of network can transmit clock, and clock synchronous process is no longer subject to weather effect, has solved in harsh weather situation between system base-station easy step-out, has occurred the problem of high cutting off rate.
The first computing unit of said system embodiment can calculate in the following manner: by T2 and T4 sum, deduct T1 and T3 sum, with subtract each other result divided by 2 to obtain transmission delay; By T1 and transmission delay sum, deduct the difference of T3 and T2 to obtain the master clock equivalence value of T3.
Said system embodiment can also comprise the second computing unit and amending unit, and the second computing unit calculates frequency deviation for T1 and the T2 according to adjacent twice; Described amending unit is for frequency deviation being multiplied by respectively to T2 and/or T3 to revise T2 and/or T3, described the second computing unit by the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency deviation.By these two unit, can realize the correction to T2, T3, the frequency difference between compensation synchronous ethernet recovered clock and local crystal oscillator, is conducive to realize more accurately clock synchronous.
Said system embodiment can also comprise timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, to clock equipment forward delay interval, proofreaies and correct solicitation message.The general span of Preset Time is herein 2
mto 2
m+1, described M is that clock equipment is proofreaied and correct solicitation message Desired Min Tx Interval according to the time delay of its data disposal ability indication.By this timer, can regulate the interval receiving between synchronization message and forward delay interval correction solicitation message, meet the needs of practical application.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of doing, be equal to replacement, improvement etc., within all should being included in the protection range of invention.
Claims (8)
1. a clock synchronizing method, is characterized in that, the method comprises:
Receive the synchronization message that clock equipment sends, resolve synchronization message, obtain the synchronization message transmitting time T1 that synchronization message comprises; The clock count T2 of local crystal oscillator while recording synchronization message arrival;
To clock equipment forward delay interval, proofread and correct solicitation message, the clock count T3 of local crystal oscillator when record sends this application message, and start the counting to synchronous Ethernet clock;
Reception delay is proofreaied and correct application response message, and resolution response message is obtained the clock equipment that response message comprises and received the time T 4 that solicitation message is proofreaied and correct in time delay;
According to T1, T2, T3 and T4 calculated transmission delay, according to T1, T2, T3 and transmission delay, calculate the master clock equivalence value of T3;
By the master clock equivalence value of T3 with the current count value of synchronous Ethernet clock is carried out to summation operation, according to summation operation result, adjust clock output;
Describedly according to T1, T2, T3 and T4 calculated transmission delay, specifically comprise: by T2 and T4 sum, deduct T1 and T3 sum, with subtract each other result divided by 2 to obtain transmission delay; The described master clock equivalence value according to T1, T2, T3 and transmission delay calculating T3 specifically comprises: by T1 and transmission delay sum, add that the difference of T3 and T2 is to obtain the master clock equivalence value of T3.
2. method according to claim 1, it is characterized in that, according to the T1 of adjacent twice and T2, calculate frequency deviation, with this frequency deviation, be multiplied by respectively T2 and/or T3 to revise T2 and/or T3, described T1 according to adjacent twice and T2 calculate frequency deviation and specifically comprise: by the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency deviation.
3. according to the method described in any one in claim 1 to 2, it is characterized in that, when receiving the synchronization message that clock equipment sends, start timer, when timer reaches Preset Time, to clock equipment forward delay interval, proofread and correct solicitation message.
4. method according to claim 3, is characterized in that, described Preset Time scope is 2
mto 2
m+1, described M is that clock equipment is proofreaied and correct solicitation message Desired Min Tx Interval according to the time delay of its data disposal ability indication.
5. a clock system, is characterized in that, this system comprises: the first acquiring unit, the first record cell, the second record cell, clock count unit, second acquisition unit, the first computing unit and adjustment unit, wherein:
Described the first acquiring unit, for resolving synchronization message after the synchronization message receiving clock equipment transmission, obtains the synchronization message transmitting time T1 that synchronization message comprises;
Described the first record cell, the clock count T2 of local crystal oscillator while arriving for recording synchronization message;
Described the second record cell, for recording the clock count T3 of local crystal oscillator when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described clock count unit, for starting the counting to synchronous Ethernet clock when clock equipment forward delay interval is proofreaied and correct solicitation message;
Described second acquisition unit, for proofread and correct resolution response message after application response message at receive time delay, obtains the clock equipment that response message comprises and receives the time T 4 that solicitation message is proofreaied and correct in time delay;
Described the first computing unit, for according to T1, T2, T3 and T4 calculated transmission delay, calculates the master clock equivalence value of T3 according to T1, T2, T3 and transmission delay;
Described adjustment unit, for exporting according to the master clock equivalence value of T3 and the current count value sum adjustment clock to synchronous Ethernet clock;
Described the first computing unit deducts T1 and T3 sum by T2 and T4 sum, with subtract each other result divided by 2 to obtain transmission delay; By T1 and transmission delay sum, add that the difference of T3 and T2 is to obtain the master clock equivalence value of T3.
6. system according to claim 5, is characterized in that, described system also comprises the second computing unit and amending unit, and the second computing unit calculates frequency deviation for T1 and the T2 according to adjacent twice; Described amending unit is for frequency deviation being multiplied by respectively to T2 and/or T3 to revise T2 and/or T3, described the second computing unit by the difference of adjacent twice T1 divided by the difference of adjacent twice T2 with acquisition frequency deviation.
7. according to the system described in any one in claim 5 to 6, it is characterized in that, described system also comprises timer, and this timer starts when receiving the synchronization message of clock equipment transmission, when timer reaches Preset Time, to clock equipment forward delay interval, proofreaies and correct solicitation message.
8. system according to claim 7, is characterized in that, the scope of described Preset Time is 2
mto 2
m+1, described M is that clock equipment is proofreaied and correct solicitation message Desired Min Tx Interval according to the time delay of its data disposal ability indication.
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