CN102544103B - InP inversion n ditch field effect transistor and preparation method thereof - Google Patents
InP inversion n ditch field effect transistor and preparation method thereof Download PDFInfo
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- CN102544103B CN102544103B CN201210005872.8A CN201210005872A CN102544103B CN 102544103 B CN102544103 B CN 102544103B CN 201210005872 A CN201210005872 A CN 201210005872A CN 102544103 B CN102544103 B CN 102544103B
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- inp
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000002353 field-effect transistor method Methods 0.000 title 1
- 230000005669 field effect Effects 0.000 claims abstract description 10
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 11
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- JLTRXTDYQLMHGR-UHFFFAOYSA-N trimethylaluminium Chemical compound C[Al](C)C JLTRXTDYQLMHGR-UHFFFAOYSA-N 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 5
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- NLXLAEXVIDQMFP-UHFFFAOYSA-N Ammonium chloride Substances [NH4+].[Cl-] NLXLAEXVIDQMFP-UHFFFAOYSA-N 0.000 claims description 3
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims description 3
- 230000004913 activation Effects 0.000 claims description 3
- 235000011114 ammonium hydroxide Nutrition 0.000 claims description 3
- 238000000137 annealing Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 238000000313 electron-beam-induced deposition Methods 0.000 claims description 3
- 238000005987 sulfurization reaction Methods 0.000 claims description 3
- 238000007865 diluting Methods 0.000 claims description 2
- 238000002161 passivation Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 12
- 230000005284 excitation Effects 0.000 abstract description 3
- 238000004377 microelectronic Methods 0.000 abstract description 2
- 229920006395 saturated elastomer Polymers 0.000 abstract description 2
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- 238000000231 atomic layer deposition Methods 0.000 description 9
- 238000012360 testing method Methods 0.000 description 6
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- 238000005516 engineering process Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 238000011160 research Methods 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
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- 230000000694 effects Effects 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 241000220317 Rosa Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
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- 239000012895 dilution Substances 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
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- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 230000005527 interface trap Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
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Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention belongs to the technical field of micro-electronics, and particularly relates to an InP inversion n ditch field effect transistor and a preparation method thereof. The nMOSFET (metal-oxide-semiconductor field-effect transistor) mainly comprises an InP semi-conductor substrate with the surface lattice direction being (111) A, a high-dielectric constant gate medium and a metal gate source leak electrode. The nMOSFET structure shows excellent current characteristics. Simultaneously, under the scanning excitation of continuous direct current voltage, the saturated current performance of a device is stable and reliable, and the current drift value is nearly zero. According to the nMOSFET structure, the current drift problem on an InPMOSFET device for a long time is solved. The invention also further provides an integration and preparation method of the nMOSFET structure.
Description
Technical field
The invention belongs to microelectronics technology, be specifically related to a kind of InP transoid n channel field-effect pipe (
nMOSFET) and preparation method thereof.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device based on Si has approached its physics limit along with Moore's Law is scaled.If the further size of reduction of device, can there is current tunnelling phenomenon in thin gate dielectric layer, the high level to being difficult to accept, and device cannot normally be worked.For the performance of further boost device, must adopt the new semi-conducting material with high mobility to replace traditional Si channel layer.III-V semi-conducting material, as GaAs, In
xga
1-xas, InP, InAs etc., pay close attention to because higher electronic transmission performance has caused widely.III-V material has the drift velocity under higher electron mobility and low electric field, makes the III-V device can be at a high speed and the work of low-power consumption.
In numerous III-V semi-conducting materials, InP is a kind of compound semiconductor materials that is widely used in electronics, photoelectron and optics.Its energy gap is 1.34 eV, than the In of rich In
xga
1-xas's is wide.Than GaAs, research thinks less on InP surface and occurs fermi level pinning effect and the saturated rate of displacement of electronics of its material is larger simultaneously---2.5 × 10
7cm/s.
In former research report, the general research to InP MOSFET, is mainly at InP(100) be prepared from the substrate of crystal orientation.No matter gate medium is the Al of chemical vapor deposition (CVD)
2o
3or the SiO of thermal oxidation
2, InP(100) MOSFETs at room temperature after 1000 s leakage current drift all reached more than 90%, seriously affected the normal work of device.It has been generally acknowledged that this serious current drift characteristic is by InP(100) a large amount of bound trap and gate medium oxide and InP(100 in native oxide) interface trap between semiconductor causes.Therefore, if adopt a kind of InP substrate of less boundary defect, can realize the gate dielectric material of the high-k (high-k) of grow a kind of high-quality, thermal stability simultaneously thereon, by suitable semiconductor surface processing method, improve the interfacial characteristics between high-k and InP, thereby obtain having the InP base MOSFET device of excellent electrology characteristic.So, in following high speed logic circuit, InP will be a kind of very important transistor channel material.
Summary of the invention
The object of the present invention is to provide the outstanding InP transoid n channel field-effect pipe of a kind of current capability (
nMOSFET) and preparation method thereof.
InP transoid n channel field-effect pipe provided by the invention, adopts the InP in (111) A crystal orientation as Semiconductor substrate, and the mixture film of metal Ni/Ge/Au, as grid leak source electrode, adopts the Al of the high-k of atomic layer deposition technology (ALD) growth
2o
3film, as gate dielectric material, is then made InP transoid nMOSFET.Adopt the InP in (111) A crystal orientation as Semiconductor substrate, itself and Al
2o
3obviously level and smooth than (100) crystal orientation of the interface of gate medium, and device electrical testing shows InP(111) there are larger electron mobility and larger leakage current on A surface.Particularly under direct voltage continuous sweep excitation, the saturation current of InP transoid nMOSFET show be close to 100% stability---current drift is almost " zero ".
The present invention propose with ALD Al
2o
3for the InP(111 of gate medium) preparation method of A nMOSFET, concrete steps are as follows:
(1) first with the HCl solution I nP(111 diluting) A disk 5 ~ 10 min, to remove surperficial native oxide;
(2), when temperature is 150 ~ 300 ° of C, using trimethyl aluminium (TMA) and the pulse predecessor replacing of water to combine, at InP(111) deposit a layer thickness is the Al of 20 ~ 50 nm on A substrate
2o
3as surface coating;
(3) see through Al
2o
3cover layer, uses Si ion selectivity to inject formation source, drain region;
(4) temperature be in the nitrogen of 700 ~ 800 ° of C through 15 ~ 30 s quick thermal annealing process, the ion that activation of source, drain region are injected;
(5) remove cover layer Al with buffer oxide layer lithographic method
2o
3;
(6) in sulfuration ammonia solution, soak 5 ~ 10 minutes, form the passivation layer of layer of surface containing S;
(7) be under the condition of 150 ~ 300 ° of C in temperature, use trimethyl aluminium (Al (CH
3)
3, TMA) and the pulse predecessor the replacing combination of water, then be the Al of 3 ~ 10 nm with ALD growth thickness
2o
3gate dielectric layer;
(8) sample upper step being made 30 ~ 120 s that anneal in 500 ~ 900 ° of C nitrogen chambeies;
(9) mixture of electron beam deposition Ni/Ge/Au is as the Metal Contact of source, drain region;
(10) under being the condition of 300 ~ 400 ° of C, temperature uses nitrogen rapid thermal annealing 30 ~ 60 s again;
(11) with forming gate metal after electron beam depositing Ti/Au and Liftoff technique, make InP nMOSFET device.
InP (111) A nMOSFET device is carried out to Electrical.
The present invention has the following advantages:
1, the upper atomic layer deposition Al that adopts of the InP in (111) A crystal orientation
2o
3can greatly improve its interface quality and grid oxygen quality as gate dielectric material.
2, under direct voltage continuous sweep excitation, saturation current show be close to 100% stability---current drift is almost nil.These characteristics have very large using value in metal-oxide-semiconductor field effect transistor field.
Brief description of the drawings
Fig. 1 InP n of the present invention channel mosfet device architecture schematic diagram.
Fig. 2 InP Grown of the present invention Al
2o
3transmission electron microscope micrograph after dielectric layer.
The electric current output characteristic of Fig. 3 InP n of the present invention channel mosfet device.
The current drift characteristic of Fig. 4 InP n of the present invention channel mosfet device.
Embodiment
Below with reference to accompanying drawing, embodiments of the present invention are described.In description below, identical Reference numeral represents identical assembly, and it is repeated in this description omission.
Fig. 1 InP n of the present invention channel MOS field effect transistor device architecture schematic diagram.First, utilize HCl solution and the (NH of dilution
4)
2s solution carries out surface treatment, removes InP(111) native oxide on A disk 101 surfaces.Disk is inserted immediately in the reaction cavity of ASM F-120 ALD.When temperature is 300 ° of C, use trimethyl aluminium (Al (CH
3)
3, TMA) and the thick Al of the pulse predecessor replacing combination deposit one deck 30 nm of water
2o
3as surface coating.See through Al
2o
3cover layer, using Si ion selectivity injection formation source, drain region 102(energy is 30 KeV, concentration 1 × 10
14cm
-2with energy be 80 KeV, concentration 1 × 10
14cm
-2).Subsequently in the nitrogen of 750 ° of C through 15 s rapid thermal annealing (RTA) techniques, so that the ion that activation of source, drain region inject.With buffer oxide layer (BOE) lithographic method removal cover layer Al
2o
3, then in sulfuration ammonia solution, soak 10 minutes, more again insert the thick Al of 8 nm that grows in ALD reaction chamber
2o
3, i.e. 103 parts in figure.Then, cross after PDA annealing 1min at 500 ° of C nitrogen chamber back warps, the mixture of electron beam deposition Ni/Ge/Au is as the Metal Contact 104 of source, drain region.Finally, in the time of 400 ° of C, use nitrogen RTA 30 s that anneal.With forming gate metal 105 after electron beam depositing Ti/Au and liftoff technique.From 0.40 μ m to 40 μ m not etc., grid width is 100 μ m to the nMOSFETs grid length of processing.
Al
2o
3/ InP(100) and Al
2o
3/ InP(111) A interface transmission microscopy (TEM) picture as shown in Figure 2.In figure, 5 nm engineer's scales can be found out ALD Al thus
2o
3thickness be 8 nm.And on oxide layer and semi-conductive interface, do not find any obvious native oxide, prove " self-cleaning (self-cleaning) " effect of the upper ALD technique of InP.Al
2o
3/ InP(111) interface phase of A is to Al
2o
3/ InP(100) interface obviously smoother, and the degree of roughness at interface is one of principal element affecting electron mobility in the surface channel of III-V MOSFETs.
Shown in Fig. 3 at the upper InP counter-rotative type of (100) and (111) A nMOSFET
i ds -
v ds output characteristic curve.Test grid bias (
v gs ) from 0 to 3 V, step-length is 0.5 V.Grid length is 1 μ m, and grid width is 100 μ m.When grid bias (
v gs ), drain bias (
v ds ) while being all 3 V, the upper drain current of (111) A (
i ds ) reach maximum 600 μ A/ μ m---be (100) lip-deep 3.5 times under equal conditions.In the document of reporting about transoid InP nMOSFET at present, this current values is record-breaking.
In experiment, use Keithley 4200 test I nP nMOSFETs leakage current drift characteristics as shown in Figure 4.Step signal from
t=0 moment rose and is added to grid as grid bias.Three utmost point settings of source drain-gate publicly.Drain electrode adopts Keithley 4200 that a fixed-bias transistor circuit is set, and the leakage current of real-time testing device (
i ds ).Starting voltage signal stabilization time (
t) be 5 s, the sampling time is set to 0.35 s, and the testing time is 1400 s.Drain bias as shown in Figure 4, under normal temperature,
v ds and grid bias
v gs while being 3 V, InP(100) and InP(111) the drift characteristic curve of the leakage current of the upper nMOSFETs of A.The grid length of two kinds of devices is 8 μ m.Ordinate is with initial leakage current value
i ds (
t=5s) normalized leakage current.In 1400 seconds of test, InP(100) upper leakage current compares initial leakage current value
i ds (
t=5s) declined about 6.9%, surprisingly InP(111 under equal conditions) but find almost nil leakage current drift characteristic on A.Except may be random electrical noise little " the jolting " of causing, InP(111) drift of the upper leakage current of A is almost completely suppressed---and leakage current drift curve keeps straightened condition always.Therefore the result that, the present invention provides tool to have significant practical applications for the CMOS technology of the following non-Si of following 16 nm techniques.
Above-described embodiment is of the present invention giving an example, although disclose for the purpose of illustration most preferred embodiment of the present invention and accompanying drawing, but it will be appreciated by those skilled in the art that: without departing from the spirit and scope of the invention and the appended claims, various replacements, variation and amendment are all possible.Therefore, the present invention should not be limited to most preferred embodiment and the disclosed content of accompanying drawing.
Claims (1)
1. a preparation method for InP transoid n slot field-effect transistor, is characterized in that concrete steps are:
(1) first with the HCl solution diluting and (NH
4)
2s solution-treated InP(111) A disk 5 ~ 10 min, to remove surperficial native oxide;
(2), when temperature is 150 ~ 300 DEG C, using the pulse predecessor the replacing combination of trimethyl aluminium and water, at InP(111) deposit a layer thickness is the Al of 20 ~ 50 nm on A substrate
2o
3as surface coating;
(3) see through Al
2o
3cover layer, uses Si ion selectivity to inject formation source, drain region;
(4) in the nitrogen of 700 ~ 800 DEG C through 15 ~ 30 s quick thermal annealing process, the ion that activation of source, drain region inject;
(5) remove cover layer Al with buffer oxide layer lithographic method
2o
3;
(6) in sulfuration ammonia solution, soak 5 ~ 10 minutes, form the passivation layer of layer of surface containing S;
(7) be under 150 ~ 300 DEG C of conditions in temperature, use the pulse predecessor the replacing combination of trimethyl aluminium and water, then be the Al of 3 ~ 10 nm with ALD growth thickness
2o
3gate dielectric layer;
(8) sample upper step being made 30 ~ 120 s that anneal in 500 ~ 900 DEG C of nitrogen chambeies;
(9) mixture of electron beam deposition Ni/Ge/Au is as the Metal Contact of source, drain region;
(10) under being the condition of 300 ~ 400 DEG C, temperature uses nitrogen rapid thermal annealing 30 ~ 60 s again;
With forming gate metal after electron beam depositing Ti/Au and Liftoff technique, make InP transoid n slot field-effect transistor.
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| CN102544103B true CN102544103B (en) | 2014-09-03 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104143760A (en) * | 2013-05-10 | 2014-11-12 | 长春理工大学 | Surface passivation method in the preparation of InP-based semiconductor lasers by ALD |
| CN106298780A (en) * | 2016-09-27 | 2017-01-04 | 中国科学院微电子研究所 | InP substrate MOSCAP structure and preparation method thereof |
| CN111584359A (en) * | 2020-05-09 | 2020-08-25 | 中国科学院上海技术物理研究所 | A kind of ultrasonic wet etching method based on ALD deposition Al2O3 as mask |
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| CN1762057A (en) * | 2003-03-17 | 2006-04-19 | 皇家飞利浦电子股份有限公司 | Semiconductor device with isolation layer |
| CN101097955A (en) * | 2006-06-29 | 2008-01-02 | 国际商业机器公司 | Semiconductor device and method of forming semiconductor device |
| CN101894793A (en) * | 2009-05-21 | 2010-11-24 | 新加坡格罗方德半导体制造私人有限公司 | Integrated circuit (IC) system and manufacture method thereof with silicon through hole |
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| CN1762057A (en) * | 2003-03-17 | 2006-04-19 | 皇家飞利浦电子股份有限公司 | Semiconductor device with isolation layer |
| CN101097955A (en) * | 2006-06-29 | 2008-01-02 | 国际商业机器公司 | Semiconductor device and method of forming semiconductor device |
| CN101894793A (en) * | 2009-05-21 | 2010-11-24 | 新加坡格罗方德半导体制造私人有限公司 | Integrated circuit (IC) system and manufacture method thereof with silicon through hole |
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