CN102544023A - Flash memory and preparation method for same - Google Patents

Abstract

The present invention provides a flash memory and a preparation method thereof. The flash memory includes: a semiconductor substrate; a storage medium layer, the storage medium layer is formed on the semiconductor substrate, and sequentially includes: tunneling An oxide layer, a silicon nitride layer, a blocking oxide layer; a semiconductor layer, the semiconductor layer is formed on the storage medium layer, including a channel region and source and drain regions on both sides of the channel region; and a gate A stack, formed on the channel region, includes a gate dielectric and a gate formed on the gate dielectric. By forming a storage medium ONO layer between the substrate and the channel region, the interference of the transistor operating region on the charge storage region is reduced, the reliability of the device is increased, and the data storage time of the memory is significantly improved. Moreover, compared with the traditional SONOS flash memory, it has a smaller equivalent oxide layer thickness of the gate dielectric, which is conducive to reducing the size of the device.

Description

A kind of flash memory and preparation method thereof

technical field

The invention relates to the technical field of semiconductor design and manufacture, in particular to a flash memory and a preparation method thereof.

Background technique

Flash memory (Flash Memory) has the characteristics that the stored data will not be lost after power failure, and is especially suitable for the fields of mobile communication and computer storage components.

The SONOS flash memory has a silicon-oxide-nitride-oxide-silicon structure, including a tunnel oxide layer, a silicon nitride layer and a blocking oxide layer. SONOS-type flash memory uses quantum tunneling effect or hot carrier injection effect to inject charges (electrons or holes) into the silicon nitride layer through the tunneling oxide layer, and are captured by charge traps in the silicon nitride layer, thereby It causes the change of the threshold voltage of the memory cell to achieve the effect of data storage. Figure 1 is a cross-sectional view of a typical SONOS memory cell. As shown in FIG. 1, the structure of a typical SONOS memory cell is that the two ends of the substrate 101 are respectively a source 101s and a drain 101d, separated by a tunnel oxide layer 103, and on the tunnel oxide layer 103 Covering the silicon nitride layer 105, the blocking oxide layer 107 and the gate 101g are sequentially formed thereon. Wherein, the ONO region composed of the tunnel oxide layer 103 , the silicon nitride layer 105 and the blocking oxide layer 107 is a charge storage region. Since the charge storage region is located between the gate 101g and the channel region of the transistor operation region, as the size of semiconductor devices further shrinks, the transistor operation region will interfere with the charge storage region, resulting in reduced device reliability and reduced data storage time.

Contents of the invention

The purpose of the present invention is to at least solve one of the above-mentioned technical defects, particularly to provide a novel SONOS type flash memory and its preparation method, to solve the problem that the transistor operation area of the existing SONOS type flash memory interferes with the charge storage area defects, improve device reliability, and increase data storage time.

In order to achieve the above object, the present invention proposes a flash memory on the one hand, which is characterized in that it includes: a semiconductor substrate; a storage medium layer, the storage medium layer is formed on the semiconductor substrate, sequentially from bottom to top Comprising: a tunnel oxide layer, a silicon nitride layer, a blocking oxide layer; a semiconductor layer, the semiconductor layer is formed on the storage medium layer, including a channel region and source regions and drains located on both sides of the channel region region; and a gate stack, formed on the channel region, including a gate dielectric and a gate formed on the gate dielectric.

In one embodiment of the present invention, the semiconductor substrate is an SOI (silicon-on-insulator) substrate, and the entire flash memory is formed on the SOI substrate, which is beneficial to reduce the leakage of the substrate and improve the electrical performance of the device.

In one embodiment of the present invention, the semiconductor layer is a silicon layer. That is, the silicon layer of the SOI substrate, the tunnel oxide layer, the silicon nitride layer, the blocking oxide layer, and the semiconductor layer constitute a SONOS type flash memory, and the storage medium ONO layer (tunneling layer) in the SONOS type flash memory Oxide layer-silicon nitride layer-blocking oxide layer) is formed between the substrate and the channel region, and the threshold voltage of the memory cell is changed by using the lining bias effect.

In one embodiment of the present invention, the silicon layer of the semiconductor substrate or the silicon-on-insulator substrate is heavily doped with the first type, the channel region is lightly doped with the second type, and the source region The drain region and the drain region are heavily doped with the first type, which is beneficial to reduce the series resistance of the back electrode.

In one embodiment of the present invention, sidewalls are formed on the sidewalls of the gate stack.

In one embodiment of the present invention, a passivation layer is formed on the semiconductor substrate, the semiconductor layer and the gate, and the passivation layer has a lead hole penetrating to the semiconductor substrate, the semiconductor layer and the gate .

In one embodiment of the present invention, a lead metal layer is formed on the passivation layer, and the lead metal layer is connected to the semiconductor substrate, the semiconductor layer and the gate through the lead hole.

Another aspect of the present invention also proposes a method for preparing a flash memory, which is characterized in that it includes the following steps: S1: providing a semiconductor substrate, and performing a first type of heavy doping on the semiconductor substrate; S2: sequentially forming a tunnel oxide layer, a silicon nitride layer, and a blocking oxide layer on the semiconductor substrate; S3: forming a semiconductor layer on the blocking oxide layer, and performing light doping of the second type on the semiconductor layer; S4: in A gate stack is formed on the semiconductor layer, the gate stack includes a gate dielectric and a gate formed on the gate dielectric, and the area of the semiconductor layer covered by the gate stack is a channel region; S5: for the exposed The semiconductor layer is heavily doped with the first type to form a source region and a drain region on both sides of the channel region.

In one embodiment of the present invention, the semiconductor substrate is a silicon-on-insulator substrate, and the silicon layer of the silicon-on-insulator substrate is heavily doped with the first type. The entire flash memory is formed on the SOI substrate, which is beneficial to reduce the leakage of the substrate and improve the electrical performance of the device.

In one embodiment of the present invention, after the step S1, it further includes: etching the silicon layer of the silicon-on-insulator substrate to form mutually isolated active regions. That is, in steps S2-S5, a memory cell is formed in an active region, and a plurality of memory cells isolated from each other can be formed in an array on the entire semiconductor substrate.

In one embodiment of the present invention, the semiconductor layer is a silicon layer. That is, the silicon layer of the SOI substrate, the tunnel oxide layer, the silicon nitride layer, the blocking oxide layer, and the semiconductor layer constitute a SONOS flash memory, and the ONO layer (tunnel oxide layer) in the SONOS flash memory -silicon nitride layer-blocking oxide layer) is formed between the substrate and the channel region, and the threshold voltage of the memory cell is changed by the substrate bias effect.

In one embodiment of the present invention, after step S4, the method further includes: forming sidewalls on the sidewalls of the gate stack.

In one embodiment of the present invention, after step S5, the following steps are further included: S6: forming a passivation layer on the semiconductor substrate, the semiconductor layer and the gate, forming a passivation layer in the passivation layer to the semiconductor The wiring hole of the substrate, the semiconductor layer and the gate; S7: forming a wiring metal layer on the passivation layer, and the wiring metal layer is connected to the semiconductor substrate, the semiconductor layer and the grid through the wiring hole .

The invention provides a flash memory and a preparation method thereof. By forming a storage medium ONO layer between a substrate and a channel region, the threshold voltage of the memory unit is changed by using the lining bias effect. Since the charge storage area (ONO layer) is separated from the transistor operation area in space, the interference of the transistor operation area on the charge storage area is reduced, the reliability of the device is increased, and the data storage time of the memory is significantly improved. Moreover, compared with the traditional SONOS flash memory, the flash memory according to the embodiment of the present invention has a smaller equivalent oxide layer thickness of the gate dielectric, which is conducive to reducing the size of the device.

Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Description of drawings

The above and/or additional aspects and advantages of the present invention will become apparent and easy to understand from the following description of the embodiments in conjunction with the accompanying drawings, wherein:

Figure 1 is a cross-sectional view of a typical SONOS memory cell;

FIG. 2 is a schematic structural diagram of a flash memory according to an embodiment of the present invention;

Fig. 3 is a sectional view along AA' direction in Fig. 2;

4-10 are structural schematic diagrams of each step of a method for manufacturing a flash memory according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are described in detail below, examples of which are shown in the drawings, wherein the same or similar reference numerals designate the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the figures are exemplary only for explaining the present invention and should not be construed as limiting the present invention.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", " The orientations or positional relationships indicated by "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying Describes, but does not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and operate in a specific orientation, and therefore should not be construed as limiting the invention.

It should be noted that, in addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. Further, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

FIG. 2 is a schematic structural diagram of a flash memory according to an embodiment of the present invention, and FIG. 3 is a cross-sectional view along the direction AA' in FIG. 2 . It should be noted that the flash memory of the present invention can be applied to both n-type and p-type transistors. For the sake of simplicity, each embodiment of the present invention will only be described by taking an n-type transistor as an example. For a flash memory including a p-type transistor, it can be The doping type can be changed correspondingly with reference to the embodiment of the present invention, which will not be repeated here.

As shown in FIGS. 2-3 , the flash memory includes a semiconductor substrate 100 , a storage medium layer 200 , a semiconductor layer 300 , and a gate stack.

Wherein, the semiconductor substrate 100 may include conventional semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, silicon carbide, indium arsenide, or indium phosphide. In addition, the substrate may optionally include epitaxial layers, which may be altered by stress to enhance its performance, and may also include silicon-on-insulator (SOI) structures. In a preferred embodiment of the present invention, the semiconductor substrate 100 is an SOI substrate, which is beneficial to reducing substrate leakage and improving the electrical performance of the device. The SOI substrate includes, from bottom to top, an insulating layer 102 , a buried oxide layer 104 and a silicon layer 106 . In this embodiment, the semiconductor substrate 100 or the silicon layer 106 of the SOI substrate is heavily doped with n-type, which reduces the series resistance of the back electrode.

The storage medium layer 200 is formed on the semiconductor substrate 100 , and in this embodiment, the storage medium layer 200 is located on the silicon layer 106 of SOI. The storage medium layer 200 sequentially includes: a tunnel oxide layer 202 , a silicon nitride layer 204 , and a blocking oxide layer 206 from bottom to top.

The semiconductor layer 300 is formed on the storage medium layer 200 , and the semiconductor layer 300 includes a channel region 302 and a source region 304 and a drain region 306 located on two sides of the channel region 302 . Wherein, the channel region 302 is lightly doped with p-type, and the source region 304 and drain region 306 are heavily doped with n-type. In this embodiment, the material of the semiconductor layer 300 is silicon, that is, the silicon layer 106 of the SOI substrate, the tunnel oxide layer 202, the silicon nitride layer 204, the blocking oxide layer 206 and the semiconductor layer 300 constitute a SONOS type flash memory , the storage medium ONO layer (tunneling oxide layer 202-silicon nitride layer 204-blocking oxide layer 206) in the SONOS type flash memory is formed between the substrate 100 and the channel region 302, and the memory cell is realized by using the lining bias effect change in threshold voltage. Since the ONO layer of the storage medium is not connected to the channel region, that is, the charge storage region and the transistor operation region are separated in space, so that the read operation will not affect the electrical characteristics of the device, and the storage time of the stored charge is improved. Thereby improving the reliability of the device. Moreover, compared with the traditional SONOS flash memory, the flash memory according to the embodiment of the present invention has a smaller equivalent oxide layer thickness of the gate dielectric, which is beneficial to the reduction of device size.

A gate stack is formed on the channel region 302 , and the gate stack includes a gate dielectric 402 and a gate 404 formed on the gate dielectric 402 . The gate dielectric 402 may be any gate dielectric material used in manufacturing transistors, including but not limited to high-K dielectric and silicon dioxide. The gate 404 may be, but not limited to, a polysilicon gate or a metal gate.

It should be noted that, in the embodiment of the present invention, the silicon layer 106 of the SOI substrate can be patterned into a plurality of mutually isolated active regions (only one active region is shown in FIG. 1 and FIG. 2 ), and each memory Cells are formed in a separate active area so that different memories are completely isolated from each other.

In the embodiment of the present invention, sidewalls 406 are formed on the sidewalls of the gate dielectric 402 and the gate 404 . The spacer 406 may include silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, fluoride-doped silicon glass, low-k dielectric material (such as silicon carbonitride, silicon oxycarbonitride, etc.), or a combination thereof. The sidewall 406 may have a multi-layer structure. A passivation layer 500 is formed on the semiconductor substrate 100, the semiconductor layer 300, and the gate 404, and the passivation layer 500 has leads penetrating to the semiconductor substrate 100, the source region 304, the drain region 306 of the semiconductor layer 300, and the gate 404. hole 502 . As shown in FIG. 2 , for a memory cell, the area of the storage medium layer 200 is smaller than the area of the active region of the semiconductor substrate where it is located, so that electrodes can be drawn out of the active region. A lead metal layer 600 is formed on the passivation layer 500 , and the lead metal layer 600 is connected to the semiconductor substrate 100 , the source region 304 , the drain region 306 of the semiconductor layer 300 , and the gate 404 through the lead hole 502 . Preferably, a metal silicide may be formed on the semiconductor substrate 100, the source region 304, the drain region 306, and the gate 404, and the metal silicide forms an ohmic contact to reduce the contact resistance between the metal in the lead hole 502 and the semiconductor substrate 100 , the source region 304 and the drain region 306 , and the gate 404 .

The preparation method of the flash memory according to the embodiment of the present invention is specifically described below in conjunction with accompanying drawings 4-9, the method includes the following steps:

Step S1 : providing a semiconductor substrate 100 , and performing heavy doping of the first type on the semiconductor substrate 100 . In this embodiment, the semiconductor substrate 100 is an SOI substrate, and the device is formed on the SOI substrate, which is beneficial to reduce substrate leakage and improve the electrical performance of the device. As shown in FIG. 4 , the SOI substrate includes, from bottom to top, an insulating layer 102 , a buried oxide layer 104 and a silicon layer 106 . Ion implantation and annealing are performed on the silicon layer 106 to form n+ type doping to reduce the series resistance of the back electrode.

In the embodiment of the present invention, after step S1, it further includes: etching the silicon layer 106 of the SOI substrate to form active regions 108 isolated from each other, as shown in FIG. 5 . That is, each subsequent step is to form memory cells in the active region 108 , and a plurality of memory cells isolated from each other can be formed in an array on the entire semiconductor substrate.

Step S2: sequentially forming a tunnel oxide layer 202, a silicon nitride layer 204, and a blocking oxide layer 206 on the semiconductor substrate 100, that is, forming a storage medium ONO layer. Specifically, an oxide material, such as silicon oxide, is deposited on the silicon layer 106 , and the tunnel oxide layer 202 is formed through coating photoresist, photolithography, etching, and stripping. Then a silicon nitride layer 204 and a blocking oxide layer 206 are formed in the same manner, as shown in FIG. 6 .

Step S3 : forming a semiconductor layer 300 on the blocking oxide layer 206 , and performing light doping of the second type on the semiconductor layer 300 . In this embodiment, the material of the semiconductor layer 300 may be silicon, and the semiconductor layer 300 is formed on each active region 108 . Specifically, a semiconductor material layer, such as silicon, is deposited on the blocking oxide layer 206 , and the semiconductor layer 300 on the active region 108 is formed through coating photoresist, photolithography, etching, and stripping. Then ion implantation and annealing are performed on the semiconductor layer 300 to form p-type doping, as shown in FIG. 7 .

Step S4 : forming a gate stack on the semiconductor layer 300 , the gate stack includes a gate dielectric 402 and a gate 404 formed on the gate dielectric, and the area of the semiconductor layer covered by the gate stack is the channel region 302 . Specifically, a gate dielectric layer material is deposited on the semiconductor layer 300 , and a gate dielectric 402 is formed after coating photoresist, photolithography, etching, and stripping. In this embodiment, the material of the gate dielectric 402 may be, but not limited to, silicon dioxide or a high-K dielectric material such as hafnium oxide. Deposit the gate material on the gate dielectric 402. In this embodiment, the gate material can be but not limited to a polysilicon gate or a metal gate, and then apply photoresist, photolithography, etching, and glue removal to form The gate 404 is as shown in FIG. 8 .

In this embodiment, after step S4 , it further includes: forming sidewalls 406 on the sidewalls of the gate stack. Specifically, a protective medium can be deposited and dry-etched to form sidewalls 406 on the sidewalls of the gate stack. The protective medium can be silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or fluoride-doped silicon glass. , a low-k dielectric material (such as silicon carbonitride, silicon oxycarbonitride, etc.) or a combination thereof, as shown in FIG. 9 .

Step S5 : performing heavy doping of the first type on the exposed semiconductor layer 300 to form a source region 304 and a drain region 306 on both sides of the channel region 302 . In this embodiment, ion implantation and annealing are performed on the exposed semiconductor layer 300 to form n+ type doped regions on both sides of the channel region 302 , as shown in FIG. 10 .

In the embodiment of the present invention, after step S5, it also includes: step S6: forming a passivation layer 500 on the semiconductor substrate 100, the semiconductor layer 300 and the gate 404, and then photolithography, etching, on the passivation layer 10 A wiring hole 502 penetrating through the semiconductor substrate 100 , the semiconductor layer 300 and the gate 404 is formed. Step S7: forming a lead metal layer 600 on the passivation layer 500, the lead metal layer 600 is connected to the semiconductor substrate 100, the source region 302, the drain region 304, and the gate 404 of the semiconductor layer 300 through the lead hole 502, as shown in the figure 1-2 shown. Preferably, before step S6, it may also include: forming a metal silicide on the semiconductor substrate 100, the source region 302 and the drain region 304 of the semiconductor layer 300, and the gate 404, so as to reduce the metal and semiconductor substrate in the lead hole 502. Contact resistance between the bottom 100 , the source region 302 and the drain region 304 of the semiconductor layer 300 , and the gate 404 .

The invention provides a flash memory and a preparation method thereof. By forming a storage medium ONO layer between a substrate and a channel region, the threshold voltage of the memory unit is changed by using the lining bias effect. Since the charge storage area (ONO layer) is separated from the transistor operation area in space, the interference of the transistor operation area on the charge storage area is reduced, the reliability of the device is increased, and the data storage time of the memory is significantly improved. Moreover, compared with the traditional SONOS flash memory, the flash memory according to the embodiment of the present invention has a smaller equivalent oxide layer thickness of the gate dielectric, which is conducive to reducing the size of the device.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present invention have been shown and described, those skilled in the art can understand that various changes, modifications and substitutions can be made to these embodiments without departing from the principle and spirit of the present invention. and modifications, the scope of the invention is defined by the appended claims and their equivalents.

Claims (13)

1. a flash memory is characterized in that, comprising:

Semiconductor substrate;

Storage medium layer, said storage medium layer is formed on the said Semiconductor substrate, comprises successively from bottom to top: tunnel oxide, silicon nitride layer, barrier oxide layer;

Semiconductor layer, said semiconductor layer is formed on the said storage medium layer, comprises channel region and the source region and the drain region that are positioned at said channel region both sides; With

Grid pile up, and are formed on the said channel region, comprise gate medium and are formed on the grid on the said gate medium.

2. flash memory as claimed in claim 1 is characterized in that, said Semiconductor substrate is a silicon-on-insulator substrate.

3. flash memory as claimed in claim 2 is characterized in that, said semiconductor layer is a silicon layer.

4. according to claim 1 or claim 2 flash memory; It is characterized in that; The silicon layer of said Semiconductor substrate or said silicon-on-insulator substrate is first kind heavy doping, and said channel region is the second type light dope, and said source region and drain region are first kind heavy doping.

5. flash memory as claimed in claim 1 is characterized in that, is formed with side wall on the sidewall that said grid pile up.

6. flash memory as claimed in claim 4 is characterized in that, is formed with passivation layer on said Semiconductor substrate, semiconductor layer and the grid, has the fairlead that connects to said Semiconductor substrate, semiconductor layer and grid in the said passivation layer.

7. flash memory as claimed in claim 6 is characterized in that, is formed with the lead-in wire metal level on the said passivation layer, and said lead-in wire metal level is connected with said Semiconductor substrate, semiconductor layer and grid through said fairlead.

8. the preparation method of a flash memory is characterized in that, may further comprise the steps:

S1: Semiconductor substrate is provided, said Semiconductor substrate is carried out first kind heavy doping;

S2: on said Semiconductor substrate, form tunnel oxide, silicon nitride layer, barrier oxide layer successively;

S3: on said barrier oxide layer, form semiconductor layer, said semiconductor layer is carried out the second type light dope;

S4: on said semiconductor layer, form grid and pile up, said grid pile up and comprise gate medium and be formed on the grid on the said gate medium, and the zone that said grid pile up the said semiconductor layer of covering is a channel region;

S5: the said semiconductor layer to exposing carries out first kind heavy doping, to form source region and drain region in said channel region both sides.

9. the preparation method of flash memory as claimed in claim 8 is characterized in that, said Semiconductor substrate is a silicon-on-insulator substrate, and the silicon layer of said silicon-on-insulator substrate is carried out first kind heavy doping.

10. the preparation method of flash memory as claimed in claim 9 is characterized in that, also comprise after the step S1: the silicon layer of the said silicon-on-insulator substrate of etching is to form the active area of mutual isolation.

11. the preparation method of flash memory as claimed in claim 9 is characterized in that, said semiconductor layer is a silicon layer.

12. the preparation method of flash memory as claimed in claim 8 is characterized in that, also comprises after the step S4: the sidewall that piles up at said grid forms side wall.

13. the preparation method of flash memory as claimed in claim 8 is characterized in that, and is further comprising the steps of after the step S5:

S6: on said Semiconductor substrate, semiconductor layer and grid, form passivation layer, in said passivation layer, form the fairlead that connects to said Semiconductor substrate, semiconductor layer and grid;

S7: on said passivation layer, form the lead-in wire metal level, said lead-in wire metal level is connected with said Semiconductor substrate, semiconductor layer and grid through said fairlead.

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