CN102543928A - QFN (quad-flat no-lead) packaging structure - Google Patents
QFN (quad-flat no-lead) packaging structure Download PDFInfo
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- CN102543928A CN102543928A CN2011104467917A CN201110446791A CN102543928A CN 102543928 A CN102543928 A CN 102543928A CN 2011104467917 A CN2011104467917 A CN 2011104467917A CN 201110446791 A CN201110446791 A CN 201110446791A CN 102543928 A CN102543928 A CN 102543928A
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- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 13
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- 238000003786 synthesis reaction Methods 0.000 claims description 11
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention provides a QFN (quad-flat no-lead) packaging structure, which comprises a die, a base, a plurality of bonding pads and insulation materials, wherein the bonding pads are arranged surrounding the base, the insulation materials are filled in a packaging space of a packaging structure, the die is arranged on the base, and the thickness of the die ranges from 50 micrometers to 200 micrometers. The QFN packaging structure can be used for reducing the packaging thermal resistance.
Description
Technical field
The present invention relates to the encapsulation technology field of semiconductor device, relate in particular to a kind of QFN encapsulating structure.
Background technology
Along with the development of electronic product, for example consumer electronics products such as notebook computer, mobile phone, mini CD, palmtop PC, CPU, digital camera more and more develop to miniaturization.
For a short time do thinly along with doing of product, how the heat that millions of transistors produced among the IC distributes must not irrespective problem with regard to becoming one.In the prior art,, still can not avoid the trend of heat generation density increase though can reduce mode such as voltage and reduce caloric value through promoting IC processing procedure ability.Heat dissipation problem does not solve, and can make IC because of the overheated reliability of products that has influence on, and seriously can shorten life of product even cause the product damage.
In addition, realize that the chip of each function needs encapsulation, in the prior art, QFN encapsulating structure (Quad Flat NO Lead) is a kind of semiconductor chip package of quad flat non-pin.Because the QFN encapsulation has gull wing lead-in wire unlike traditional SOIC and TSOP encapsulation that kind, the conductive path between inner pin and the pad is short, and the cloth line resistance is very low in coefficient of self-inductance and the packaging body, so it can provide remarkable electrical property.
Under the situation that packing forms is fixed,, can only realize by any sacrifice in performance during product design for making the product heat radiation meet the demands; With the very big quick charge of present demand is example; The charging current of 300mA, power consumption is 1.5W nearly, if electric current is big again; The chip caloric value can not in time be distributed, and reliability of products and life-span will receive very big influence.If there is not the packaging thermal resistance restriction, charging current can be accomplished 1A, and the time of charging is just saved greatly.So how to reduce the thermal resistance of encapsulation, realize that in as far as possible little encapsulated space the design of bigger power consumption has become the key of restriction production development.
In view of this, be necessary to propose a kind of new QFN encapsulating structure in fact, this encapsulating structure can reduce the thermal resistance in it.
Summary of the invention
The purpose that the present invention realizes provides a kind of new QFN encapsulating structure, and this encapsulating structure can reduce the thermal resistance in it.
For realizing above-mentioned purpose, the present invention provides a kind of QFN encapsulating structure, comprising:
Chip;
Ji Dao, said chip is arranged on the Ji Dao;
A plurality of pads around said Ji Dao layout;
The insulation material of filling in the encapsulated space of said encapsulating structure;
Wherein, the thickness range of said chip is: 50 μ m-200 μ m.
Alternatively, the another side of the said encapsulating structure relative with the one side at said Ji Dao place is provided with the heat-conducting metal structure.
Alternatively, said heat-conducting metal structure material is a stainless steel.
Alternatively, said heat-conducting metal thickness of structure scope is: 150 μ m-350 μ m.
Alternatively, bond through the silver slurry between said heat-conducting metal structure and the said insulation material.
Alternatively, the back side of said chip and said Ji Dao are through silver slurry bonding.
Alternatively, said insulation material is the plastic packaging synthesis material, and the thickness of said plastic packaging synthesis material is not more than 600 μ m.
Alternatively, at least one said pad is communicated with said Ji Dao, and all the other pads are connected with said chip through metal wire.
Alternatively, the material of said metal wire is a gold.
Alternatively, said QFN encapsulating structure is fixed on the pcb board.
Compared with prior art, technique scheme has the following advantages: in the existing QFN encapsulating structure, chip leans on heat radiation up or down; Its thickness is greatly about 200 μ m-300 μ m; And the chip heating region generally concentrates within the 10 μ m of top layer, and this zone also is a device area, and the back side of chip does not have device; Be generally silicon, the thermal conductivity of this silicon is very poor.Thereby the inventor proposes the thinning back side with chip, reaches gross thickness and is: 50 μ m-200 μ m; Thereby shorten the path that chip dispels the heat through the back side up or down, reduced the packaging thermal resistance of QFN structure;
Further, the another side of the said encapsulating structure relative with the one side at Ji Dao place is provided with the heat-conducting metal structure, and evenly packaging body heat radiation has strengthened the upwards effect of heat radiation of QFN encapsulating structure (chip);
Further, the one side with respect to Ji Dao of said encapsulating structure is provided with the heat-conducting metal structure, and said heat-conducting metal structure material is a stainless steel; Strengthened the vapour corrosion property that has improved the anti-environment for use of QFN encapsulating structure when the QFN encapsulating structure makes progress the effect of dispelling the heat, the useful life of having improved the QFN encapsulating structure;
Further; The another side of the said encapsulating structure relative with the one side at said Ji Dao place is provided with the heat-conducting metal structure; And bond through the silver slurry between heat-conducting metal structure and the said insulation material; Adopt the good conductor of silver-colored this heat, strengthened the upwards effect of heat radiation of QFN encapsulating structure (chip);
Further; The back side of said chip and said Ji Dao are through silver slurry bonding; Based on and heat-conducting metal structure and said insulation material between adopt the similar reason of silver slurry bonding, adopted the good conductor of silver-colored this heat, strengthened QFN encapsulating structure (chip) effect of heat radiation downwards;
Further; Said insulation material is the plastic packaging synthesis material; The thickness of said plastic packaging synthesis material is not more than 600 μ m, compares with existing QFN encapsulating structure thickness, has reduced the relatively poor plastic packaging synthesis material thickness of thermal conductivity; Shorten the upwards path of heat radiation of QFN encapsulating structure (chip), strengthened radiating effect;
Further, at least one pad is communicated with Ji Dao, all the other pads are connected with said chip through metal wire, and pad is communicated with the area that has played the conducting strip that increases the downward heat radiation of QFN encapsulating structure with Ji Dao, have played the purpose that reduces thermal resistance.
Description of drawings
Fig. 1 is the vertical view of the QFN encapsulating structure that provides of the embodiment of the invention;
Fig. 2 is the upward view of the QFN encapsulating structure that provides of the embodiment of the invention;
Fig. 3 is along the cutaway view of A-A straight line among Fig. 2;
Fig. 4 is along the cutaway view of B-B straight line among Fig. 2;
Fig. 5 and Fig. 6 are respectively the sketch map of the definition of the two kinds of thermal resistance value of standard that are used for showing SEMI.
Embodiment
Said as background technology, under the fixing situation of packing forms,, generally be that any sacrifice in performance realizes during through product design in the prior art for making the product heat radiation meet the demands.The present invention will not have the chip back attenuate of device, reach gross thickness to be: 50 μ m-200 μ m; Thereby shorten the path that chip dispels the heat through the back side up or down, reduce the thermal resistance of encapsulating structure.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.Because the present invention focuses on interpretation principle, therefore, drawing not in scale.
The vertical view of the QFN encapsulating structure that Fig. 1 provides for the embodiment of the invention, Fig. 2 is the upward view of this structure, Fig. 3 be among Fig. 2 along the cutaway view of A-A straight line, Fig. 4 is along the cutaway view of B-B straight line among Fig. 2.In conjunction with Fig. 1 to Fig. 4, this encapsulating structure comprises:
Base island 12;
Eight pads 13 arranging around this base island 12;
The insulation material 14 of filling in the encapsulated space of said encapsulating structure;
Wherein, the thickness range of this chip 11 is: 50 μ m-200 μ m.
In the present embodiment one, this chip (Die) the 11st, the thermal source of overall package structure, and heating region generally concentrates within the 10 μ m of top layer, i.e. the positive device region of chip 11, the Back Material of chip 11 is a silicon, and the back side does not have device.Device region is connected with pad 13 through metal wire 15; Fill isolated each conductive structure of insulation material in 13 electric actions of the pad of this connection, remaining encapsulated space, in the present embodiment one; Metal wire 15 can be metal wire, and this insulation material 14 is selected the plastic packaging synthesis material.This plastic packaging synthesis material is mixed by epoxy resin and particles filled thing.In the present embodiment, preferred chip 11 device regions are placed on the basic island 12 up, and promptly the heat of chip 11 distributes through the bigger basic island 12 of area.After chip 11 was packed, its heat radiation approach can be through the upwards heat radiation or the approach that dispels the heat downwards.According to statistics, existing QFN encapsulating structure, chip 11 produced 85% heat be through the encapsulating structure that sheds of the basic island 12 under it, and have only 15% heat to distribute through the insulation material on it.The present invention has improved the QFN encapsulating structure, and its thermal resistance that makes progress, dispels the heat is downwards reduced.
The downward heat radiation approach of following analysis earlier.
In the present embodiment one, preferred chip 11 device regions are placed on the basic island 12 up, and promptly the heat of chip 11 distributes through the bigger basic island 12 of area.As noted earlier, in the existing QFN encapsulating structure, chip 11 thickness are greatly about 200 μ m-300 μ m; And chip 11 heating regions generally concentrate on the device area of top layer, and within about 10 μ m, the back side of chip does not have device; Be generally silicon, the thermal conductivity of this silicon is very poor.Thereby the encapsulating structure of present embodiment is with the thinning back side of chip 11, and the inventor finds, when its 11 gross thickness is 50 μ m-200 μ m, can not influence the performance of chip 11, can effectively reduce the thermal resistance of encapsulating structure again.
In addition, the encapsulating structure that present embodiment provides also is communicated with basic island 12 with a pad 13, and the connection here is meant on the physical structure and is communicated with that this pad 13 plays the ground connection effect, and all the other seven pads 13 are connected with chip 11 through metal wire 15.Referring to Fig. 1, Fig. 2 and shown in Figure 4.Because pad 13 is communicated with basic island 12, has increased the area of the fin of chip 11 back sides contacts, thereby strengthened its effect of dispelling the heat downwards through the back side.Still be not connected electric action with chip, specifically referring to shown in Figure 3 through metal wire 15 with the pad 13 that basic island 12 is communicated with.This metal wire 15 can be gold thread.Among other embodiment, can design more than one pad 13 and be communicated with according to the wiring situation of chip 11 with basic island 12.
In addition, the encapsulating structure that present embodiment provides has improved the bonding material (not indicating) between chip 11 back sides and the basic island 12, particularly, adopts silver slurry bonding.This silver slurry component is the mixture of silver and binding agent, it is understandable that the content of silver is high more, and heat conductivility is good more.
Then analyze upwards heat radiation approach.
Referring to Fig. 2 and shown in Figure 3, present embodiment is at the upper surface of encapsulating structure, and promptly the one side with respect to basic island 12 is provided with heat-conducting metal structure 16.In the present embodiment, these heat-conducting metal structure 16 materials are stainless steel, because this heat-conducting metal structure 16 is arranged on the outer surface of encapsulating structure, thereby stainless steel is not allowed to be subject to the influence of water in air vapour and got rusty, and reduces heat conductivility.In addition, can find out among Fig. 3 and Fig. 4 that chip 11 just is in one of the encapsulating structure center very zonule; Thereby pyrotoxin is more concentrated; This metal structure is a laminated structure, sees the dashed region among Fig. 1, covers the upper surface of encapsulating structure as far as possible; The thermal source of concentrating is dispersed on the whole laminated structure, avoids encapsulating structure local heating.
The inventor finds that this stainless thickness range is: during 150 μ m-350 μ m, can preferably dispel the heat, and package dimension meets the demands.
In addition, the encapsulating structure that present embodiment provides has improved the bonding material (not indicating) between existing heat-conducting metal structure 16 and the said insulation material 14, particularly, adopts silver slurry bonding.This silver slurry is the mixture of silver with binding agent, and wherein, the content of silver is high more, and heat conductivility is good more.
In addition, present embodiment also compresses the thickness of existing insulation material 14, insulation material 14; Be the plastic packaging synthesis material in the present embodiment, this material is relatively poor to the conductibility of heat, and the purpose of its filling is to avoid undesirable conductive structure electric connection; Be mainly conducting of metal wire 15 and other pad 13, thereby, through controlling the routing camber line height of this metal wire 15; Can be under the prerequisite that plays insulation effect, the thickness of attenuate insulation material 14.The thickness of normal QFN encapsulating structure epoxy resin is approximately 700 μ m-800 μ m, in the present embodiment, can control the height of routing, and promptly the thickness of may command plastic packaging synthesis material is not more than 600 μ m, has shortened the path of upwards conducting heat.
On the QFN encapsulating structure that the QFN encapsulating structure that present embodiment provides can use in all sizes, for example encapsulating structure such as 4mm*4mm, 3mm*3mm is compatible strong with existing encapsulating structure.
At last, in the existing IC circuit, packaged QFN encapsulating structure is to be fixed on the pcb board, and several holes are set on pcb board more, also can improve the heat dispersion of this encapsulating structure, reduces thermal resistance.
For verifying the heat dispersion of QFN encapsulating structure provided by the invention, the inventor has measured encapsulating structure and the thermal resistance of existing QFN encapsulating structure of the foregoing description of 3mm*3mm specification.Defined two kinds of thermal resistance value in the standard according to SEMI, i.e. Θ ja and Θ jc, wherein Θ ja measures under free convection or conditions of forced convection, to connect face from chip and pass to the heat the atmosphere, and as shown in Figure 5, some temperature of being got in the chip 11 are T
j, the temperature in the atmosphere is T
a, Q is the heat energy that is consumed,
Because measuring is under the condition of standard criterion, to do, therefore just have different results for different substrate design and environmental condition, this value can be used for the comparison package cooling easily whether, be used for comparing qualitatively.Θ jc is meant that heat connects the thermal resistance that face passes to the IC package casing by chip, and is as shown in Figure 6, and some temperature of being got in the chip 11 still are T
j, the temperature of package casing is T
Tts, the heat energy that is consumed still is Q,
When measuring, need contact an isothermal level, this value mainly is the performance that is used to assess fin.These two kinds of thermal resistances all exist resistance big more, the phenomenon that radiating effect is poor more.
Measurement result is: Θ ja and Θ jc before improving are respectively 61 ℃/W; 38 ℃/W, after the improvement, Θ ja and Θ jc are respectively 34 ℃/W; 23 ℃/W; Can find out that the thermal resistance value of the QFN encapsulating structure after the improvement is significantly less than the thermal resistance value before improving, and has shown that quantitatively QFN encapsulating structure provided by the invention improves the heat dispersion of himself.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (10)
1. QFN encapsulating structure comprises:
Chip;
Ji Dao, said chip is arranged on the Ji Dao;
A plurality of pads around said Ji Dao layout;
The insulation material of filling in the encapsulated space of said encapsulating structure;
It is characterized in that the thickness range of said chip is: 50 μ m-200 μ m.
2. QFN encapsulating structure as claimed in claim 1 is characterized in that, the another side of the said encapsulating structure relative with the one side at said Ji Dao place is provided with the heat-conducting metal structure.
3. QFN encapsulating structure as claimed in claim 2 is characterized in that, said heat-conducting metal structure material is a stainless steel.
4. like claim 2 or 3 described QFN encapsulating structures, it is characterized in that said heat-conducting metal thickness of structure scope is: 150 μ m-350 μ m.
5. QFN encapsulating structure as claimed in claim 2 is characterized in that, bonds through the silver slurry between said heat-conducting metal structure and the said insulation material.
6. QFN encapsulating structure as claimed in claim 1 is characterized in that, the back side of said chip and said Ji Dao are through silver slurry bonding.
7. QFN encapsulating structure as claimed in claim 1 is characterized in that, said insulation material is the plastic packaging synthesis material, and the thickness of said plastic packaging synthesis material is not more than 600 μ m.
8. QFN encapsulating structure as claimed in claim 1 is characterized in that, at least one said pad is communicated with said Ji Dao, and all the other pads are connected with said chip through metal wire.
9. QFN encapsulating structure as claimed in claim 1 is characterized in that, the material of said metal wire is a gold.
10. QFN encapsulating structure as claimed in claim 1 is characterized in that, said QFN encapsulating structure is fixed on the pcb board.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011104467917A CN102543928A (en) | 2011-12-27 | 2011-12-27 | QFN (quad-flat no-lead) packaging structure |
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| CN2011104467917A CN102543928A (en) | 2011-12-27 | 2011-12-27 | QFN (quad-flat no-lead) packaging structure |
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- 2011-12-27 CN CN2011104467917A patent/CN102543928A/en active Pending
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| CN102097409A (en) * | 2009-11-05 | 2011-06-15 | 瑞萨电子株式会社 | Semiconductor device and method for manufacturing the same |
| CN101771008A (en) * | 2010-01-29 | 2010-07-07 | 江苏长电科技股份有限公司 | External connection heat radiation plate encapsulation structure of positive installation lock hole heat radiation block of base island exposed chip |
| CN101777539A (en) * | 2010-01-29 | 2010-07-14 | 江苏长电科技股份有限公司 | External radiator packaging structure of inverted-T heat radiating block positively arranged on base island exposed chip |
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Application publication date: 20120704 |