CN102543878A - Manufacturing method of memory - Google Patents

Abstract

The present invention discloses a method for manufacturing a memory. The manufacturing method comprises the following steps: providing a substrate including a memory cell region and a peripheral region, a plurality of gates having spacers formed on the substrate, and a plurality of openings between the gates of the memory cell region. Forming a first material layer in the memory cell region to cover the gates and fill the openings. Forming a barrier layer on the substrate to cover the gates of the peripheral region and the first material layer of the memory cell region. Forming a second material layer on the substrate in the peripheral region to cover the barrier layer on the gates of the peripheral region. Removing the barrier layer covering the first material layer. Removing a portion of the first material layer to form a plurality of second openings, the second openings being located on the top of the gates of the memory cell region. Forming a pattern in the second opening. Removing the first material layer to form a plurality of contact window openings. Forming a contact window plug in each contact window opening. The present invention can simplify the process and enable the memory to have good characteristics.

Description

Manufacturing method of memory

technical field

The invention relates to a manufacturing method of a memory.

Background technique

Generally, as the size of the memory gradually shrinks, in order to overcome the increasingly smaller line width and prevent the misalignment of the contact, a self-aligned contact (SAC) process is adopted.

In the self-aligned contact process, the thickness of the spacer on the sidewall of the gate will affect the size of the contact formed between the gates. However, since the memory device includes a memory cell area and a peripheral area, and the elements in the memory cell area and the peripheral area have different requirements on the thickness of the spacer, the complexity of the process is increased. Generally speaking, the first layer of spacers will be formed on the gate sidewalls of the memory cell region and the peripheral region at the same time, and then, in order to form the source and drain regions of the peripheral region, usually on the first layer of the gate of the peripheral region A second layer of spacers is formed on the first layer of spacers. Among them, in order to simplify the process, the second layer of spacer material will be filled into the openings between the gates of the memory cell area at the same time, and after the source and drain regions are formed in the base of the peripheral area, the peripheral area will be removed together. The second layer of spacer material in the region and the second layer of spacer material between the gates of the memory cell region.

However, since the openings between the gates of the memory cell region have a relatively large aspect ratio, it is not easy to remove the second layer of spacer material between the gates, and the removal process may Will damage the first layer of spacers in the memory cell area. As a result, the first-layer spacer cannot provide good electrical insulation for the gate, and affects the size of the subsequent contact window formed by using the first-layer spacer. In addition, unfavorable removal conditions will cause damage to the substrate in the peripheral region, resulting in degradation of device characteristics.

Contents of the invention

The purpose of the present invention is to provide a manufacturing method of a memory, which simplifies the steps and makes the memory have good device characteristics.

The invention provides a manufacturing method of a memory. Firstly, a substrate is provided. The substrate includes a memory cell region and a peripheral region. A plurality of gates have been formed on the substrate, and a first spacer is provided on the sidewall of each gate, wherein the gates of the memory cell region There are a plurality of first openings between them. Next, a first material layer is formed on the base of the memory unit area, the first material layer covers the gate of the memory unit area and fills up the first opening. Then, a barrier layer is formed on the substrate to cover the gate in the peripheral area and the first material layer in the memory unit area. Next, a second material layer is formed on the base of the peripheral region to cover the barrier layer on the gate of the peripheral region. Then, the barrier layer covering the first material layer is removed. Then, part of the first material layer is removed to form a plurality of second openings, and each second opening is located on the top of each gate of the memory cell region. Then, a first pattern is formed in each second opening. Next, the remaining first material layer is removed to form a plurality of contact window openings in the memory cell area. Then, a contact plug is formed in each contact opening, wherein the first pattern is arranged between the contact plugs.

The beneficial effect of the present invention is that, based on the above, the manufacturing method of the memory of the present invention uses the first material layer and the second material layer to protect the elements of the memory cell area and the peripheral area respectively, so that one of the peripheral area and the memory cell area When processing such as deposition and etching, the other of the peripheral region and the memory cell region will not be damaged, so that the spacers on the gate sidewalls can maintain a complete structure. In this way, the spacer can provide good electrical insulation for the gate, and can form a self-aligned contact window between two adjacent spacers, so that the memory has good device characteristics.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 to FIG. 9 are cross-sectional schematic diagrams of a manufacturing method of a memory according to an embodiment of the present invention.

Wherein, the reference signs are explained as follows:

100: base

102: storage unit area

104: Outer area

110, 120: grid

110a: top

112, 122, 124: spacers

114, 132: opening

126: Source and drain regions

130, 150: material layer

134, 135: contact window opening

136, 137: contact window plug

140: barrier layer

150a: top surface

160: pattern

Detailed ways

1 to 9 are schematic cross-sectional flow diagrams of a manufacturing method of a memory according to an embodiment of the present invention.

Please refer to FIG. 1, firstly, a substrate 100 is provided, the substrate 100 includes a memory cell region 102 and a peripheral region 104, a plurality of gates 110, 120 have been formed on the substrate 100, and the sidewalls of the gates 110, 120 have first The spacers 112 and 122 have a plurality of first openings 114 between the gates 110 of the memory cell region 102 . The substrate 100 is, for example, a semiconductor substrate, such as an N-type or P-type silicon substrate, a III-V semiconductor substrate, and the like. The material of the gates 110 and 120 is, for example, doped polysilicon, and the material of the first spacers 112 and 122 is, for example, silicon nitride.

Referring to FIG. 2 , next, a first material layer 130 is formed on the substrate 100 , the first material layer 130 covers the memory cell region 102 and the peripheral region 104 , and the first material layer 130 fills the opening 114 . The first material layer 130 is, for example, a polysilicon layer, and its formation method is, for example, chemical vapor deposition. In this embodiment, this step further includes performing a planarization process such as chemical mechanical polishing (CMP) on the first material layer 130 .

Referring to FIG. 3 , then, the first material layer 130 covering the peripheral region 104 is removed to expose the peripheral region 104 . A method for removing the first material layer 130 is, for example, reactive ion etching (RIE).

Referring to FIG. 4 , next, a second spacer 124 is formed on the first spacer 122 of the gate 120 in the peripheral region 104 . The second spacer 124 is formed by, for example, first forming a spacer material layer (not shown in the figure) on the substrate 100 by means of chemical vapor deposition, and then performing an anisotropic etching process to remove part of the spacer material layer. , so as to form a spacer structure on the first spacer 122 . The material of the second spacer 124 is, for example, silicon nitride, and the method of removing part of the material layer of the spacer to form the second spacer 124 is, for example, reactive ion etching.

Then, for example, using the second spacer 124 as a mask, an implantation process is performed to form source and drain regions 126 on both sides of the gate 120 in the peripheral region 104 . In particular, after the source and drain regions 126 are formed on both sides of the gate 120 in the peripheral region 104, the second spacer 124 may or may not be removed. In this embodiment, the second spacer 124 is not removed. The second spacer 124 is taken as an example. In other words, the step of removing the second spacer 124 is actually an optional step.

In particular, compared with the known technology, the spacer material will be filled into the openings between the gates of the memory cell region at the same time when the second spacer is formed, or the second spacer will be removed when the second spacer is removed. In addition to the spacer material layer in the opening, in this embodiment, since the first material layer 130 will cover the gate 110 and the first spacer 112 protecting the memory cell region 102, the formation or removal of the second spacer 124 No process (including deposition or etching process) will cause damage to the gate 110 or the first spacer 112 of the memory cell region 102 , so that the first spacer 112 of the memory cell region 102 can maintain a complete structure. In other words, the first material layer 130 is suitable for protecting the memory cell region 102 from damage that may be caused by any processing performed on the peripheral region 104 .

Please refer to FIG. 5 , and then, a barrier layer 140 is formed on the substrate 100 to cover the first material layer 130 of the memory cell region 102 and the gate 120 of the peripheral region 104 . In this embodiment, the barrier layer 140 is, for example, the first material layer 130 covering the gate 120 of the peripheral region 104 , the surfaces of the first spacer 122 and the second spacer 124 , and the memory cell region 102 .

Next, a second material layer 150 is formed on the substrate 100 in the peripheral region 104 to cover the barrier layer 140 on the gate 120 in the peripheral region 104 . In this embodiment, the second material layer 150 includes, for example, borosilicate glass or silicon oxide, and its formation method is, for example, chemical vapor deposition. In this embodiment, this step is, for example, first forming a second material layer on the substrate 100 that completely covers the peripheral region 104 and the memory cell region 102, and then using the barrier layer 140 on the first material layer 130 as an etching stop layer , performing a planarization process on the second material layer, so that the top surface 150 a of the second material layer 150 is approximately equal to the top surface of the barrier layer 140 and substantially on the same plane. Wherein, the planarization process includes, for example, a chemical mechanical polishing process.

Generally, if the barrier layer 140 is not formed on the first material layer 130 of the memory cell region 102, when the second material layer 150 is planarized, the top of the first material layer 130 will be used as an etching stop. layer. In this way, the second material layer 150 may be over-etched, which may cause the first material layer 130 to have a dishing phenomenon. However, in this embodiment, since the first material layer 130 of the memory cell region 102 is covered with the barrier layer 140, when the second material layer 150 is planarized, the The barrier layer 140 serves as an etching stop layer, and since the barrier layer 140 generally has a higher density, the above-mentioned problems of the second material layer 150 and the first material layer 130 can be avoided.

Referring to FIG. 6 , next, the barrier layer 140 covering the first material layer 130 of the memory cell region 102 is removed. A method for removing part of the barrier layer 140 is, for example, a dry etching process.

Then, part of the first material layer 130 is removed to form a plurality of second openings 132 . In this embodiment, the method for removing part of the first material layer 130 includes reactive ion etching. In particular, in this embodiment, in the step of forming the second opening 132, since the area of the peripheral region 104 has been completely covered and protected by the second material layer 150, it is selected to remove part of the first material layer. The etching conditions of the layer 130 do not need to take into account whether the peripheral region 104 will be damaged, and better etching conditions can be used to remove part of the first material layer 130 to obtain the second opening 132 with a vertical profile. For example, in the selection of the etchant, it is not necessary to consider whether the etchant used has a high selective etching ratio for the first material layer 130 and the gate 120, but can only be obtained from the viewpoint of openings with a better profile. Make a selection.

Please refer to FIG. 7 , and then, a first pattern 160 is formed in each second opening 132 . The material of the first pattern 160 includes, for example, borophosphosilicate glass or silicon oxide, and the forming method thereof is, for example, a chemical vapor deposition process.

Referring to FIG. 8 , next, the remaining first material layer 130 is removed to form a plurality of contact openings 134 in the memory cell region 102 . A method for removing the first material layer 130 is, for example, a dry etching method or a wet etching method. Then, a part of the second material layer 150 located in the peripheral region 104 is removed to form a contact opening 135 in the peripheral region 104 , wherein the contact opening 135 exposes the source and drain regions 126 . A method for removing the second material layer 150 is, for example, a dry etching method or a wet etching method.

Please refer to FIG. 9, and then, fill the conductive material layer in the contact window openings 134, 135 to form a contact window plug 136 between two adjacent first spacers 112, and form a contact window plug in the peripheral region 104. 137. The material of the contact plugs 136 and 137 is, for example, tungsten, copper, aluminum or other suitable metals.

In this embodiment, the first material layer 130 is used to protect the memory cell region 102 to facilitate the processing of the peripheral region 104 (such as forming and removing the second spacer 124 ), and then the first material layer 130 is used to protect the memory cell region 102. The barrier layer 140 serves as an etching stop layer for forming the second material layer 150 to avoid the problem of over-etching of the second material layer 150 and the phenomenon of surface depression of the first material layer 130 . Then, in the process of removing the first material layer 130 to form the first pattern 160 , since the second material layer 150 can protect the peripheral region 104 , the first pattern 160 has a better vertical profile. In addition, since the first spacer 112 of the memory cell region 102 will be covered by the first material layer 130, the first spacer 112 will not be affected by the processing process of the peripheral region 104 (such as the formation and removal of the second spacer). Therefore, good electrical insulation can be provided for the gate 110 , and a contact plug 136 can be formed between the intact first spacer 112 structures.

To sum up, in the manufacturing method of the memory of the present invention, the elements in the memory cell region and the peripheral region are protected by the first material layer and the second material layer respectively, so that when depositing one of the peripheral region and the memory cell region During processing such as etching, the other of the peripheral region and the memory cell region will not be damaged, so that the spacers on the gate sidewalls can maintain a complete structure. In addition, when forming the second material layer, since the barrier layer has been formed on the first material layer, it can protect the first material layer from problems such as dents due to the planarization process of the second material layer, which is beneficial to subsequent A pattern defining a contact plug is formed in the first material layer. In particular, in the step of forming the pattern used to define the contact plug, since the gate of the peripheral region has been covered and protected by the second material layer, there is no need to consider whether the connection between the gate of the peripheral region and the spacer will be damaged. Select a better etching method under the conditions to obtain a pattern with a better profile. In this way, the spacers in the memory cell area and the peripheral area have complete structures, so a self-aligned contact window can be formed between two adjacent spacers, so that the memory has good device characteristics.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall prevail as defined by the claims.

Claims (8)

1. the manufacturing approach of a memory comprises step:

One substrate is provided, and this substrate comprises a memory cell areas and an external zones, has been formed with a plurality of grids in this substrate, and respectively has one first clearance wall on the sidewall of this grid, wherein has a plurality of first openings between said a plurality of grids of this memory cell areas;

In this substrate of this memory cell areas, form one first material layer, said a plurality of grids of this this memory cell areas of first layer of material covers and fill up said a plurality of first opening;

In this substrate, form a barrier layer, with said a plurality of grids of covering this external zones and this first material layer of this memory cell areas;

In this substrate of this external zones, form one second material layer, with this barrier layer on the said a plurality of grids that cover this external zones;

Remove this barrier layer that covers this first material layer;

Remove this first material layer of part, to form a plurality of second openings, respectively this second opening is positioned on the top of respectively this grid of this memory cell areas;

In respectively forming one first pattern in this second opening;

Remove remaining this first material layer, to form a plurality of contact windows in this memory cell areas; And

In respectively forming a contact hole connector in this contact window, wherein said a plurality of first pattern arrangement are between said a plurality of contact hole connectors.

2. the manufacturing approach of memory as claimed in claim 1 is characterized in that, this manufacturing approach also comprises step:

On this first clearance wall of respectively this grid of this external zones, form one second clearance wall; And

With said a plurality of second clearance walls is mask, forms one source pole and drain region in respectively these grid both sides of this external zones.

3. the manufacturing approach of memory as claimed in claim 2 is characterized in that, this barrier layer more covers said a plurality of second clearance wall.

4. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of this barrier layer comprises silicon nitride.

5. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the step that forms this second material layer comprises:

In this substrate, form one second material layer that comprehensively covers; And

With this barrier layer on this first material layer is an etch stop layer, and this second material layer is carried out a flatening process.

6. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of this second material layer comprises boric acid silex glass or silica.

7. the manufacturing approach of memory as claimed in claim 1 is characterized in that, this first material layer comprises polysilicon.

8. the manufacturing approach of memory as claimed in claim 1 is characterized in that, the material of said first pattern comprises boron-phosphorosilicate glass or silica.

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