CN102543825B - Manufacturing method of semiconductor trench and double trench and structure for isolating elements - Google Patents

Abstract

The invention relates to a manufacturing method of a semiconductor trench and a double trench and a structure for isolating elements. The structure for isolating the element comprises a first isolation structure and a second isolation structure. The first isolation structure has a profile of at least three steps and is located in the substrate of the peripheral region. The second isolation structure has a cross section of at least two steps and is located in the substrate of the array region.

Description

Manufacturing method of semiconductor trench and double trench and structure for isolating elements

technical field

The invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a double isolation structure or double trench structure with different depths and a manufacturing method thereof.

Background technique

Today, with the vigorous development of integrated circuits, the miniaturization and integration of components is an inevitable trend, and it is also an important topic for active development in all walks of life. As the size of components shrinks and the degree of integration gradually increases, the isolation structure between components must also be reduced. Therefore, the difficulty of component isolation technology also gradually increases.

As far as the current isolation technology is concerned, since the shallow trench isolation structure (shallow trench isolation, STI) has the advantage of being easy to adjust the size, and can avoid the shortcoming of the bird's beak erosion in the traditional area oxidation (LOCOS) method isolation technology, therefore, it is suitable for the second half It is an ideal isolation technology for the metal oxide semiconductor process of micron or below.

In addition, according to different applications of the array area and the peripheral area of the memory device, the depths of the required isolation structures are also different. Generally speaking, the depth of the shallow trench isolation structure in the peripheral area is much greater than the depth of the shallow trench isolation structure in the array area. Therefore, when manufacturing such a double isolation structure with different depths, usually at least two lithography processes are required to fulfill the above requirement, which is complicated and costly.

It can be seen that the manufacturing method of the double isolation structure with different depths in the above-mentioned existing memory element and the isolation structure obviously still have inconveniences and defects in the manufacturing method, product structure and use, and need to be further improved. In order to solve the above-mentioned existing problems, relevant manufacturers have tried their best to find a solution, but no suitable design has been developed for a long time, and there is no suitable method and structure for general methods and products to solve the above-mentioned problems. This is obviously a problem that relevant industry players are eager to solve. Therefore, how to create a new manufacturing method of semiconductor trenches and double trenches and a structure for isolating components is one of the current important research and development topics, and it has also become a goal that the industry needs to improve.

Contents of the invention

The main purpose of the present invention is to overcome the existing defects in the manufacturing method and isolation structure of the double isolation structure with different depths in the existing memory element, and to provide a new semiconductor trench and double trench manufacturing method and for isolating The technical problem to be solved for the structure of the element is to make it only need one lithography process to manufacture double isolation structures with different depths, the process is simple and cost-saving, and is very suitable for practical use.

The purpose of the present invention and the solution to its technical problems are achieved by adopting the following technical solutions. A method for manufacturing a semiconductor trench proposed according to the present invention. Firstly, a base is provided, and the base has a peripheral area and an array area. Then, a mask layer is formed on the base, and the mask layer has a first opening exposing the base of the peripheral area and a second opening exposing the base of the array area. Next, a first spacer is formed on the sidewall of the first opening. Afterwards, using the mask layer and the first spacer as a mask, a depression is formed in the base of the peripheral area. Then, a second spacer is formed on the sidewall of the second opening, and part of the first spacer is removed to expose the top corner of the depression. Next, using the mask layer, the first spacer and the second spacer as a mask, part of the substrate is removed to form a first trench in the substrate of the peripheral region and a second trench in the substrate of the array region.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned method of manufacturing a semiconductor trench, the first opening is larger than the second opening.

The aforementioned method of manufacturing a semiconductor trench, wherein the step of forming a first spacer on the sidewall of the first opening includes: forming a dielectric material layer on the substrate, the thickness of the dielectric material layer being greater than half the width of the second opening; and Part of the dielectric material layer is removed until the surface of the mask layer is exposed, wherein the remaining dielectric material layer forms a first spacer on the sidewall of the first opening and fills up the second opening.

The aforementioned method of manufacturing a semiconductor trench further includes filling the first trench and the second trench with a first dielectric layer, wherein the material of the dielectric material layer is the same as that of the first dielectric layer.

In the aforementioned method of manufacturing a semiconductor trench, after the step of forming the first trench and the second trench and before the step of filling the first dielectric layer, the method of the present invention further includes: removing the first spacer and the second a spacer; and forming a liner on the surface of the first ditch and the second ditch.

In the aforementioned method of manufacturing a semiconductor trench, the surface of the substrate exposed by the first opening and the second opening is lower than the bottom surface of the mask layer.

In the aforementioned method of manufacturing semiconductor trenches, the first trench has a cross-section of at least three levels, and the second trench has a cross-section of at least two levels.

The aforementioned method of manufacturing semiconductor trenches, wherein the depth of the first trench is 2 to 3 times the depth of the second trench.

The purpose of the present invention and the solution to its technical problem also adopt the following technical solutions to achieve. A method for manufacturing double trenches with different depths proposed according to the present invention. First, a substrate is provided, and the substrate has a first region and a second region. Then, a mask layer is formed on the base, the mask layer has a first opening exposing the base of the first area and a second opening exposing the base of the second area. Next, a first spacer is formed on the sidewall of the first opening and the first dielectric layer is filled in the second opening. A depression is formed in the base of the first region by using the mask layer and the first spacer as a mask. After that, part of the first dielectric layer is removed to form a second spacer on the sidewall of the second opening, and part of the first spacer is removed to expose the top corner of the recess. Then, using the mask layer, the first spacer and the second spacer as a mask, part of the substrate is removed to form a first trench in the substrate of the first region and a second trench in the substrate of the second region.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

In the aforementioned method of manufacturing double trenches with different depths, the first opening is larger than the second opening.

The aforementioned method for manufacturing double trenches with different depths, wherein the step of forming a first spacer on the sidewall of the first opening and filling the second opening with the first dielectric layer includes: forming a dielectric material on the substrate layer, the thickness of the dielectric material layer is greater than half the width of the second opening; and removing part of the dielectric material layer until the surface of the mask layer is exposed.

The aforementioned method of manufacturing double trenches with different depths, wherein the depth of the first trench is 2 to 3 times that of the second trench.

In the aforementioned method of manufacturing double trenches with different depths, the material of the base includes a dielectric material. A structure for isolating elements is disposed in a substrate with a peripheral area and an array area. The above structure for isolating components includes a first isolation structure. The first isolation structure has at least a third-order profile and is located in the base of the peripheral region.

The purpose of the present invention and its technical problems can also be further realized by adopting the following technical measures.

The aforementioned structure for isolating devices further includes a second isolation structure located in the base of the array region, and the second isolation structure has at least a second-order profile.

In the aforementioned structure for isolating components, the first isolation structure and the second isolation structure each include a liner and a dielectric layer.

The aforementioned structure for isolating components, wherein the depth of the first isolation structure is 2-3 times the depth of the second isolation structure.

Compared with the prior art, the present invention has obvious advantages and beneficial effects.

With the above-mentioned technical solutions, the method for manufacturing semiconductor trenches and double trenches and the structure for isolating elements of the present invention have at least the following advantages and beneficial effects: Compared with this method, only one lithography process is required to fabricate double isolation structures or double trench structures with different depths, the method is simple and cost-effective, and can increase the competitive advantage. In addition, the double isolation structure of the present invention has different depths and can be applied to the peripheral area and the array area of the memory element respectively to meet the design requirements of the memory element.

To sum up, the present invention relates to a method for manufacturing semiconductor trenches and double trenches and a structure for isolating devices. The structure for isolating devices is disposed in a substrate having a peripheral region and an array region. The above structure for isolating components includes a first isolation structure and a second isolation structure. The first isolation structure has at least a third-order profile and is located in the base of the peripheral region. The second isolation structure has at least a second-order profile and is located in the base of the array region. The present invention has significant progress in technology, has obvious positive effects, and is a novel, progressive and practical new design.

The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and advantages of the present invention more obvious and understandable , the following preferred embodiments are specifically cited below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

1A to 1H are schematic cross-sectional views of a method for manufacturing a structure for isolating devices according to an embodiment of the present invention.

100: base 100′, 102″: surface

101: First zone/surrounding zone 102: Mask material layer

102a: mask layer 102': bottom surface

103: Second area/array area 104: Patterned photoresist layer

105: Bottom silicon oxide layer 106: First opening

107: Silicon nitride layer 108: Second opening

109: top silicon oxide layer 110: dielectric material layer

112: first spacer 114: first dielectric layer

116: depression 118: second spacer

120: The first ditch 122: The second ditch

124: Liner 126: Second dielectric layer

128: First isolation structure 130: Second isolation structure

W1: Thickness W2, W3: Width

D1, D2: Depth

Detailed ways

In order to further explain the technical means and effects of the present invention to achieve the intended purpose of the invention, the following in conjunction with the accompanying drawings and preferred embodiments, the semiconductor trench and double trench manufacturing method and the structure for isolating elements proposed according to the present invention Its specific implementation, methods, steps, structures, features and effects thereof are described in detail below.

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of preferred embodiments with reference to the drawings. Through the description of the specific implementation mode, a more in-depth and specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are only for reference and description, and are not used to explain the present invention. be restricted.

1A to 1H are schematic cross-sectional views of a method for manufacturing a structure for isolating devices according to an embodiment of the present invention.

Please refer to FIG. 1A , firstly, a substrate 100 is provided. The substrate 100 may be a semiconductor substrate such as a silicon substrate. The substrate 100 has a first region 101 and a second region 103 . When the present invention is applied to a memory device, the first area 101 is, for example, a peripheral area, and the second area 103 is, for example, an array area. For the sake of clarity, the peripheral area 101 and the array area 103 are taken as examples for illustration below.

Then, a mask material layer 102 and a patterned photoresist layer 104 are sequentially formed on the substrate 100 . The above-mentioned method for forming the mask material layer 102 includes performing chemical vapor deposition. The mask material layer 102 can be a single layer or a multi-layer structure. The material of the mask material layer 102 is selected from silicon oxide, silicon carbide, silicon nitride, silicon oxynitride and combinations thereof. In one embodiment, the mask material layer 102 may be a three-layer structure, including a bottom silicon oxide layer 105 , a silicon nitride layer 107 and a top silicon oxide layer 109 .

Next, as shown in FIG. 1B , using the patterned photoresist layer 104 as a mask, part of the mask material layer 102 is removed to form a mask layer 102 a. The mask layer 102 a has a first opening 106 exposing the substrate 100 of the peripheral region 101 and a second opening 108 exposing the substrate 100 of the array region 103 , wherein the first opening 106 is larger than the second opening 108 . The method for removing part of the mask material layer 102 includes dry etching. The dry etching method includes a break etching step, a main etching step and an over etching step. In one embodiment, during the over-etching step, the surface 100 ′ of the substrate 100 exposed by the first opening 106 and the second opening 108 is lower than the bottom surface 102 ′ of the mask layer 102 a, as shown in FIG. 1B . In another embodiment (not shown), the surface 101 ′ of the substrate 100 exposed by the first opening 106 and the second opening 108 may also be substantially equal to the bottom surface 102 ′ of the mask layer 102 a. Then, the patterned photoresist layer 104 is removed.

In the above embodiment, one first opening 106 and two second openings 108 are taken as an example for illustration, but the present invention is not limited thereto. In other words, the present invention does not limit the numbers of the first openings 106 and the second openings 108 .

After that, as shown in FIG. 1C , a dielectric material layer 110 is formed on the substrate 100 . The above method for forming the dielectric material layer 110 includes performing chemical vapor deposition. The material of the dielectric material layer 110 is, for example, silicon oxide or silicon nitride. In particular, the thickness W1 of the dielectric material layer 110 is greater than half of the width W2 of the second opening 108 , but less than half of the width W3 of the first opening 106 . That is to say, the thickness W1 of the dielectric material layer 110 needs to be thick enough to fill the second opening 108 but not fill the first opening 106 .

Then, as shown in FIG. 1D, part of the dielectric material layer 110 is removed until the surface 102" of the mask layer 102a is exposed, so as to form a first spacer 112 on the sidewall of the first opening 106, and a second The opening 108 is filled with the first dielectric layer 114. Then, the mask layer 102a and the first spacer 112 are used as a mask to form a recess 116 in the substrate 100 in the peripheral region 101. The above-mentioned removal of part of the dielectric material layer 110 and the method for forming the recess 116 include a two-step dry etching method, that is, the above-mentioned steps in FIG. 1D can be performed in the same reaction chamber.

Next, as shown in FIG. 1E , part of the first dielectric layer 114 is removed to form a second spacer 118 on the sidewall of the second opening 108 , and part of the first spacer 112 is removed to expose the top of the recess 116 . Angle A. The method for removing part of the first dielectric layer 114 and removing part of the first spacer 112 includes performing wet etching.

而第二沟渠122的深度D2为1400埃。上述形成第一沟渠120及第二沟渠122的方法包括进行干蚀刻法。After that, as shown in FIG. 1F , using the mask layer 102a, the first spacer 112 and the second spacer 118 as a mask, part of the substrate 100 is removed to form a first trench 120 in the substrate 100 in the peripheral region 101. And a second trench 122 is formed in the substrate 100 in the array region 103 . The first trench 120 has an at least third-order profile, and the second trench 122 has an at least second-order profile. The depth D1 of the first trench 120 is 2-3 times the depth D2 of the second trench 122 . In one embodiment, the depth D1 of the first trench 120 is 3500 Angstroms

The depth D2 of the second trench 122 is 1400 angstroms. The above method of forming the first trench 120 and the second trench 122 includes performing dry etching.

Then, as shown in FIG. 1G , the first spacer 112 and the second spacer 118 are removed. The method for removing the first spacer 112 and the second spacer 118 includes performing wet etching. Then, a lining layer 124 is formed on the surfaces of the first trench 120 and the second trench 122 . The material of the lining layer 124 is silicon oxide, for example. The above method of forming the liner 124 includes performing a thermal oxidation method. During the process of forming the liner 124 , sharp corners of the first trench 120 and the second trench 122 are also rounded.

Next, a second dielectric layer 126 is filled in the first trench 120 and the second trench 122 . The above method of filling the second dielectric layer 126 includes performing chemical vapor deposition. The material of the second dielectric layer 126 is, for example, silicon oxide. In one embodiment, the second dielectric layer 126 is made of the same material as the dielectric material layer 110 , such as silicon oxide. In another embodiment, the material of the second dielectric layer 126 is different from that of the dielectric material layer 110 .

It should be noted that the above steps of removing the first spacer 112 and the second spacer 118 and the step of forming the liner 124 can also be omitted, so that the second dielectric layer 126 is directly formed on the first spacer 112 and the second spacer. The spacer wall 118 is filled into the first ditch 120 and the second ditch 122 .

Afterwards, as shown in FIG. 1H , the second dielectric layer 126 outside the first trench 120 and the second trench 122 is removed by dry etching. Then, the mask layer 102a is removed by dry etching. So far, the fabrication of the first isolation structure 128 and the second isolation structure 130 is completed.

Based on the above, the structure used to isolate elements of the present invention is a double isolation structure with different depths (ie, the first isolation structure 128 and the second isolation structure 130 in FIG. 1H ), and only one lithography process is required in the manufacturing process. (The patterned photoresist layer 104 in FIG. 1A ), not only the process is simple but also the cost can be saved.

Next, the structure for isolating elements of the present invention will be described with the structure of FIG. 1H . The structure for isolating devices of the present invention is configured in the substrate 100 having the peripheral area 101 and the array area 103 . The above structure for isolating devices includes a first isolation structure 128 and a second isolation structure 130 . The first isolation structure 128 has an at least three-level profile and is located in the substrate 100 of the peripheral region 101 . The second isolation structure 130 has at least a second-order profile and is located in the substrate 100 of the array region 103 . The first isolation structure 128 and the second isolation structure 130 each include a liner 124 and a second dielectric layer 126 . The depth D1 of the first isolation structure 128 is 2-3 times the depth D2 of the second isolation structure 130 .

In the above embodiments, the trench manufacturing method is applied to form the structure for isolating devices, however, the present invention is not limited thereto. The above-mentioned trench manufacturing method can also be applied to any material layer that needs trenches of different depths. For example, the above-mentioned substrate is not limited to a semiconductor substrate, and may also be a dielectric material substrate, and the trench filling layer filled in the trench is not limited to a dielectric layer. In another embodiment, the double trench is formed in the dielectric layer, and the material layer filled in the trench can be a conductive layer, such as a metal layer. The metal layer has different thicknesses and can be used as a wire. Or called metal wire.

To sum up, the method of the present invention only needs one lithography process to produce double isolation structures or double trench structures with different depths, and does not need the conventional two lithography processes. The method is simple and cost-effective, and can increase Competitive Advantage. In addition, the double isolation structure of the present invention has different depths and can be applied to the peripheral area and the array area of the memory element respectively to meet the design requirements of the memory element.

The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Anyone familiar with this field Those skilled in the art, without departing from the scope of the technical solution of the present invention, may use the technical content disclosed above to make some changes or modify them into equivalent embodiments with equivalent changes, but as long as they do not depart from the technical solution of the present invention, the Technical Essence Any simple modifications, equivalent changes and modifications made to the above embodiments still fall within the scope of the technical solution of the present invention.

Claims (9)

1. a manufacture method for semiconductor irrigation canals and ditches, is characterized in that it comprises the following steps:

One substrate is provided, and this substrate has a surrounding zone and an array district;

In this substrate, form a cover curtain layer, this cover curtain layer has one first opening of this substrate that exposes this surrounding zone to the open air and exposes one second opening of this substrate of this array area to the open air;

Sidewall at this first opening forms one first clearance wall;

Take this cover curtain layer and this first clearance wall as cover curtain, in this substrate of this surrounding zone, form a depression;

Sidewall at this second opening forms one second clearance wall, and removes this first clearance wall of part to expose the drift angle of this depression; And

Take this cover curtain layer, this first clearance wall and this second clearance wall as cover curtain, remove this substrate of part, to form one first irrigation canals and ditches and form one second irrigation canals and ditches in this substrate of this surrounding zone in this substrate of this array area.

2. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, is characterized in that the first wherein said opening is greater than this second opening.

3. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, is characterized in that wherein the step that forms this first clearance wall at the sidewall of this first opening comprises:

In this substrate, form a dielectric materials layer, the thickness of this dielectric materials layer is greater than a half width of this second opening; And

Remove this dielectric materials layer of part, until expose the surface of this cover curtain layer, wherein remaining this dielectric materials layer forms this first clearance wall and fills up this second opening at the sidewall of this first opening.

4. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, it is characterized in that the first wherein said irrigation canals and ditches have the section at least three rank, and these second irrigation canals and ditches has at least section of second order.

5. the manufacture method of semiconductor irrigation canals and ditches according to claim 1, the degree of depth that it is characterized in that the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of these the second irrigation canals and ditches.

6. there is a manufacture method for two irrigation canals and ditches of different depth, it is characterized in that it comprises the following steps:

One substrate is provided, and this substrate has one first district and a Second Region;

In this substrate, form a cover curtain layer, this cover curtain layer has one first opening of this substrate that exposes this firstth district to the open air and exposes one second opening of this substrate of this Second Region to the open air;

Sidewall at this first opening forms one first clearance wall and in this second opening, fills up one first dielectric layer;

Take this cover curtain layer and this first clearance wall as cover curtain, in this substrate in this firstth district, form a depression;

Remove this first dielectric layer of part, form one second clearance wall with the sidewall at this second opening, and remove this first clearance wall of part to expose the drift angle of this depression; And

Take this cover curtain layer, this first clearance wall and this second clearance wall as cover curtain, remove this substrate of part, to form one first irrigation canals and ditches and form one second irrigation canals and ditches in this substrate in this firstth district in this substrate of this Second Region.

7. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, is characterized in that the first wherein said opening is greater than this second opening.

8. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, is characterized in that wherein the step that forms this first clearance wall and fill up this first dielectric layer in this second opening at the sidewall of this first opening comprises:

In this substrate, form a dielectric materials layer, the thickness of this dielectric materials layer is greater than a half width of this second opening; And

Remove this dielectric materials layer of part, until expose the surface of this cover curtain layer.

9. the manufacture method of two irrigation canals and ditches with different depth according to claim 6, the degree of depth that it is characterized in that the first wherein said irrigation canals and ditches is 2～3 times of the degree of depth of these the second irrigation canals and ditches.

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