CN102543714B - Method for improving uniformity of chemical mechanical planarization process for opening polycrystalline grid top - Google Patents

Abstract

Before the chemical mechanical planarization process for a silicon oxide layer, a one-step silicon oxide etching process is adopted, so that the height difference between the silicon oxide layer between adjacent polycrystalline grids and the silicon oxide layer right above the polycrystalline grids is greatly reduced, therefore, the influence of the smaller height difference on the chemical mechanical planarization process is greatly reduced, the height difference cannot be transmitted in the grinding process, the depression in the silicon oxide layer is greatly reduced, the flat silicon oxide surface is obtained, the possibility of metal residue existing later is eliminated, and the electrical property and the yield of a device are improved.

Description

Method for Improving Uniformity of Chemical Mechanical Planarization Process for Opening Polycrystalline Gate Top

technical field

The invention relates to a process method for manufacturing a semiconductor device, in particular to a method for improving the uniformity of a chemical mechanical planarization process for opening a polycrystalline gate top.

Background technique

The successful application of high-K/metal gate engineering on the 45nm technology node makes it an indispensable key modular engineering for technology nodes below 30nm. Currently, only Intel, which adheres to the high-K/gate last route, has achieved success in mass production at the 45nm and 32nm technology nodes. In recent years, Samsung, TSMC, Infineon and other industry giants following the IBM Industry Alliance have also shifted their previous research and development focus from high-K/gate first to gate last.

For the gate last project, the development of the chemical mechanical planarization (CMP) process is considered the most challenging in the industry. In the gate last project, a CMP process is required to grind off the silicon oxide and silicon nitride isolation layer on the top of the poly gate, and stop grinding after exposing the top of the poly gate. This step is called opening the poly gate. The CMP on the top of the gate, that is, polyopening polish nitrogen CMP, referred to as POP CMP; then, the polycrystalline gate prepared by the traditional process is dug out and filled with metal to form a metal gate, and then one or more chemical mechanical steps for the metal gate are required. Planarization, that is, metal gate CMP, finally obtains a high K/metal gate structure.

POP CMP includes two steps of CMP, one is CMP of silicon oxide, and the other is CMP of silicon nitride, and these two steps of CMP have high requirements on the grinding uniformity (within in die uniformity) inside the wafer chip. Among them, the grinding uniformity control of the first silicon oxide CMP process is the most critical. Referring to accompanying drawing 1, because device density is bigger, and the height of polycrystalline gate 13 is usually 1000-1800 This results in that after the silicon oxide 11 is deposited, the thickness difference H between the silicon oxide directly above the polycrystalline gate 13 and the silicon oxide between the adjacent polycrystalline gates 13 can reach 1000-4000 even bigger. If the conventional silicon oxide CMP technology is adopted, such a large thickness drop cannot be effectively eliminated, and this drop will be transmitted to the end of the silicon oxide CMP as the CMP process progresses, which results in gaps between the polysilicon gates 13. Silicon oxide 11 has depressions. Although there is CMP for silicon nitride 12 afterwards, it is also difficult to repair the depression of silicon oxide 11 in this step of CMP, and due to the difference in material selection ratio, the depression of silicon oxide 11 may be further enlarged to form the final depression 14, See Figure 2. The larger silicon oxide recess 14 will cause a huge obstacle to the CMP process of the metal gate, and it is easy to form metal residues between the polycrystalline gates 13 , thus causing short circuit of the device.

In order to meet the high requirements of POP CMP on the internal grinding uniformity of the wafer chip, it is necessary to develop a new process method to eliminate the dielectric depression between the gates, thereby improving the reliability of the device.

Contents of the invention

The invention adopts the method of combining application of silicon oxide etching and silicon oxide CMP to improve the uniformity of chemical mechanical planarization process for opening polycrystalline gate top.

The invention provides a method for improving the uniformity of the chemical mechanical planarization process on the top of the polycrystalline gate, including:

providing a substrate, and a polycrystalline gate on the substrate;

depositing a silicon nitride layer on the substrate, and patterning the silicon nitride layer so that the silicon oxide layer covers the top and sidewalls of the polycrystalline gate;

depositing a silicon oxide layer on the substrate, the silicon oxide layer at least completely filling the gaps between the polycrystalline gates;

performing a planarization process on the silicon oxide layer by using a first chemical mechanical planarization process until the silicon nitride layer covering the top of the polycrystalline gate is exposed;

performing a planarization treatment on the exposed silicon nitride layer by using a second chemical mechanical planarization process until the top of the polycrystalline gate is exposed;

Wherein, before the first chemical mechanical planarization process, the following steps are performed:

After depositing the silicon oxide layer, a photoresist is coated on the substrate and exposed through a photomask to form a photoresist pattern. The photoresist pattern exposes the The silicon oxide layer on the top covers the silicon oxide layer between adjacent polycrystalline gates;

Etching the exposed silicon oxide layer above the top of the polycrystalline gate by using an etching process, the etching depth of the etching process is not greater than that of the oxide layer above the top of the polycrystalline gate the thickness of the silicon layer;

After the etching process, the height difference between the upper surface of the silicon oxide layer located above the top of the polycrystalline gate and the upper surface of the silicon oxide layer located between adjacent polycrystalline gates was reduced;

The photoresist pattern on the substrate is removed by using a glue-removing process.

In the method of the present invention, the main etching gas in the etching process is a fluorocarbon-based etching gas; the fluorocarbon-based etching gas includes CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F ₈ , one or more of CH ₂ F ₂ , CH ₃ F, and C ₅ F ₈ ;

In the method of the present invention, the auxiliary added gas in the etching process includes one or more of CO, O ₂ , Ar, He, SF ₆ , N ₂ ;

In the method of the present invention, the first chemical mechanical planarization is silicon oxide CMP-based chemical mechanical planarization;

In the method of the present invention, the polishing liquid in the first chemical mechanical planarization process includes an alkaline _SiO2 -based polishing liquid or an alkaline CeO2 _- based polishing liquid;

In the method of the present invention, the polishing pad in the first chemical mechanical planarization process includes a hard polishing pad or a soft polishing pad.

In the method of the present invention, the second chemical mechanical planarization is chemical mechanical planarization based on silicon nitride CMP.

The advantage of the present invention is that: before the chemical mechanical planarization process for the silicon oxide layer, a one-step silicon oxide etching process is adopted, so that the silicon oxide layer between adjacent polycrystalline gates and the silicon oxide layer directly above the polycrystalline gate The height difference is greatly reduced, therefore, the impact of the small height difference on the chemical mechanical planarization process will be greatly reduced, so that the height difference will not be passed on during the grinding process, greatly reducing the depression in the silicon oxide layer , a flat silicon oxide surface is obtained, which eliminates the possibility of subsequent metal residues, thereby improving the electrical performance and yield of the device.

Description of drawings

Figure 1 is a schematic diagram of the device structure before the conventional silicon oxide CMP process;

Figure 2 is a schematic diagram of the device structure after the conventional silicon nitride CMP process;

Fig. 3 shows the device structure after the present invention deposits silicon oxide layer;

Fig. 4 has shown the process that the present invention forms photoresist pattern and carries out etching;

Fig. 5 has shown the silicon oxide layer surface of the present invention through etching;

Figure 6 shows that the device after silicon oxide CMP has a flat surface;

Figure 7 shows that the device after silicon nitride CMP has a flat surface.

detailed description

The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in combination with exemplary embodiments.

First, referring to FIG. 3 , a substrate 1 is provided, and a polycrystalline gate 2 is provided on the substrate 1 . The substrate 1 can be various substrates common in semiconductor devices, such as silicon, gallium arsenide, etc.; the polycrystalline gate 2 is formed by traditional methods, and has a height, generally 1000-1500 Next, a silicon nitride layer 3 is deposited on the surface of the substrate 1 , and the silicon nitride layer 3 is patterned to cover the top and sidewalls of the polycrystalline gate 2 . Next, a silicon oxide layer 4 is deposited. The silicon oxide layer 4 has a thickness such that it can at least completely fill the gaps between the polysilicon gates 2 . Since the polycrystalline gate 2 has a height, the silicon oxide layer 4 has a protruding portion 41 located above the top of the polycrystalline gate 2 . There is a height difference h ₁ between the upper surface of the protruding portion 41 and the upper surface of the silicon oxide layer 4 between the polycrystalline gate 2 , that is, the protruding height of the protruding portion 41 , and the value of the height difference h ₁ is usually not less than that of the polycrystalline The height of grid 2 is generally 1000-4000 Depositing the silicon nitride layer 3 and the silicon oxide layer 4 may adopt processes such as CVD, PVD, and ALD.

After the deposition of the silicon oxide layer 4 is completed, the entire substrate 1 is coated with photoresist; by selecting a suitable photomask, exposing and developing, a photoresist pattern 5 is formed, and the photoresist pattern 5 covers the adjacent substrates. The silicon oxide layer 4 between the polycrystalline gates 2 exposes the protruding portion 41 of the silicon oxide layer 4 , see FIG. 4 .

Using an etching process, select appropriate silicon oxide etching conditions and etching time according to the value of the height difference _h1 , and perform etching treatment on the exposed protruding part 41 of the silicon oxide layer 4, and the etching depth is not greater than the height difference h ₁ , to reduce the height difference, see Figure 4, the arrow shows the direction of etching and reducing the silicon oxide layer 4. The etching process can adopt anisotropic dry etching process, and the main etching gas is fluorocarbon-based etching gas, including CF ₄ , CHF ₃ , C ₂ F ₆ , C ₄ F ₈ , CH ₂ F ₂ , CH ₃ F, one or more of C ₅ F ₈ , the auxiliary added gas includes one or more of CO, O ₂ , Ar, He, SF ₆ , N ₂ . After this etching process, the height difference h ₁ between the upper surface of the protruding portion 41 and the upper surface of the silicon oxide layer 4 between the polycrystalline gates 2 is reduced to h ₂ , see FIG. 5 . Since the edge of the protruding portion 41 is close to the photoresist, the etching speed of the edge of the protruding portion 41 will be lower than the etching speed of the central portion of the protruding portion 41 due to the influence of the photoresist, so that the reduced speed of the central portion of the protruding portion 41 will be Therefore, at the end of the etching process, there will be a concave surface on the top of the protruding portion 41 . Subsequently, the photoresist pattern 5 is removed through a stripping process. Generally, the photoresist pattern 5 is removed by wet etching or dry etching, and the entire substrate 1 is dried; in order to ensure the flatness of the unetched silicon oxide layer 4, the adhesive removal process The conditions should not have a damaging effect on the silicon oxide layer 4 .

Next, the first chemical mechanical planarization is performed. The first chemical mechanical planarization is based on silicon oxide CMP, and the silicon oxide layer 4 is planarized to expose the silicon nitride layer 3 covering the top of the polycrystalline gate 2. , see accompanying drawing 6. The polishing liquid used in the first chemical mechanical planarization process includes an alkaline SiO ₂ -based polishing liquid or an alkaline CeO ₂ -based polishing liquid, and the polishing pad used includes a hard polishing pad or a soft polishing pad. Since the value of the height difference h2 is small, this has little impact _on the first chemical mechanical planarization step. During the grinding process, the height difference h2 in the silicon oxide layer ₄ will not be transferred to the on the surface of the silicon oxide layer 4 between the polycrystalline gates 2, thereby avoiding the generation of recesses, and making the remaining silicon oxide layer 4 have a flat surface.

Subsequently, the second chemical mechanical planarization is performed. The second chemical mechanical planarization is based on silicon nitride CMP, and the silicon nitride layer 3 is planarized to expose the top of the polycrystalline gate 2, and the device has For flat surfaces, see Figure 6.

In the present invention, before the first chemical mechanical planarization, an etching process is used to etch the silicon oxide layer, which reduces the large height difference existing in the silicon oxide layer, so that the first chemical mechanical planarization During the grinding process, the original large height drop will not be transferred to the remaining silicon oxide layer, and a device with a flat surface is obtained, thereby improving the electrical performance and yield of the device.

Although the present invention has been described with reference to the above exemplary embodiments, those skilled in the art can know that various suitable changes and equivalents can be made to the technical solutions of the present invention without departing from the scope of the present invention. In addition, many modifications, possibly suited to a particular situation or material, may be made from the disclosed teaching without departing from the scope of the invention. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode for carrying out this invention, but that the disclosed device structures and methods of making the same will include all embodiments falling within the scope of the invention .

Claims (8)

1. a polysilicon gate top CMP process uniformity method is opened in raising, comprising:

Substrate is provided, and is positioned at the polysilicon gate on described substrate;

Deposited silicon nitride layer on described substrate, and carries out patterning to described silicon nitride layer, makes described silicon nitride layer cover top and the sidewall of described polysilicon gate;

Silicon oxide layer deposited is on described substrate, and described silicon oxide layer fills the gap between described polysilicon gate at least completely;

Adopt the first CMP process, planarization is carried out to described silicon oxide layer, until expose the described silicon nitride layer covering described polysilicon gate top;

Adopt the second CMP process, planarization is carried out to the described silicon nitride layer exposed, until expose the top of described polysilicon gate;

It is characterized in that: before described first CMP process, carry out following steps:

After the described silicon oxide layer of deposition, apply photoresist over the substrate, exposed by photomask, form a photoetching agent pattern, described photoetching agent pattern exposes the described silicon oxide layer being positioned at described polysilicon gate over top, and covers the silicon oxide layer between adjacent described polysilicon gate;

Adopt an etching technics, etch the described silicon oxide layer being positioned at described polysilicon gate over top exposed, the etching depth of described etching technics is not more than the thickness of the described silicon oxide layer being positioned at described polysilicon gate over top;

After described etching technics, the height fall between the upper surface of the described silicon oxide layer of described polysilicon gate over top and the upper surface of the described silicon oxide layer between adjacent described polysilicon gate is reduced;

Adopt degumming process, remove the described photoetching agent pattern on described substrate.

2. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, the main etching gas in described etching technics is the fluorine-based etching gas of carbon.

3. as claimed in claim 2 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, the fluorine-based etching gas of described carbon comprises CF ₄, CHF ₃, C ₂f ₆, C ₄f ₈, CH ₂f ₂, CH ₃f, C ₅f ₈in one or more.

4. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, the auxiliary interpolation gas in described etching technics comprises CO, O ₂, Ar, He, SF ₆, N ₂in one or more.

5. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, described first chemical-mechanical planarization is the chemical-mechanical planarization based on silica CMP.

6. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, in the method for the invention, the polishing fluid in described first CMP process comprises alkaline SiO ₂base lapping liquid or alkaline CeO ₂base lapping liquid.

7. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, the polishing pad in described first CMP process comprises hard polishing pad or soft polishing pad.

8. as claimed in claim 1 raising opens polysilicon gate top CMP process uniformity method, and it is characterized in that, described second chemical-mechanical planarization is the chemical-mechanical planarization based on silicon nitride CMP.