CN102540598B - Pixel array substrate and display panel - Google Patents

Abstract

The invention discloses a pixel array substrate and a display panel. The pixel array substrate comprises a substrate, a plurality of scanning line groups, a plurality of data lines and a plurality of pixel structures. The scanning line group is configured on the substrate, and the data line is intersected with the scanning line group. The pixel structures are connected to the scanning line group and the data line, wherein each pixel structure comprises an active element group, a first pixel electrode, a second pixel electrode and a connecting electrode. The first pixel electrode is positioned between the second pixel electrode and the nth group of scanning line groups. The connecting electrode is positioned on one side of the first pixel electrode adjacent to one of the data lines, and the second pixel electrode is electrically connected to the active element group through the connecting electrode, wherein the connecting electrode, the first pixel electrode and the second pixel electrode are the same film layer.

Description

Pixel array substrate and display panel

technical field

The present invention relates to a pixel structure and a display panel, and in particular to a pixel structure and a display panel applicable to stereoscopic display technology.

Background technique

The performance requirements of the market for LCD panels are high contrast ratio, no gray scale inversion, little color shift, high luminance, high color richness, Features such as high color saturation, fast response and wide viewing angle. At present, the technologies that can meet the requirement of wide viewing angle include twist nematic (TN) liquid crystal plus wide viewing film (wide viewing film), in-plane switching (IPS) liquid crystal display panel, fringe field Switching (fringe field switching) liquid crystal display panels, multi-domain vertical alignment (multi-domain vertically aligned, MVA) liquid crystal display panels, etc.

However, in addition to high image resolution and high color saturation, displays capable of displaying stereoscopic images have also been developed in order to satisfy users' demands for viewing real images. Stereoscopic display technologies can be broadly classified into stereoscopic, in which viewers need to wear specially designed glasses to watch, and auto-stereoscopic, in which viewers directly watch with naked eyes. Glasses-type stereoscopic displays can be divided into color filter glasses, polarizing glasses, and shutter glasses. The working principle of the glasses-type stereoscopic display is mainly to use the display to send left and right eye images with special information, and through the selection of the head-mounted glasses, the left and right eyes can see the left and right eye images respectively to form a stereoscopic vision.

For the viewer, when wearing glasses to watch the 3D image, the viewing angle of the 3D image is highly dependent, so that the position of the viewer is limited when viewing the 3D display. Therefore, how to reduce the viewing angle dependence of the stereoscopic display to increase the viewable viewing angle of the observer will be an important point in the development of the stereoscopic display.

Contents of the invention

The object of the present invention is to provide a pixel array substrate, in which existing opaque structures are disposed between adjacent pixel structures, so as to increase the display aperture ratio of the pixel array substrate.

Another object of the present invention is to provide a display panel with a stereoscopic display function and an ideal display aperture ratio.

To achieve the above purpose, the present invention provides a pixel array substrate, including a substrate, a plurality of scan line groups, a plurality of data lines and a plurality of pixel structures. The scanning line group is arranged on the substrate, and the data line intersects with the scanning line group. The pixel structure is connected to the scan line group and the data line, wherein each pixel structure includes an active element group, a first pixel electrode, a second pixel electrode and a connection electrode. The active element group is connected to the nth scan line group and the mth data line, wherein both n and m are positive integers. The first pixel electrode is electrically connected to the active element group. The second pixel electrode is electrically connected to the active element group, and the first pixel electrode is located between the second pixel electrode and the nth scan line group. The connection electrode is located on the side of the first pixel electrode adjacent to one of the data lines, and the second pixel electrode is electrically connected to the active element group through the connection electrode, wherein the connection electrode, the first pixel electrode and the second pixel electrode are the same film layer.

The present invention further proposes a display panel, which includes the pixel array substrate described above, an opposite substrate, and a polymer stable alignment liquid crystal layer. The opposite substrate is opposite to the pixel array substrate. The polymer stabilized alignment liquid crystal layer is disposed between the pixel array substrate and the opposite substrate.

Based on the above, in the present invention, the opaque elements in the pixel array substrate are arranged on the edge of each pixel structure, and the corresponding pixel electrodes are connected to the active elements by connecting electrodes. Therefore, in the display panel with the pixel array substrate of the present invention, even if a black matrix is arranged between each pixel structure, the original display aperture ratio will not be affected. In other words, the pixel array substrate and the display panel of the present invention can have an ideal display aperture ratio, and the occurrence of cross talk can be avoided when the display panel performs stereoscopic display.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;

2 is a schematic top view of a pixel array substrate according to an embodiment of the present invention;

3 is a schematic top view of a black matrix according to an embodiment of the present invention;

FIG. 4 is a pixel structure of another embodiment of the present invention;

5A and FIG. 5B are schematic cross-sectional views along the section line I-I' and section line II-II' of FIG. 4 according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a pixel structure according to another embodiment of the present invention;

7A and FIG. 7B are schematic cross-sectional views along the section line III-III' and section line IV-IV' of FIG. 6 according to another embodiment of the present invention;

8 and 9 are schematic diagrams of pixel structures in two further embodiments of the present invention.

Description of main component symbols

10: Display panel

12: Pixel array substrate

12A, 22A: Substrate

14: Facing substrate

16: polymer stabilized alignment type liquid crystal layer

18: Patterned phase retarder

18L, 18R: delay zone

100, 100L, 100R, 200, 300, 400, 500: pixel structure

102, 202: active component group

104: first pixel electrode

106, 306: the second pixel electrode

108A, 308A: connection electrodes

108B, 308B: coupling electrodes

110, 210: scan line group

120: data line

132: first capacitor electrode

134: second capacitor electrode

136: The third capacitance electrode

140: Black Matrix

142: Transverse section

144: Vertical section

202A: first active element

202B: second active element

212: The first scan line

214: Second scan line

250: color filter layer

C: channel layer

D1, D2: drain

I-I', II-II', III-III', IV-IV': broken line

I1, I2: insulating layer

S1, S2: Slits

T: overlap width

VA, VB: Perspective

W1: first contact opening

W2: second contact opening

Detailed ways

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention. Referring to FIG. 1 , the liquid crystal display panel 10 includes a pixel array substrate 12 , an opposite substrate 14 , a polymer stabilized alignment liquid crystal layer 16 and a patterned phase retarder 18 . The pixel array substrate 12 is disposed opposite to the opposite substrate 14 , and the polymer stabilized alignment liquid crystal layer 16 is disposed between the pixel array substrate 12 and the opposite substrate 14 . Pixel Array Substrate The substrate 12 includes, for example, a substrate 12A and a plurality of pixel structures 100 arranged in an array on the substrate 12A. In addition, the patterned phase retarder 18 is disposed on the opposite substrate 14 so that the display panel 10 has a stereoscopic display function. That is to say, when the patterned phase retarder 18 is disposed, the display panel 10 has, for example, a stereoscopic display function. However, the display panel 10 does not need to be configured with the patterned phase retarder 18 , but only provides a two-dimensional (2D) display function.

Specifically, when the display panel 10 performs stereoscopic display, some of the pixel structures 100 , such as the pixel structure 100L, display images for the left eye, while other pixel structures, such as the pixel structure 100R, display images for the right eye. The patterned phase retarder 18 has a plurality of retardation regions 18L, 18R, wherein each of the retardation regions 18L, 18R provides a specific phase retardation effect.

When watching the picture displayed on the display panel 10 , the viewer, for example, wears polarized glasses. The image displayed by the pixel structure 100 will have the first polarization state after being affected by the retardation region 18L, and will be seen by the left eye of the observer through the left lens of the polarized glasses. The image displayed by the pixel structure 100 will have the second polarization state after being affected by the retardation region 18R, and will be seen by the observer's right eye through the right lens of the polarized glasses. In this way, the left and right eyes of the viewer can receive different images and watch the stereoscopic display screen.

Generally speaking, the pixel structure 100L is used to display the image for the left eye, and the pixel structure 100R is used for displaying the image for the right eye. When the viewer watches the picture presented by the display panel 10 from the viewing angle VA, the left-eye image displayed by the pixel structure 100L can pass through the delay region 18L so that the left eye can indeed only receive the left-eye image displayed by the pixel structure 100L. However, when the viewing angle VA of the observer increases to the viewing angle VB, the right-eye image displayed by the pixel structure 100R can also pass through the retardation region 18L. Therefore, the viewer's left eye will receive the right-eye image displayed by the pixel structure 100R, resulting in a bad display effect (also generally referred to as cross talk). This is the main reason why the stereoscopic display technology is highly dependent on the viewing angle. Therefore, this embodiment proposes a pixel structure 100 as shown in FIG. 2 .

FIG. 2 is a schematic top view of a pixel array substrate according to an embodiment of the present invention. Referring to FIG. 2 , the pixel array substrate 12 includes a substrate 12A, a plurality of pixel structures 100 , a plurality of scan line groups 110 and a plurality of data lines 120 . The scan line group 110 is disposed on the substrate 12A, and the data line 120 intersects with the scan line group 110 . In this embodiment, the scan line group 110 is described as a single wire as an example, but the invention is not limited thereto. The pixel structure 100 is connected to the scanning line group 110 and the data line 120, wherein each pixel structure 100 includes an active element group 102, a first pixel electrode 104, a second pixel electrode 106, a connection electrode 108A and a coupling electrode 108B .

In the pixel array substrate 12 , the active device group 102 of each pixel structure 100 is connected to the nth scan line group 110 and the mth data line 120 , wherein n and m are both positive integers. In addition, in this embodiment, the active element group 102 is described by taking a double-drain thin film transistor as an example. The first pixel electrode 104 is electrically connected to the active element group 102 . The second pixel electrode 106 is electrically connected to the active element group 102 , and the first pixel electrode 104 is located between the second pixel electrode 106 and the corresponding scan line group 110 . The connecting electrode 108A is located on one side of the first pixel electrode 104 adjacent to one of the data lines 120 , and the coupling electrode 108B is located on the other side of the first pixel electrode 104 adjacent to the other data line 120 . In addition, the second pixel electrode 106 is electrically connected to the active element group 102 through the connection electrode 108A, wherein the connection electrode 108A, the coupling electrode 108B, the first pixel electrode 104 and the second pixel electrode 106 are the same film layer.

It is worth mentioning that in this embodiment, the connection electrode 108A and the coupling electrode 108B are respectively located on two opposite sides of the first pixel electrode 104 for illustration, and the connection electrode 108A and the coupling electrode 108B are electrically connected to the second pixel electrode 106 . However, the coupling electrode 108B can be selectively omitted from the pixel structure 100 , that is, in other embodiments, the pixel structure 100 does not need to be configured with the coupling electrode 108B.

In addition, in order to form the polymer stabilized alignment type liquid crystal layer 14 in the display panel 10 by polymer stabilized alignment technology, the first pixel electrode 104 of each pixel structure 100 has a plurality of slits S1, for example, and the second pixel electrode 106 has The plurality of slits S2, for example, the slits S1 and S2 respectively define four alignment directions. In this way, the polymer-stabilized alignment liquid crystal layer 14 in the display panel 10 can exhibit multi-field alignments to achieve a display effect with a wide viewing angle. But in another embodiment, the liquid crystal layer is not limited to the polymer stabilized alignment type liquid crystal, that is, any suitable liquid crystal can be determined according to the designer's requirement.

Furthermore, the pixel array substrate 12 further includes a first capacitor electrode 132 and a second capacitor electrode 134 , which are respectively located under the first pixel electrode 104 and the second pixel electrode 106 . That is to say, the first capacitor electrode 132 is located between the first pixel electrode 104 and the substrate 12A, and the second capacitor electrode 134 is located between the second pixel electrode 106 and the substrate 12A. The first capacitor electrode 132 can form a storage capacitor with the first pixel electrode 104 , and the second capacitor electrode 134 can form a storage capacitor with the second pixel electrode 106 .

In this embodiment, the scan line group 110 is an opaque element located at the edge of the pixel structure 100 . When the pixel array substrate 12 shown in FIG. 2 is applied to the display panel 10 , the scanning line group 110 corresponds to the boundary between two adjacent pixel structures 100 . Therefore, when the observer watches from the viewing angle VB, the observer's left eye will not see the right-eye image displayed by the pixel structure 100R. That is to say, the scan line group 110 provides a light-shielding effect and helps to avoid the phenomenon of cross talk.

FIG. 3 is a schematic top view of a black matrix according to an embodiment of the present invention. Please refer to FIG. 2 and FIG. 3 at the same time. In one embodiment, a black matrix 140 as shown in FIG. The horizontal portion 142 corresponds to, for example, the scan line group 110 shown in FIG. 2 , and the vertical portion 144 corresponds to, for example, the data line 120 shown in FIG. 2 . That is to say, the pixel array substrate 12 may be a black matrix on array (black matrix on array, BOA) design.

The black matrix 140 can provide a good light-shielding effect, so when the pixel array substrate 12 is applied to the display panel 10 in FIG. 1 , it is helpful to improve the display contrast of the display panel 10 . In addition, the black matrix 140 at least partially overlaps the scan line group 110 and the data line 120 , and the scan line group 110 and the data line 120 are originally opaque elements. Therefore, the arrangement of the black matrix 140 will not cause loss of display aperture ratio. That is to say, the configuration of the black matrix 140 can make the display panel 10 in FIG. 1 have an ideal display quality without losing the display aperture ratio. In addition, in other embodiments, the black matrix 140 can also be selectively disposed on the opposite substrate 14 of the display panel 10 .

The pixel structure 100 of the above embodiment is only for illustration, and is not intended to limit the present invention. For example, FIG. 4 shows a pixel structure according to another embodiment of the present invention. Referring to FIG. 4 , the pixel structure 200 is connected to the scan line group 210 and the data line 120 , for example. The scan line group 210 includes a first scan line 212 and a second scan line 214 adjacent to each other. In addition, the pixel structure 200 includes an active element group 202, a first pixel electrode 104, a second pixel electrode 106, a connecting electrode 108A, and a coupling electrode 108B, wherein the active element group 202 includes a first active element 202A and a first Two active components 202B. One end of the second active element 202B is, for example, coupled as a capacitor with a third capacitor electrode 136 , wherein the third capacitor electrode 136 is located between the first scan line 212 and the second scan line 214 .

This embodiment can also be applied to the display panel 10 in FIG. 1 , so the first pixel electrode 104 and the second pixel electrode 106 can have a plurality of slits S1 and S2 respectively to provide different alignment directions to achieve a display effect with a wide viewing angle and The formation of the polymer-stabilized alignment type liquid crystal layer 16 is realized. Of course, the first capacitor electrode 132 and the second capacitor electrode 134 may be disposed under the first pixel electrode 104 and the second pixel electrode 106 .

Although this embodiment only shows one set of scan line groups 210 and one pixel structure 200 , when applied to the display panel 10 , there are multiple scan line groups 210 and pixel structures 200 . Multiple sets of scan line groups 210 may be arranged in parallel, and the data lines 120 are interleaved with these scan line groups 210 . A plurality of pixel structures 200 are arranged in an array and connected to corresponding scan line groups 210 and data lines 120 . In addition, among the multiple scan line groups 210 , the second scan line 214 of the nth scan line group 210 may be electrically connected to the first scan line 212 of the n+1th scan line group 210 . In another embodiment, the second scan line 214 of the nth scan line group 210 may be electrically connected to the first scan line 212 of the n+2 scan line group 210; that is, the nth scan line group The second scan line 214 of 210 may be electrically connected to the first scan line 212 of the n+i-th scan line group 210, and i is a positive integer.

As far as the pixel structure 200 is connected to the nth scan line group 210 and the mth data line 120, the first active element 202A is connected to the corresponding first scan line 212, the corresponding data line 120, the first pixel electrode 104 and the second pixel electrode 106 , and the second active element 202B is connected to the corresponding second scanning line 214 and the second pixel electrode 106 . The first active element 202A can be a double-drain thin film transistor, which has two drains D1, D2 and the first pixel electrode 104 is electrically connected to the drain D1, and the second pixel electrode 106 is electrically connected to the drain through the connection electrode 108A. Pole D2. In addition, the second active element 202B can be connected to the second pixel electrode 106 through the drain D2 of the first active element 202A and the connection electrode 108A.

The second scan line 214 of the nth scan line group 210 may be electrically connected to the first scan line 212 of the n+1th scan line group 210 . Therefore, the second active element 202B of each pixel structure 200 is turned on when the next row of pixel structures 200 is turned on, so as to redistribute the voltages of the first pixel electrode 104 and the second pixel electrode 106 to achieve a more ideal display quality. In this way, even if the first pixel electrode 104 and the second pixel electrode 106 are subjected to different capacitive coupling effects, they can still present an ideal display gray scale.

5A and FIG. 5B are schematic cross-sectional views along the section line I-I' and section line II-II' of FIG. 4 according to an embodiment of the present invention, respectively. Please refer to FIG. 4, FIG. 5A and FIG. 5B at the same time. The scan line group 210, the data line 120 and the pixel structure 200 are disposed on the substrate 22A, for example, wherein a part 122 of the data line 120 is extended to form the first active element 202A. source. In addition, the insulating layer I1 , the insulating layer I2 and the channel layer C are further disposed on the substrate 22A. The insulating layer I1 covers the first scanning line 212 and the second scanning line 214, the channel layer C is disposed on the insulating layer I1 and above the first scanning line 212, wherein a part 122 of the data line 120 is connected to the first active The drains D1 and D2 of the device 202A are disposed on the channel layer C. The insulating layer I2 covers the scan line group 210 , the data line 120 and the active element group 202 of each pixel structure 200 .

In this embodiment, the insulating layer I2 has a first contact opening W1 and a second contact opening W2. The first pixel electrode 104 is electrically connected to the first active element 202A through the first contact opening W1 , and the connecting electrode 108A is electrically connected to the first active element 202A and the second active element 202B through the second contact opening W2 . In addition, the first contact opening W1 and the second contact opening W2 are located between the first scan line 212 and the second scan line 214 of the scan line group 210 in this embodiment. In other embodiments, the first contact opening W1 and the second contact opening W2 can be arranged at any position between the first pixel electrode 104 of each pixel structure 200 and the second pixel electrode 106 of the previous pixel structure 200 . For example, the first contact opening W1 and the second contact opening W2 may be located between the first pixel electrode 104 of a pixel structure 200 and the second scan line 214 of the corresponding scan line group 210 . The positions of the first contact opening W1 and the second contact opening W2 are areas where display cannot be performed originally. Therefore, the configuration of the first contact opening W1 and the second contact opening W2 will not affect the display aperture ratio of the pixel structure 200 . In other words, in this embodiment, there is no need to configure contact openings in the configuration areas of the first pixel electrode 104 and the second pixel electrode 106, and there is no need to configure contact openings between the first pixel electrode 104 and the second pixel electrode 106 of the same pixel structure 200. Any contact openings are provided between them to increase the display aperture ratio, but the present invention is not limited thereto. In other implementation manners, specific contact openings can be optionally provided in the configuration areas of the first pixel electrode 104 and the second pixel electrode 106 to achieve a desired connection relationship.

FIG. 6 shows a pixel structure according to yet another embodiment of the present invention, and FIG. 7A and FIG. 7B are respectively drawn along section line III-III' and section line IV-IV' of FIG. 6 according to another embodiment of the present invention. The schematic cross-section shown. Referring to FIG. 6 , FIG. 7A and FIG. 7B , the pixel structure 300 of this embodiment is substantially the same as the pixel structure 200 of FIG. 4 . Therefore, the element symbols of some components in this embodiment are the same as those in FIG. 4 , FIG. 5A and FIG. 5B , and will not be repeated here. The main difference between this embodiment and the previous embodiments is that a color filter layer 250 is further disposed on the substrate 22A. That is to say, this embodiment is used to illustrate the implementation of the color filter layer on the array substrate (color filter on array, COA). Of course, in other embodiments, the arrangement sequence of the color filter layer 250 and other components may be different to form an array on color filter substrate (array on color filter, AOC) design. In addition, the second pixel electrode 306 , the connection electrode 308A and the coupling electrode 308B overlap the data line 120 by an overlapping width T, for example.

In order to provide ideal color saturation, the color filter layer 250 preferably has a certain thickness. In this embodiment, the first pixel electrode 104 , the second pixel electrode 106 , the connecting electrode 108A and the coupling electrode 108B are disposed on a side of the color filter layer 250 away from the substrate 22A. Therefore, the areas of the first contact opening W1 and the second contact opening W2 must be appropriately enlarged to ensure that the connecting electrode 108A is electrically connected to the drain D2 and the first pixel electrode 104 is electrically connected to the drain D1 . If the first contact opening W1 and the second contact opening W2 are located within the arrangement area of the first pixel electrode 104 and the second pixel electrode 106 , the display aperture ratio will be adversely affected. Therefore, the first contact opening W1 and the second contact opening W2 of this embodiment are located in the area where display will not be performed originally, that is, between the first scanning line 212 and the second scanning line 214, which will not affect the display opening. rate has a negative impact. Even if the configuration areas required by the first contact opening W1 and the second contact opening W2 increase, the pixel structure 200 of this embodiment can still have an ideal display aperture ratio.

In addition, since the color filter layer 250 is thicker, the coupling effect of the data line 120 on the second pixel electrode 306 , the connecting electrode 308A and the coupling electrode 308B is weaker than that of the embodiment shown in FIG. 4 . Therefore, the second pixel electrode 306 , the connecting electrode 308A and the coupling electrode 308B can overlap the data line 120 by the overlapping width T, which is used to expand the display area of the pixel structure 300 . On the whole, although the present embodiment requires larger areas of the first contact opening W1 and the second contact opening W2 , it can still maintain an ideal display aperture ratio.

FIG. 8 and FIG. 9 illustrate pixel structures of two further embodiments of the present invention. Please refer to FIG. 8, the pixel structure 400 is substantially similar to the pixel structure 200 shown in FIG. 4, the same components will be marked with the same component symbols. Specifically, in this embodiment, the first contact opening W1 and the second contact opening W2 are located between the first pixel electrode 104 of the pixel structure 400 and the second scan line 214 corresponding to the scan line group 210 .

In addition, please refer to FIG. 9, the pixel structure 500 is substantially similar to the pixel structure 300 shown in FIG. As in Fig. 6, the same elements will be marked with the same reference numerals. Specifically, in this embodiment, the first contact opening W1 and the second contact opening W2 are located between the first pixel electrode 104 of the pixel structure 500 and the second scan line 214 corresponding to the scan line group 210 .

To sum up, in the present invention, the light-shielding element is arranged on the edge of the pixel structure, and the connection electrode is formed by the same film layer as the pixel electrode. Therefore, the pixel array substrate can have an ideal display aperture ratio. In particular, when the pixel array substrate is applied to a display panel for stereoscopic display, the edge of the pixel structure is already provided with an opaque member. Even if a black matrix is arranged at the edge of the pixel, the display panel can still have a good display aperture ratio. Furthermore, when the color filter layer is disposed on the pixel array substrate, the coupling effect of the data lines can be reduced. Therefore, the pixel electrodes in the pixel array substrate can further partially overlap the data lines to further enlarge the display area to have a high display aperture ratio.

Although the present invention has been disclosed in conjunction with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (14)

1. A pixel array substrate, comprising: Substrate; Multiple scanning line groups are arranged on the substrate; a plurality of data lines intersecting the scan line groups; and A plurality of pixel structures connected to the scan line groups and the data lines, wherein each pixel structure includes: The active element group is connected to the nth scan line group and the mth data line, where n and m are both positive integers; a first pixel electrode electrically connected to the active element group; a second pixel electrode electrically connected to the active element group, and the first pixel electrode is located between the second pixel electrode and the nth scan line group; and A connection electrode, located on the side of the first pixel electrode adjacent to one of the data lines, and the second pixel electrode is electrically connected to the active element group through the connection electrode, wherein the connection electrode, the first pixel electrode and The second pixel electrode is the same film layer, Wherein each of the scan line groups includes adjacent first scan lines and second scan lines and each active element group of the pixel structure includes a first active element and a second active element, Wherein the pixel array substrate further includes an insulating layer, disposed on the substrate, covering the scanning line groups, the data lines and the active element groups of each pixel structure, and Wherein the insulating layer has a first contact opening and a second contact opening, the first pixel electrode is electrically connected to the first active element through the first contact opening, and the connection electrode is electrically connected to the first active element through the second contact opening. The first active element and the second active element, and the first contact opening and the second contact opening are located between the first scan line and the second scan line of the nth scan line group. 2. The pixel array substrate as claimed in claim 1, wherein the second scan line of the nth scan line group is electrically connected to the first scan line of the n+i scan line group, and i is a positive integer. 3. The pixel array substrate according to claim 2, wherein the first active element is connected to the first scanning line of the nth scanning line group, the mth data line, the first pixel electrode and the second The pixel electrode, and the second active element is connected to the second scan line of the nth scan line group and the second pixel electrode. 4. The pixel array substrate as claimed in claim 3, wherein the first active element is a double-drain thin film transistor having two drains and the first pixel electrode is electrically connected to one of the drains, and the The second pixel electrode is electrically connected to the other drain through the connecting electrode. 5. The pixel array substrate as claimed in claim 4, wherein the second active element is connected to the second pixel electrode through the other drain of the first active element. 6. The pixel array substrate as claimed in claim 1, wherein each of the pixel structures further comprises a coupling electrode located on the other side of the first pixel electrode adjacent to the other data line, and the coupling electrode is connected to the first pixel electrode. Two pixel electrodes. 7. The pixel array substrate as claimed in claim 6, wherein the coupling electrode and the second pixel electrode are of the same film layer. 8. The pixel array substrate as claimed in claim 1, further comprising a color filter layer disposed on the substrate. 9. The pixel array substrate as claimed in claim 1, further comprising a black matrix layer disposed on the substrate and at least partially overlapped with the scan line groups and the data lines. 10. The pixel array substrate as claimed in claim 1, wherein the second pixel electrode of each pixel structure partially overlaps at least one of the adjacent data lines. 11. The pixel array substrate as claimed in claim 10, wherein each of the connecting electrodes partially overlaps at least one of the adjacent data lines. 12. The pixel array substrate as claimed in claim 1, wherein the first pixel electrode and the second pixel electrode of each pixel structure respectively have a plurality of slits to define at least four alignment directions. 13. A display panel comprising: The pixel array substrate according to any one of claims 1 to 12; an opposite substrate, opposite to the pixel array substrate; and The polymer stabilized alignment liquid crystal layer is arranged between the pixel array substrate and the opposite substrate. 14. The display panel as claimed in claim 13, further comprising a patterned phase retarder disposed on the opposite substrate, wherein the patterned phase retarder has a plurality of phase retardation regions, and each of the phase retardation regions corresponds to One of the pixel structures.