CN102540047B - Assessment method for test coverage - Google Patents
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- 238000012360 testing method Methods 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000013100 final test Methods 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000011156 evaluation Methods 0.000 claims description 13
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- 238000001514 detection method Methods 0.000 claims description 3
- 238000004364 calculation method Methods 0.000 claims description 2
- 230000006872 improvement Effects 0.000 description 7
- 238000010998 test method Methods 0.000 description 3
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Abstract
The invention discloses an assessment method for test coverage. The assessment method comprises following steps: S1, assessing the coverage of a tested object in a testable stage; S2, assessing the coverage of the tested object in a fixture manufacturing stage; and S3, assessing the coverage of the tested object in a final testing stage. The assessment method has the advantages that the test coverage of the testable stage, the test coverage of the fixture manufacturing stage and the test coverage of the final testing stage are respectively obtained via the S1, the S2 and the S3, testing programs applied onto an online testing machine are simplified, and a fixture manufacturing period is shortened.
Description
Technical Field
The invention relates to an evaluation method for testing coverage rate, belonging to the field of integrated circuit board-level production test.
Background
With the increasing reduction of the process size and the increasing complexity of integrated circuits, especially the emergence and wide application of System-on-Chip (SoC), the integration level of very large scale integrated circuits has been developed to the extent that more than several tens of millions of transistors can be integrated on one Chip. Therefore, the exploration and application of low-cost and high-efficiency test technology and test system has become an important issue in chip testing.
In-circuit tester testing (ICT Test) is widely used in electronics manufacturing enterprises and is mainly used for testing electrical devices of electronic components mounted on a circuit board (PCB) by using a fixture and a Test point on the circuit board as an interface. The online testing machine has the advantages of high speed and comprehensive coverage. A disadvantage of in-line tester testing is that the tester, fixture, and test costs are prohibitively expensive. Because the tester takes the physical test points on the circuit board as interfaces, test excitation is generated through a specially manufactured test program and a corresponding clamp. However, as the circuit board is designed to be more and more complex, the number of components is more and more, and the pins are more and more dense, so that the test procedure and the fixture manufacturing cycle applied to the online tester are longer and more complicated.
Therefore, there is a need for an improvement in the existing evaluation methods for test coverage.
Disclosure of Invention
The invention aims to provide a simplified and staged test coverage rate evaluation method.
In order to solve the technical problems, the invention adopts the following technical scheme: an evaluation method for testing coverage rate is used for testing the coverage rate of a tested object, the tested object comprises a component and a pin corresponding to the component, the component comprises a digital component and an analog component, and the evaluation method comprises the following steps:
step S1, in the testability stage, evaluating the coverage rate of the tested object, wherein the step S1 includes step S11, that is, analyzing the component library of the components, if the pin of the corresponding component is assigned, the pin is considered to be covered by the test;
step S2, evaluating the coverage of the tested object in the manufacturing stage of the fixture, wherein step S2 includes step S21 and step S22, and the pin is considered to be covered by the test only if the pin is covered in step S21 and step S22;
step S21, analyzing the component library of the components, if the pin of the corresponding component is assigned, the pin is preliminarily considered to be covered by the test;
step S22, analyzing the layout detection report of the tested object, if the pin has a test point, the pin is preliminarily considered to be covered by the test, if the pin has no test point, but the pin is on the connection network lines of a plurality of boundary scanning devices, the pin is preliminarily considered to be covered by the test; and
step S3, in the final testing stage, evaluating the coverage of the tested object, wherein the step S3 includes: step S31, evaluating the test coverage rate of the pins of the corresponding digital device; wherein if the digital device is a boundary scan device and is covered by a boundary scan test, the pin of the corresponding digital device is considered to have been covered by the test; if the digital device is a non-boundary scan device, the pin corresponding to the non-boundary scan device is considered to be covered by the test only if the pin meets the fixed 0 fault and the fixed 1 fault; step S32, evaluating the stability of the analog device, that is, calculating the results of multiple tests to obtain the standard deviation and the value of the process capability, if the value of the process capability is greater than 20, the analog device is considered to be unstable; and step S33, evaluating the existence of the component.
As a further improvement of the invention, the pin for connecting the power supply or the ground is not measurable, and the pin for connecting more than 5 parallel capacitors is also not measurable.
As a further improvement of the present invention, the object under test includes a plurality of wires, and in step S2, the wires may be connected by clamps.
As a further improvement of the present invention, the calculation formula of the standard deviation is:
wherein,Xis a test value;nis the number of tests.
As a further improvement of the present invention, the formula for calculating the process capability is:
wherein μ is a test average;USLis the upper tolerance limit of the device;LSLis the lower tolerance limit of the device.
As a further improvement of the present invention, in step S33, the existence coverage of the component adopts the following rule:
if the component is a capacitor, at least one capacitor test or serial capacitor test covers all pins;
if the component is a connector, at least one pin is tested;
if the component is a diode, both pins need to be covered by the diode test;
if the component is an inductor, at least one jumper test or inductor test covers the two pins;
if the component is a jumper, at least one jumper test covers two pins;
if the component is a resistor, at least one of the resistance tests or the series resistance test covers all pins.
As a further improvement of the present invention, in step S33, the existence coverage of the component adopts the following rule:
if the component is a triode, at least one triode is tested to cover all pins;
if the component is a light emitting diode, at least one diode test or light emitting diode color test covers all pins;
if the component is an oscillator, at least one of the simulated power tests covers and detects the correct frequency;
if the component is a digital component, at least one pin is tested by a fixed 0 fault and a fixed 1 fault;
if the component is an analog power supply, at least one pin is tested.
Compared with the prior art, the invention can respectively obtain the test coverage of the testability stage, the fixture manufacturing stage and the final test stage through the steps S1, S2 and S3, thereby simplifying the test procedure applied to the online test machine and shortening the fixture manufacturing period.
Drawings
FIG. 1 is a flow chart of the test coverage assessment method of the present invention.
Detailed Description
The invention discloses an evaluation method for testing coverage rate, which is used for testing the coverage rate of a tested object. In this embodiment, the object to be tested is a circuit board, which includes a plurality of components and a plurality of pins corresponding to the components. The components comprise digital devices and analog devices. Referring to fig. 1, the method for evaluating test coverage of the present invention includes the following steps:
step S1, in the testability stage, evaluating the coverage of the tested object, wherein the step S1 includes:
step S11, analyzing the component library of the components, and if the pin of the corresponding component is assigned, the pin is considered to be covered by the test;
step S2, evaluating the coverage of the tested object in the manufacturing stage of the fixture, wherein step S2 includes step S21 and step S22, and the pin is considered to be covered by the test only if the pin is covered in step S21 and step S22;
step S21, analyzing the component library of the components, if the pin of the corresponding component is assigned, the pin is preliminarily considered to be covered by the test;
step S22, analyzing the layout detection report of the tested object, if the pin has a test point, the pin is preliminarily considered to be covered by the test, if the pin has no test point, but the pin is on the connection network lines of a plurality of boundary scanning devices, the pin is preliminarily considered to be covered by the test; and
step S3, in the final testing stage, evaluating the coverage of the tested object, wherein the step S3 includes:
step S31, evaluating the test coverage rate of the pins of the corresponding digital device;
step S32, evaluating the stability of the analog device; and
in step S33, the presence of the component is evaluated.
The method for evaluating test coverage further comprises a step of initializing before step S1, wherein the pin connected to power or ground is not testable, and the pin connected to more than 5 capacitors connected in parallel is also not testable.
The object under test includes a plurality of wires, and in step S2, the wires may be connected by clamps.
In step S21, taking agilent 3070 online testing machine as an example:
capacitor *, 1000p, 10, 10, f
external pins 1
device * pins 1
external pins 2
device * pins 2
then pins 1, 2 of the component are test covered.
In step S31, if the digital device is a boundary scan device and is covered by the boundary scan test, the pin of the corresponding digital device is considered to have been covered by the test. The pins are TAP pins, or direct connection, or BusWire, or SiliconNai. The description is as follows: if the pins corresponding to the boundary scanning device are connected to the serial resistor, the condition that the pins are tested by one interconnection is satisfied, and the connected pins are on the same network cable; if the pins corresponding to the boundary scan device are tested by one interconnect, but on two silicon nodes, then only these pins are covered, and the resistors are not covered.
In step S31, if the digital device is a non-boundary scan device, the pin corresponding to the non-boundary scan device is considered to be covered by the test only when the pin satisfies the fixed 0 fault (Stuck-At-0) and the fixed 1 fault (Stuck-At-1).
In step S32, the results of the multiple tests are calculated to obtain the Standard Deviation (Standard development) and the process capability (Cpk) values. In this embodiment, if the process capability value is greater than 20, the analog device is considered unstable and needs to be retested or replaced.
The standard deviation is calculated as:
wherein,Xis a test value;nis the number of tests.
The formula for calculating the process capability is as follows:
wherein μ is a test average;USLis the upper tolerance limit of the device;LSLis the lower tolerance limit of the device.
In step S33, the existence coverage of the component adopts the following rule:
if the component is a capacitor, at least one capacitor test or serial capacitor test covers all pins, and a bypass capacitor is not included;
if the component is a connector, at least one pin is tested;
if the component is a diode, both pins need to be covered by the diode test;
if the component is an inductor, at least one jumper test or inductor test covers the two pins;
if the component is a jumper, at least one jumper test covers two pins;
if the component is a resistor, at least one resistor test or serial resistor test covers all pins;
if the component is a triode, at least one triode is tested to cover all pins;
if the component is a light emitting diode, at least one diode test or light emitting diode color test covers all pins;
if the component is an oscillator, at least one of the simulated power tests covers and detects the correct frequency;
if the component is a digital component, at least one pin is tested by a fixed 0 fault and a fixed 1 fault;
if the component is an analog power supply, at least one pin is tested.
Compared with the prior art, the method for evaluating the test coverage rate can obtain the test coverage rates of the testability stage, the clamp manufacturing stage and the final test stage through the steps S1, S2 and S3 respectively, so that the test procedure applied to the online test machine is simplified, and the clamp manufacturing period is shortened. In addition, because the test coverage rate can reflect the defects of the tested object, the tester can make corresponding adjustment according to the test coverage rate so as to achieve the purposes of obtaining the maximum coverage rate and reducing the risk when finally performing board-level online test.
In summary, the above is only a preferred embodiment of the present invention, and should not be limited to the scope of the present invention, and all the simple equivalent changes and modifications made according to the claims and the content of the specification of the present invention should be covered by the scope of the present invention.
Claims (7)
1. The method for evaluating the test coverage rate is characterized by being used for testing the coverage rate of a tested object, wherein the tested object comprises a component and a pin corresponding to the component, the component comprises a digital device and an analog device, and the method for evaluating the test coverage rate comprises the following steps:
step S1, in the testability stage, evaluating the coverage of the tested object, wherein the step S1 includes:
step S11, analyzing the component library of the components, and if the pin of the corresponding component is assigned, the pin is considered to be covered by the test;
step S2, evaluating the coverage of the tested object in the manufacturing stage of the fixture, wherein step S2 includes step S21 and step S22, and the pin is considered to be covered by the test only if the pin is covered in step S21 and step S22;
step S21, analyzing the component library of the components, if the pin of the corresponding component is assigned, the pin is preliminarily considered to be covered by the test;
step S22, analyzing the layout detection report of the tested object, if the pin has a test point, the pin is preliminarily considered to be covered by the test, if the pin has no test point, but the pin is on the connection network lines of a plurality of boundary scanning devices, the pin is preliminarily considered to be covered by the test; and
step S3, in the final testing stage, evaluating the coverage of the tested object, wherein the step S3 includes:
step S31, evaluating the test coverage rate of the pins of the corresponding digital device; wherein if the digital device is a boundary scan device and is covered by a boundary scan test, the pin of the corresponding digital device is considered to have been covered by the test; if the digital device is a non-boundary scan device, the pin corresponding to the non-boundary scan device is considered to be covered by the test only if the pin meets the fixed 0 fault and the fixed 1 fault;
step S32, evaluating the stability of the analog device, that is, calculating the results of multiple tests to obtain the standard deviation and the value of the process capability, if the value of the process capability is greater than 20, the analog device is considered to be unstable; and
in step S33, the presence of the component is evaluated.
2. The evaluation method of claim 1, wherein: the pin connecting the power supply or the ground is not measurable, and the pin connecting more than 5 parallel capacitors is also not measurable.
3. The evaluation method of claim 1, wherein: the object under test includes a plurality of wires, and in step S2, the wires may be connected by clamps.
4. The evaluation method of claim 1, wherein: the calculation formula of the standard deviation is as follows:
whereinXis a test value;nis the number of tests.
5. The evaluation method of claim 1, wherein: the formula for calculating the process capability is as follows:
wherein μ is a test average;USLthe upper limit of the tolerance value of the analog device;LSLis the lower limit of the tolerance value of the analog device.
6. The evaluation method of claim 1, wherein: in step S33, the existence coverage of the component adopts the following rule:
if the component is a capacitor, at least one capacitor test or serial capacitor test covers all pins;
if the component is a connector, at least one pin is tested;
if the component is a diode, both pins need to be covered by the diode test;
if the component is an inductor, at least one jumper test or inductor test covers the two pins;
if the component is a jumper, at least one jumper test covers two pins;
if the component is a resistor, at least one of the resistance tests or the series resistance test covers all pins.
7. The evaluation method of claim 1, wherein: in step S33, the existence coverage of the component adopts the following rule:
if the component is a triode, at least one triode is tested to cover all pins;
if the component is a light emitting diode, at least one diode test or light emitting diode color test covers all pins;
if the component is an oscillator, at least one of the simulated power tests covers and detects the correct frequency;
if the component is a digital component, at least one pin is tested by a fixed 0 fault and a fixed 1 fault;
if the component is an analog power supply, at least one pin is tested.
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| CN108627716B (en) * | 2017-03-22 | 2021-08-31 | 株洲中车时代电气股份有限公司 | Method for analyzing detection coverage rate of whole process of converter |
| CN108627755A (en) * | 2017-03-22 | 2018-10-09 | 株洲中车时代电气股份有限公司 | A kind of circuit board overall process test coverage analysis method |
| CN112131826B (en) * | 2020-08-28 | 2023-08-15 | 上海望友信息科技有限公司 | PCB detection evaluation method, evaluation device, electronic equipment and storage medium |
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| EP0129935A1 (en) * | 1983-06-22 | 1985-01-02 | S.A. Philips Industrielle Et Commerciale | Automatic method and machine for the simultaneous testing of data processing systems |
| CN1885273A (en) * | 2005-06-21 | 2006-12-27 | 华为技术有限公司 | Function coverage ratio analysis method for logic test |
| CN1916920A (en) * | 2006-09-14 | 2007-02-21 | 华为技术有限公司 | System and method for testing and measuring percentage of coverage of function |
| CN100370465C (en) * | 2004-09-04 | 2008-02-20 | 华为技术有限公司 | Method and system for automatic schedule logic simulation and code coverage rate analysis |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6816990B2 (en) * | 2002-01-28 | 2004-11-09 | International Business Machines Corporation | VLSI chip test power reduction |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0129935A1 (en) * | 1983-06-22 | 1985-01-02 | S.A. Philips Industrielle Et Commerciale | Automatic method and machine for the simultaneous testing of data processing systems |
| CN100370465C (en) * | 2004-09-04 | 2008-02-20 | 华为技术有限公司 | Method and system for automatic schedule logic simulation and code coverage rate analysis |
| CN1885273A (en) * | 2005-06-21 | 2006-12-27 | 华为技术有限公司 | Function coverage ratio analysis method for logic test |
| CN1916920A (en) * | 2006-09-14 | 2007-02-21 | 华为技术有限公司 | System and method for testing and measuring percentage of coverage of function |
Non-Patent Citations (1)
| Title |
|---|
| 廖为民.电路板在线测试中应用边界扫描技术的探讨.《中国优秀博硕士学位论文全文数据库 (硕士)信息科技辑》.2004,(第1期), * |
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Effective date of registration: 20160201 Address after: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215021 B No. 5 Building 4 floor 13/16 unit Patentee after: Centec Networks (Suzhou) Inc. Address before: Xinghan street Suzhou Industrial Park in Suzhou city in Jiangsu province 215000 B No. 5 Building 4 Building 16 unit Patentee before: Suzhou Industrial Park ICP Technologies Co., Ltd. |
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Address after: 215000 unit 13 / 16, 4th floor, building B, No.5 Xinghan street, Suzhou Industrial Park, Jiangsu Province Patentee after: Suzhou Shengke Communication Co.,Ltd. Address before: 215021 unit 13 / 16, floor 4, building B, No. 5, Xinghan street, Suzhou Industrial Park, Suzhou, Jiangsu Patentee before: CENTEC NETWORKS (SU ZHOU) Co.,Ltd. |
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