CN102522996B - Decoding method and decoding device of FM0 coded data - Google Patents
Decoding method and decoding device of FM0 coded data Download PDFInfo
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Abstract
The invention discloses a decoding method and a decoding device of FM0 coded data, aiming to reduce demand on performances of hardware chips. The method comprises the steps of obtaining to-be-decoded data in a buffer memory area, wherein the to-be-decoded data are obtained by inputting waveforms for capturing and collecting the FM0 coded data by a timer; comparing the to-be-decoded data with threshold values; and determining decoded data according to comparison results.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for decoding FM0 encoded data.
Background
Electronic Toll Collection system (ETC system) adopts special short range Communication (DSRC) technique, accomplishes the two-way Communication between Roadside Unit (RSU) and On-Board Unit (OBU), carries out security authentication and consumption deduction through wireless mode, realizes the Toll Collection, has accelerated vehicle traffic speed greatly, has reduced the jam situation of Toll turn road junction, has improved the capacity On highway.
At present, ETC system construction is carried out all over the country, and in order to realize interconnection and intercommunication of ETC equipment, RSU and OBU equipment in the ETC system must meet the technical requirements of national standard GB/T20851-2007. GB/T20851.1-2007 makes clear regulation on the physical layer of the professional short-range communication, and in terms of the encoding mode of the communication, most of domestic equipment manufacturers adopt A-type FM0 encoding, the bit rate transmitted to an OBU by an RSU is 256kbit/s, and the bit clock precision is +/-100 multiplied by 10-5(ii) a The bit rate sent by the OBU to the RSU is 512kbit/s, and the precision of the bit clock is +/-100 multiplied by 10-6。
In order to ensure that the vehicle completes the whole transaction process in motion, the transaction needs to be completed in the shortest time. Therefore, how fast the data decoding speed affects the overall transaction time.
The FM0 code is known as a bi-phase code and is characterized by a change in level within a window of bits to represent logic. If the level is flipped from the beginning of the bit window, a logic "1" is indicated. A logic "0" is indicated if the level, in addition to flipping at the beginning of the bit window, also flips in the middle of the bit window. FIG. 1 is a level waveform of data stream "01100101" after FM0 encoding.
According to the FM0 encoding rule, the duration of the period of the pulse corresponding to "1" is greater than the duration of the period of the pulse corresponding to "0". Therefore, in the decoding process of FM0 encoded data, the duration of each pulse period is measured, the duration is defined as "1" when the duration is large, the duration is defined as half "0" when the duration is small, and two consecutive half "0" are combined into one data "0". For example: for 256kbps rate data, a pulse period having a duration of 3.9us is defined as 1, and a pulse period having a duration of 1.95us is defined as half 0; for 512kbps rate data, a pulse period having a duration of 1.95us is defined as 1, and a pulse period having a duration of 0.977us is defined as half 0.
At present, the time length of each pulse period in FM0 encoded data is collected by counting with a timer, which specifically includes: collecting the count value of the timer once per jumping edge, and storing the count value in a corresponding register; and then subtracting the last count value from the current count value to obtain the duration of the current period.
As data needs to be collected at each transition edge, for FM0 encoded data with a rate of 256kbps, the timer will collect data every 1.95us or 3.9us and store the data in the corresponding register; for 512Kbps rate FM0 encoded data, the timer will collect a data every 0.977us or 1.95us, and store the data in the corresponding register. Therefore, the data in the register corresponding to the timer is updated once at the fastest speed of 1.95us when decoding 256kbps data, and is updated once at the fastest speed of 0.977us when decoding 512kbps data, which requires a Microprocessor (MCU) to have a fast enough speed to complete decoding before updating.
Assuming that 30 clock cycles are needed for the MCU to finish decoding 1-bit FM0 coded data, and 25 clock cycles are needed for data acquisition after acquisition interruption and reading, the real-time decoding of the MCU above the 256kbps waveform theory needs the master frequency 28M IPs (instruction number executed per second); the real-time decoding of the 512kbps waveform can be realized by a MCU with the minimum main frequency of 56M IPs theoretically. In practical engineering applications, RF transceivers are not ideal transceivers, and a large number of clutter will appear after the front packet of a data packet, and need an MCU to process the clutter, and in order to reliably decode in a real use environment, an MCU with a higher dominant frequency is needed to process the interference.
Particularly for data with the rate of 512kbps, the data updating interval is 0.977us, so that the fast data rate exceeds the processing capacity of a single chip microcomputer, and therefore, an FPGA or a high-rate chip is required to collect and decode FM0 encoded data.
When FM0 coded data is decoded, most resources of the chip are used for collecting data, and only a few resources are used for decoding, so that the single chip microcomputer is required to provide a large cache area for storing the collected data, and meanwhile, the data cannot be decoded in real time; also, for 512kbps rate FM0 encoded data, a more expensive chip is required to implement the acquisition and decoding.
Therefore, the frequency of data collected in the existing FM0 encoded data decoding process is relatively fast, that is, the data is relatively fast to update, and the performance requirement on a hardware chip is relatively high. Moreover, only one "1" or half "0" can be determined in one decoding, so that the whole decoding process is slow, and the decoding rate of a high-performance hardware chip is not high.
Disclosure of Invention
The embodiment of the invention provides a method and a device for decoding FM0 coded data, which are used for reducing the requirement on the performance of a hardware chip.
The embodiment of the invention provides a method for decoding FM0 coded data, which comprises the following steps:
acquiring data to be decoded in a buffer area, wherein the data to be decoded is obtained by inputting a waveform for capturing and collecting the FM0 encoded data through a timer;
and comparing the data to be decoded with a threshold value, and determining the decoded data according to the comparison result.
The embodiment of the invention provides a decoding device of FM0 coded data, which comprises:
the acquisition unit is used for acquiring data to be decoded in a buffer area, wherein the data to be decoded is obtained by inputting a waveform for capturing and collecting the FM0 encoded data through a timer;
and the decoding unit is used for comparing the data to be decoded with a threshold value and determining the decoded data according to the comparison result.
In the embodiment of the invention, data to be decoded in a buffer area is obtained, the data to be decoded is compared with a threshold value, and the decoded data is determined according to the comparison result, wherein the data to be decoded is obtained by inputting a timer to capture and collect the waveform of the FM0 encoded data. The data to be decoded is obtained by adopting a timer input capturing mode, so that the data to be decoded is obtained only when a specific jumping edge of the waveform of the FM0 coded data is acquired, but the data to be decoded is not obtained at each jumping edge of the waveform of the FM0 coded data, thereby reducing the frequency of the acquired data, lowering the performance requirement on a hardware chip and further reducing the resource cost in the decoding process.
Drawings
FIG. 1 is a diagram illustrating a level waveform after FM0 encoding in the prior art;
FIG. 2 is a block diagram of a PWM input capture hardware according to a first embodiment of the present invention;
FIG. 3 is a timing diagram illustrating actual operation of PWM according to a first embodiment of the present invention;
FIG. 4 is a flowchart illustrating decoding of FM0 encoded data according to one embodiment of the present invention;
FIG. 5 is a flowchart illustrating a decoding process of first data to be decoded according to an embodiment of the present invention;
FIG. 6 is a timing diagram illustrating PWM input capture in accordance with one embodiment of the present invention;
FIG. 7 is a block diagram of PWM input capture hardware according to a second embodiment of the present invention;
FIG. 8 is a timing diagram illustrating actual PWM operation according to a second embodiment of the present invention;
FIG. 9 is a flowchart illustrating the decoding of FM0 encoded data according to a second embodiment of the present invention;
FIG. 10 is a flowchart illustrating a decoding process of first data to be decoded according to a second embodiment of the present invention;
FIG. 11 is a timing diagram of PWM input capture in a second embodiment of the present invention;
fig. 12 is a block diagram of an apparatus for decoding FM0 encoded data according to an embodiment of the present invention.
Detailed Description
In the embodiment of the invention, in the process of decoding the FM0 coded data, the waveform of the acquired FM0 coded data is captured by the timer to obtain the data to be decoded, then the data to be decoded is compared with the threshold value, and the decoded data is determined according to the comparison result. Therefore, the data to be decoded is obtained only when the specific jump edge of the waveform of the FM0 encoded data is acquired, so that the period for acquiring the data to be decoded is increased, the frequency for acquiring the data is reduced, and the performance requirement on a hardware chip is lowered.
In the embodiment of the invention, the timer has a plurality of input capture modes, such as: single register input capture mode, PWM input capture mode. In this way, after the timer is configured in advance to a certain input capture mode, the waveform of the FM0 encoded data can be collected by the configured input capture mode, and the data to be decoded can be obtained.
In a first embodiment, the timer is in a single-register input capture mode, which is an extension of the timer function, and only one register is corresponding to the timer, and one input terminal is set as a rising edge or falling edge detection port. As with the input capture hardware shown in fig. 2, the timer corresponds to a capture register. Thus, the external waveform enters the MCU through CH2, internally linked to the edge detector. When CH2 detects the corresponding edge, the value of the timer is automatically saved to the capture register, the interrupt flag is concatenated, and the timer is cleared on the subsequent timer edge. If the timer interrupt is started, the interrupt function is immediately entered for processing.
The rising edge valid or falling edge valid in the single register input capture mode is obtained by configuring the MCU, and therefore, prior to decoding FM0 encoded data, configuration is required, including: the timer is configured in a single register input capture mode and the count frequency of the timer is determined based on the rate at which FM0 encodes data, and the set frequency division. Wherein the capture register corresponding to the timer may be configured such that either the first transition edge or the second transition edge is active, and the interrupt is enabled. Here, the first transition edge is a rising edge or a falling edge. And the second transition edge is a falling or rising edge. I.e. the first transition edge is opposite to the second transition edge.
Generally, in the process of configuring the timer into the single-register input capture mode, the clock source of the timer may be configured with the system clock, and the timer may be configured to count up, and the timer input channel 2 is configured in the single-register input capture mode. And configuring the interrupt enable includes configuring an interrupt vector.
After the configuration of the input capture is completed through the above process, the actual operation timing of the input capture can be seen in fig. 3, where the timer is in the single register input capture mode, the channel 2(CH2) is configured to be active on the rising edge, and the interrupt is enabled.
At the point of capture of waveform a (rising edge), the CH2 channel triggers, the value 0004 of the timer is saved into the capture register, the interrupt flag triggers the interrupt, and at the point of time D when the timer count changes, the timer is cleared, i.e., still starting at 0000.
At point C (rising edge), the CH2 channel triggers, the timer value 0004 is stored in the capture register, the interrupt flag triggers an interrupt, and the timer is cleared at point F where the timer count changes.
Single register input capture, generating an interrupt only on the rising edge of the waveform, determining the value of the register as the data to be decoded in the interrupt, and reading into a buffer for decoding. For example: at point C, an interrupt is generated, and the value 0004 of the register is determined as the data to be decoded and read into the buffer.
After the data to be decoded obtained by the single register input capture mode is stored in the buffer by the interrupt mode, the process of decoding the FM0 encoded data is shown in fig. 4, and includes:
step 401: and acquiring data to be decoded in the buffer area, wherein the data to be decoded is obtained by inputting a waveform for capturing and collecting FM0 encoded data through a timer.
Since the data to be decoded is stored in the buffer by the interrupt method, the data to be decoded obtained by acquiring the waveform of the FM0 encoded data by the single register input capture mode is stored in the buffer here. Thus, when decoding is performed, the buffer stores the data to be decoded.
Here, the data to be decoded may be acquired from the buffer in a first-in first-out manner. Of course, the data to be decoded may be obtained from the buffer in another order, and thus, the decoded data may be output in the set order.
Step 402: and comparing the acquired data to be decoded with a threshold value, and determining the decoded data according to the comparison result.
Since the data to be decoded is obtained by acquiring the waveform of the FM0 encoded data in the single register input capture mode, the data to be decoded is obtained only when the rising edge or the falling edge of the waveform of the FM0 encoded data is acquired, and therefore, of the values of the data to be decoded, the minimum value corresponds to a time period corresponding to two consecutive half "0", the maximum value corresponds to a time period corresponding to two consecutive "1", and the time period corresponding to one "1" and one half "0" between the maximum value and the minimum value. Therefore, in the implementation of the present invention, firstly, according to whether the value of the data to be decoded is within the minimum value range, the decoded data is determined to be two continuous half "0"; then determining that the decoded data are two continuous '1' according to whether the value of the data to be decoded is within the maximum value range; finally, whether the "1" data precedes or half the "0" data precedes is determined according to the number of times the value of the data to be decoded occurs in a threshold space composed of a maximum value and a minimum value. The specific process comprises the following steps:
when the value of the data to be decoded is less than or equal to the first threshold, determining that the decoded data is 0; when the value of the data to be decoded is greater than or equal to a second threshold value, determining that the decoded data are two 1 s; when the value of the data to be decoded is between the first threshold and the second threshold, it is determined whether "1" data or "0" data in the decoded data is preceded according to the number of times the value of the data to be decoded appears in a threshold space composed of the first threshold and the second threshold. Wherein,
in the embodiment of the present invention, the first threshold is set to a duration corresponding to two consecutive half "0", so as to provide an error redundancy and increase a certain error, for example, increase an error by 10% or 5%; the second threshold is set to a duration corresponding to two consecutive "1" s and is reduced by a certain error, for example, by 10% or 5%.
The specific decoding process of each data to be decoded can be seen in fig. 5, which includes:
step 501: judging whether the value of the data to be decoded is smaller than or equal to a first threshold value, if so, determining that the decoded data is 0; otherwise, step 502 is performed.
Step 502: judging whether the value of the data to be decoded is greater than or equal to a second threshold value, if so, determining that the number of the decoded data is two 1; otherwise, step 503 is executed.
Step 503: and adding 1 to the number of times of the value of the data to be decoded appearing in a threshold space consisting of the first threshold and the second threshold to obtain the updated number of times.
In the decoding process, a variable may be set to record the number of times the value of the data to be decoded appears in a threshold space composed of a first threshold and a second threshold. Before decoding, the value of the variable is zero, and then the value of the data to be decoded is incremented by 1 each time the value of the variable appears in a threshold space composed of a first threshold and a second threshold.
Thus, when decoding is performed for the first time, the number of times that the value of the data to be decoded appears in the threshold space composed of the first threshold and the second threshold is zero. As decoding is performed one by one, the number of times the value of data to be decoded appears in a threshold space composed of the first threshold and the second threshold increases. After all decoding is finished, the variable may be cleared, that is, the number of times that the value of the data to be decoded appears in a threshold space composed of the first threshold and the second threshold may be reset to zero.
Step 504: judging whether the updated times are odd numbers, if so, determining that the decoded data is 1 plus half 0; otherwise, the decoded data is determined to be half 0 plus 1.
Of course, the sequence of steps 501 and 502 may be reversed, that is, it may be determined whether the value of the data to be decoded is greater than or equal to the second threshold first, and then it may be determined whether the value of the data to be decoded is less than or equal to the first threshold, and the specific process is not described repeatedly.
In one specific application of this embodiment, when the rate of FM0 encoded data is configured to be 256kbps, the timer clock source is the system clock, and the frequency division of the clock is 32, so that the configuration is such that the input capture falling edge mode, and the counting frequency of the timer is 256 × 32 × 2 — 16384 khz.
Input capture falling edge timing diagram as shown in fig. 6, the waveform of input capture FM0 encoded data has 4 cases in total, A, B, D and F, respectively, where C, E is the same as a.
Since the captured data is of three lengths, and assuming the timer count frequency is 8192KHz, decoding a 256kbps rate FM0 encoding, then:
the counting value of the A section is 64;
the count value of the section B is 128;
the count value of the C section is 64;
the D section count value is 96;
the count value of the section E is 64;
the segment F count is 96.
Therefore, in this embodiment, the decoding process for each segment, in which the first threshold is determined to be 64 × (1+ 10%) -70 and the second threshold is determined to be 128 × (1-10%) -115, includes:
the count value C2 is 64 < 70, i.e., the corresponding decoded data is two consecutive halves of 0.
The count value C2 is 128 > 115, that is, the corresponding decoded data are two consecutive 1 s.
The count value C2 is 64 < 70, i.e., the corresponding decoded data is two consecutive halves of 0.
The count value C2 is 96, and since 70 < C2 is 96 < 115, the number of occurrences is 1 and is an odd number, i.e., the corresponding decoded data is 1 plus one-half 0.
The count value C2 is 64 < 70, i.e., the corresponding decoded data is two consecutive halves of 0.
The count value C2C2 is 96, and since 70 < C2 is 96 < 115, the number of occurrences is 2 and is even, i.e., the corresponding decoded data is half 0 plus 1.
Two consecutive half 0's, i.e., one 0's, are obtained, and thus, the decoded data is "01101001".
In the above embodiment, the falling edge is enabled and the interrupt is enabled, but the embodiment of the present invention is not limited thereto, and the rising edge may also be configured to be enabled and the interrupt is enabled, and the specific application is not described again.
In the second embodiment, the timer is in a PWM (Pulse Width Modulation) input capture mode.
The PWM input capture mode of the MCU is an extension of different input capture of the timer, and the same input end is mapped to two transition edge detection ports of the timer, namely the timer corresponds to two registers. The PWM input capture hardware shown in fig. 7, the external waveform enters the MCU through CH2, internally linked to the transition edge detectors of CH1 and CH 2. The CH1 and CH2 transition edge detectors have opposite polarities, and when the CH1 transition edge detector detects a corresponding transition edge, the value of the timer is automatically saved in the CC1 register; when CH2 detects a corresponding transition edge, the value of the timer is automatically saved to the CC2 register, the interrupt flag is set, and the timer is cleared at the subsequent timer transition edge. If the timer interrupt is started, the interrupt function is immediately entered for processing.
The PWM input capture mode is obtained by configuring the MCU timer, and therefore, before decoding the FM0 encoded data, configuration is performed, including: configuring a timer to be in a PWM input capture mode, and determining a counting frequency of the timer according to the rate of the FM0 encoded data and the set frequency division, wherein a second register corresponding to the timer is configured to enable a second jumping edge, and interrupt is enabled; and configuring a first register corresponding to the timer to be valid for the first transition edge.
Generally, in the process of configuring the timer into the PWM input capture mode, the clock source of the timer is configured with the system clock, and the timer is configured to count up, and the timer input channels 1 and 2 are configured into the PWM input capture mode.
And configuring the terminal enable includes configuring an interrupt vector.
After the configuration of the PWM input capture is completed through the above process, the actual PWM operating timing can be seen in fig. 8, where the timer is in the PWM input capture mode, channel 2(CH2) is configured to be active on the rising edge, and the interrupt is enabled.
When the waveform A point (rising edge) is captured, the CH2 channel triggers, the value 0004 of the timer is stored in the CC2 register, the interrupt flag bit triggers the interrupt, and at the D time point when the timer count changes, the timer is cleared, namely, the timer is still started from 0000.
At point B (falling edge), CH1 lane toggles, timer value 0002 is saved into CC1 register;
at point C (rising edge), the CH2 channel is triggered, the timer value 0004 is stored in the CC2 register, the interrupt flag bit triggers an interrupt, and the timer is cleared at point F where the timer count changes.
During PWM input capture, an interrupt is generated only at the rising edge of the waveform, and the values of CC1 and CC2 are simultaneously determined as data to be decoded in the interrupt and read into a buffer area for decoding. For example: at point C, an interrupt is generated, and the value 0002 of CC1 and the value 0004 of CC2 are determined as data to be decoded and read into the buffer.
Therefore, the process of acquiring the waveform of the FM0 encoded data by the PWM input capturing mode to obtain the data to be decoded comprises the following steps: when a second transition edge in the waveform acquired by the FM0 encoded data is captured through the PWM input, determining a first value of a first register and a second value of a second register as data to be decoded, and reading the data into a buffer, wherein the first value of the first register is a value in a first transition edge time timer in the waveform acquired by capturing the FM0 encoded data through the PWM input, the second value of the second register is a value in a second transition edge time timer in the waveform acquired by capturing the FM0 encoded data through the PWM input, and the second transition edge is opposite to the first transition edge.
After the data to be decoded is stored in the buffer by the interrupt method, the process of decoding the FM0 encoded data is shown in fig. 9, which includes:
step 901: and acquiring data to be decoded in the buffer area, wherein the data to be decoded is obtained by capturing the waveform of the FM0 encoded data through PWM input.
Since the data to be decoded is stored in the buffer area in an interruption mode, the data to be decoded obtained by capturing the waveform of the FM0 encoded data through the PWM input is stored in the buffer area. Thus, when decoding is performed, the buffer stores the data to be decoded.
Here, the data to be decoded may be acquired from the buffer in a first-in first-out manner. Of course, the data to be decoded may be obtained from the buffer in another order, and thus, the decoded data may be output in the set order.
Step 902: and comparing the acquired data to be decoded with a threshold value, and determining the decoded data according to the comparison result.
Since the data to be decoded is obtained by capturing the waveform of the FM0 encoded data through the PWM input, the data to be decoded is obtained only when a specific transition edge of the waveform of the FM0 encoded data is acquired, and therefore, the minimum value of the second values of the second register in the data to be decoded should correspond to a time duration corresponding to two consecutive half "0" s, and the maximum value of the second values should correspond to a time duration corresponding to two consecutive "1" s. And the maximum value of the first values of the first register in the data to be decoded should correspond to half the duration corresponding to "0" and the maximum value of the first values should correspond to a duration corresponding to "1". Therefore, in the implementation of the present invention, the decoded data is determined according to the second value, and if the decoded data cannot be determined according to the second value, the decoded data is determined according to the first value. The specific process comprises the following steps:
when the second value of the second register in the data to be decoded is less than or equal to the third threshold value, determining that the decoded data is 0; when the second value is greater than or equal to the fourth threshold, determining the decoded data to be two 1 s; and when the second value is between a third threshold and a fourth threshold, comparing the first value of the first register in the data to be decoded with a fifth threshold, and determining the decoded data according to the comparison result, wherein the fifth threshold is smaller than the third threshold, and the third threshold is smaller than the fourth threshold.
Comparing the second value with a third threshold, if the decoded data cannot be determined according to the comparison result, comparing the second value with a fourth threshold, if the decoded data cannot be determined according to the comparison result, finally determining the decoded data according to the first value, namely comparing the first value with a fifth threshold, and determining the decoded data according to the comparison result, wherein when the first value is greater than the fifth threshold, the decoded data is determined to be 1 plus half 0; when the first value is less than or equal to the fifth threshold, the decoded data is determined to be half 0 plus 1.
In the embodiment of the present invention, the third threshold is set to a duration corresponding to two consecutive half "0", so as to provide an error redundancy and increase a certain error, for example, increase an error by 10% or 5%; setting the fourth threshold to a duration corresponding to two consecutive "1" s, and reducing the error by, for example, 10% or 5%; the fifth threshold is set between half the duration corresponding to "0" and one duration corresponding to "1" and may give some error redundancy corresponding to the error. As can be seen, in this embodiment, the third threshold may be equal to the first threshold in the first embodiment, and the fourth threshold may be equal to the second threshold in the first embodiment.
The specific decoding process of each data to be decoded can be seen in fig. 10, which includes:
step 1001: judging whether a second value of a second register in the data to be decoded is smaller than or equal to a third threshold value, if so, determining that the decoded data is 0; otherwise, step 1002 is executed.
Step 1002: judging whether a second value of a second register in the data to be decoded is greater than or equal to a fourth threshold value, if so, determining that the number of the decoded data is two 1; otherwise, step 1003 is performed.
Step 1003: judging whether a first value of a first register in the data to be decoded is larger than a fifth threshold value, if so, determining that the decoded data is 1 plus a half 0; otherwise, the decoded data is determined to be half 0 plus 1.
Of course, the sequence of steps 1001 and 1002 may be reversed, that is, it may be determined whether the second value is greater than or equal to the fourth threshold first, and then it may be determined whether the second value is less than or equal to the third threshold, and the specific process is not described repeatedly.
In one specific application of this embodiment, when the rate of FM0 encoded data is configured at 256kbps, the timer clock source is the system clock, and the clock is divided by 32, so that the configuration is the PWM input capture mode, and the counting frequency of the timer is 256 × 32 × 2 — 16384 khz. And the second register corresponding to the timer is configured to be effective for falling edge, and the terminal is enabled, so that the first register corresponding to the timer is effective for rising edge.
PWM input capture timing diagram as shown in fig. 11, the waveform of PWM input capture FM0 encoded data has 4 cases in total, A, B, C and E, respectively, where D, F is the same as a.
The second value of the second register, C2, is three cases, C2 for segment a, C2 for segment B, and C2 for segment C or E. The first value of the first register, C1, has only two values, C1 for segment A or E, and C1 for segment B or C, respectively. The PWM input capture peripheral enters an interrupt at each falling edge, and in an interrupt procedure, the values of two registers of CC1 and CC2 are read into a buffer area as data to be decoded, and then decoding is carried out according to the two values in the data to be decoded.
Since the captured C2 segment data has three lengths, the C1 segment data has two lengths, and assuming that the timer count frequency is 8192KHz, decoding a 256kbps rate FM0 encoding, then:
the count value of the G segment C2 is 64, and the count value of the C1 is 32;
h segment C2 has a count value of 128 and C1 has a count value of 64;
the I section C2 has a count value of 96 and the C1 has a count value of 64;
j segment C2 has a count of 64 and C1 has a count of 32;
the counting value of the K section C2 is 96, and the counting value of the C1 is 32;
the L-segment C2 count value is 64 and the C1 count value is 32.
Therefore, in this embodiment, the third threshold is determined to be 64 × (1+ 10%) -70, the fourth threshold is determined to be 128 × (1-10%) -115, the fifth threshold is determined to be 32 × (1+ 10%) -35, and the fifth threshold is determined to be any number between 64 × (1-10%) -58, where the fifth threshold is determined to be (32+64) ÷ 2 ═ 48, and then the decoding process for each segment includes:
c2 is 64 < 70, i.e. the corresponding decoded data are two consecutive halves 0.
C2 > 128, i.e. the corresponding decoded data are two consecutive 1's.
70 < C2 ═ 96 < 115, C1 ═ 64 > 48, and the corresponding decoded data are 1 plus half 0.
C2 is 64 < 70, i.e. the corresponding decoded data are two consecutive halves 0.
70 < C2 ═ 96 < 115, C1 ═ 32 < 48, i.e., the corresponding decoded data is half 0 plus 1.
C2 is 64 < 70, i.e. the corresponding decoded data are two consecutive halves 0.
Two consecutive half 0's, i.e., one 0's, are obtained, and thus, the decoded data is "01110010".
In the above embodiment, the second transition edge is a falling edge, but the embodiment of the present invention is not limited thereto, and the second transition edge may be set as a rising edge.
According to the above decoding method of FM0 encoded data, a decoding apparatus of FM0 encoded data can be constructed, see fig. 12, an obtaining unit 100 and a decoding unit 200, wherein,
the acquiring unit 100 is configured to acquire data to be decoded in the buffer, where the data to be decoded is obtained by capturing and acquiring a waveform of the FM0 encoded data through a timer input.
And the decoding unit 200 is configured to compare the data to be decoded with a threshold, and determine decoded data according to a comparison result.
The acquiring unit 100 is configured to, when the timer is configured in a single-register input acquisition mode, and a first transition edge or a second transition edge in a waveform of the FM0 encoded data is acquired through the single-register input acquisition mode, determine a value in the timer acquired by the acquisition register as the data to be decoded, and read the data into the buffer;
when the timer is configured to be in a PWM input capture mode, and a second transition edge in the waveform of the FM0 encoded data is captured through PWM input capture, determining a first value of a first register and a second value of a second register as the data to be decoded and reading the data into the buffer, wherein the first value of the first register is a value in a first transition edge time timer in the waveform of the FM0 encoded data captured through PWM input capture, and the second value of the second register is a value in a second transition edge time timer in the waveform of the FM0 encoded data captured through PWM input capture, and the second transition edge is opposite to the first transition edge.
The obtaining unit 100 is further configured to clear the timer.
When the timer is configured in the single-register input capture mode, the decoding unit 200 is specifically configured to:
when the value of the data to be decoded is less than or equal to a first threshold value, determining that the decoded data is 0; when the value of the data to be decoded is greater than or equal to a second threshold value, determining that the decoded data are two 1 s; when the value of the data to be decoded is between a first threshold and a second threshold, determining the decoded data according to the number of times that the value of the data to be decoded appears in a threshold space composed of the first threshold and the second threshold, wherein the first threshold is smaller than the second threshold.
When the value of the data to be decoded is between the first threshold and the second threshold, the decoding unit 200 is specifically configured to add 1 to the number of times that the value of the data to be decoded appears in a threshold space formed by the first threshold and the second threshold, so as to obtain an updated number of times; when the updated times are odd times, determining that the decoded data is 1 plus half 0; and when the updated times are even times, determining that the decoded data is half 0 plus 1.
When the timer is configured in the PWM input capture mode, the decoding unit 200 is specifically configured to:
when the second value is less than or equal to a third threshold, determining the decoded data to be a 0; when the second value is greater than or equal to a fourth threshold, determining that the decoded data are two 1 s; determining decoded data from the first value when the second value is between a third threshold and a fourth threshold, wherein the fifth threshold is less than the third threshold and the third threshold is less than the fourth threshold.
When the second value is between the third threshold and the fourth threshold, the decoding unit 200 is specifically configured to determine that the decoded data is 1 plus half 0 when the first value is greater than the fifth threshold; when the first value is less than or equal to a fifth threshold, the decoded data is determined to be half 0 plus 1.
The device also includes: the configuration unit is used for configuring the timer into a single-register input capture mode or a PWM input capture mode, and determining the counting frequency of the timer according to the rate of the FM0 encoded data and the set frequency division; when the timer is configured in a single-register input capture mode, configuring a capture register corresponding to the timer to enable a first transition edge or a second transition edge, and interrupting enabling; configuring a second register corresponding to the timer to be valid for a second transition edge when the timer is configured in the PWM input capture mode, and interrupting enabling; and configuring a first register corresponding to the timer to be valid for a first transition edge.
The decoding method of FM0 encoded data in the embodiment of the present invention may be used in a system that performs communication using FM0 encoded data, for example: ETC. Of course, in the embodiments of the present invention, the aforementioned "first" and "second" are only used to distinguish the respective names, wherein the first and the second can be exchanged.
Embodiments of the present invention also provide a communication device, such as an OBU, RSU, etc., which includes the above-mentioned decoding device for FM0 encoded data, and the device decodes FM0 encoded data by using the above-mentioned decoding device for FM0 encoded data.
In the embodiment of the invention, data to be decoded in a buffer area is obtained, the data to be decoded is compared with a threshold value, and the decoded data is determined according to the comparison result, wherein the data to be decoded is obtained by inputting a timer to capture and collect the waveform of the FM0 encoded data. The data to be decoded is obtained by adopting the input capture mode of the timer, so that the data to be decoded is obtained only when the specific jumping edge of the waveform of the FM0 coded data is acquired, but the data to be decoded is not obtained at each jumping edge of the waveform of the FM0 coded data, thereby reducing the frequency of the acquired data, lowering the performance requirement on a hardware chip and further reducing the resource cost in the decoding process. Even with PWM input capture decoding, such that the same rate data is decoded, a relatively inexpensive chip can be used, while using the same chip, higher rate data can be decoded or the data can be decoded more quickly.
In addition, in the embodiment of the present invention, two data can be decoded by decoding the data to be decoded once, for example: two consecutive 1 s, two consecutive half 0 s, one 1 and half 0 s, or half 0 s and one 1 s. In this way, the decoding rate is increased, i.e., a high speed waveform of decoded FM0 encoded data can be achieved using existing PWM input capture hardware.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A method of decoding FM0 encoded data, comprising:
acquiring data to be decoded in a buffer, wherein when a second transition edge in the waveform of the FM0 encoded data is acquired through a PWM input acquisition mode, a first value of a first register and a second value of a second register are determined and stored in the buffer in an interruption mode, the interruption is generated at a rising edge or a falling edge of the waveform of the FM0 encoded data, the value of the first register is a value in a first transition edge time timer in the waveform of the FM0 encoded data acquired through the PWM input acquisition mode, the value of the second register is a value in a second transition edge time timer in the waveform of the FM0 encoded data acquired through the PWM input acquisition mode, and the second transition edge is opposite to the first transition edge;
comparing the data to be decoded with a threshold;
when the second value is less than or equal to a third threshold, determining the decoded data to be a 0;
when the second value is greater than or equal to a fourth threshold, determining that the decoded data are two 1 s;
comparing the first value to a fifth threshold when the second value is between a third threshold and a fourth threshold;
when the first value is larger than a fifth threshold value, determining that the decoded data is 1 plus half 0, and when the first value is smaller than or equal to the fifth threshold value, determining that the decoded data is half 0 plus 1;
wherein the fifth threshold is less than the third threshold, which is less than the fourth threshold.
2. The method of claim 1, wherein after storing into the buffer, further comprising: and clearing the timer.
3. The method of claim 1, wherein before obtaining the data to be decoded in the buffer, further comprising:
configuring the timer in a PWM input capture mode and determining a count frequency of the timer based on the rate at which the FM0 encodes data and the set frequency division;
configuring a second register corresponding to the timer to be second transition edge active, interrupt enabled, and configuring a first register corresponding to the timer to be first transition edge active.
4. An apparatus for decoding FM0 encoded data, comprising:
the acquisition unit is used for acquiring data to be decoded in a buffer, wherein when a second transition edge in the waveform of the FM0 encoded data is acquired through a PWM input acquisition mode, a first value of a first register and a second value of a second register are determined and stored in the buffer in an interruption mode, the interruption is generated at a rising edge or a falling edge of the waveform of the FM0 encoded data, the value of the first register is a value in a first transition edge time timer in the waveform of the FM0 encoded data acquired through the PWM input acquisition mode, the value of the second register is a value in a second transition edge time timer in the waveform of the FM0 encoded data acquired through the PWM input acquisition mode, and the second transition edge is opposite to the first transition edge;
the decoding unit is configured to compare the data to be decoded with a threshold, determine that the decoded data is one 0 when the second value is less than or equal to a third threshold, determine that the decoded data is two 1 s when the second value is greater than or equal to a fourth threshold, compare the first value with a fifth threshold when the second value is between the third threshold and the fourth threshold, determine that the decoded data is 1 plus one-half 0 s when the first value is greater than the fifth threshold, and determine that the decoded data is one-half 0 plus 1 s when the first value is less than or equal to the fifth threshold, where the fifth threshold is less than the third threshold and the third threshold is less than the fourth threshold.
5. The apparatus of claim 4,
the obtaining unit is further configured to clear the timer.
6. The apparatus of claim 4, further comprising:
a configuration unit, configured to configure the timer to a PWM input capture mode, and determine a count frequency of the timer according to the rate of the FM0 encoded data and the set frequency division; configuring a second register corresponding to the timer to enable a second transition edge, and interrupt; and configuring a first register corresponding to the timer to be valid for a first transition edge.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102522997B (en) * | 2011-12-08 | 2015-09-02 | 北京握奇数据系统有限公司 | The coding/decoding method of FM0 coded data and device |
| CN102938197A (en) * | 2012-10-26 | 2013-02-20 | 合肥移瑞通信技术有限公司 | Method for decoding infrared remote control by means of input capture interrupt mode |
| CN103731237B (en) * | 2012-12-07 | 2017-03-15 | 深圳市金溢科技股份有限公司 | Coding/decoding method, device, equipment and communication system towards two-phase space code |
| CN104639176B (en) * | 2013-11-08 | 2018-02-13 | 上海华虹集成电路有限责任公司 | The asynchronous decoder and method of BMC signals |
| CN105224481A (en) * | 2015-10-22 | 2016-01-06 | 福州瑞芯微电子股份有限公司 | PWM transmits the implementation of data in input mode |
| CN106921462B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN106921466B (en) * | 2015-12-25 | 2019-11-29 | 航天信息股份有限公司 | The method and apparatus being decoded are encoded to FM0 |
| CN106921463B (en) * | 2015-12-28 | 2020-03-13 | 航天信息股份有限公司 | Anti-interference decoding method and system |
| CN106372553B (en) * | 2016-08-30 | 2019-03-01 | 成都九洲电子信息系统股份有限公司 | Flowing water matrix matching technique based on GJB Radio Frequency Identification Technology |
| CN106789517A (en) * | 2017-01-08 | 2017-05-31 | 易晓云 | CAN data link and its by turn loss arbitration method |
| CN110138501B (en) * | 2018-02-08 | 2021-09-24 | 北京万集科技股份有限公司 | Decoding method and device for FM0 codes |
| CN111327333B (en) * | 2020-03-02 | 2023-07-18 | 华润微集成电路(无锡)有限公司 | Decoding circuit |
| CN112633023B (en) * | 2020-12-18 | 2022-03-01 | 中国电子科技集团公司第五十四研究所 | Decoding method and device for national military standard RFID (radio frequency identification) tag |
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