CN102522113A - SDRAM bridge circuit - Google Patents

Abstract

The invention relates to an SDRAM bridge circuit. The circuit includes a first module, a second module and a PHY module; wherein, the first module parses the SDRAM access command sent by the controller, and the second module converts the SDRAM access command into an acceptable command of the PHY module, and the PHY module uses the The commands accepted by the PHY module access the memory, where the memory and the controller have different SDRAM types. The invention allows the SDRAM controller to realize access to the DDR3 SDRAM and perform data access through the bridging circuit; compared with replacing or redeveloping a chip integrated with the SDRAM controller, the circuit changes are small, the development cycle is short, and the cost is low, and it is compatible with The original system is well compatible.

Description

A SDRAM bridge circuit

technical field

The invention relates to access control of synchronous dynamic random access memory.

Background technique

Synchronous Dynamic Random Access Memory (SDRAM) is widely used in various electronic products, and is constantly being updated. So far, a large number of commercial products of successive generations include SDRAM, DDR SDRAM, DDR2SDRAM and DDR3SDRAM (the full name of DDR is Double Data Rate, which means double data rate). The earlier SDRAM has withdrawn from the mainstream or even ceased production, and more and more products use a new generation of memory such as DDR3SDRAM.

SDRAM accepts access from the SDRAM controller, and DDR/DDR2/DDR3 SDRAM accepts access from the controller and PHY (Physical Interface, physical layer interface) to realize data access. Each generation of memory can only be physically connected to the corresponding controller or PHY, and the generations cannot be used universally. For example, SDRAM can only be connected to the SDRAM controller and cannot be connected to the DDR3PHY.

Chips that require an external memory generally implement access to the memory by integrating a corresponding memory controller or PHY. When the memory is updated, the original memory controller or PHY also faces the problem of replacement, and the replacement of the controller or PHY requires replacement or redevelopment of the chip.

When replacing or modifying an existing chip to integrate a new PHY, it will "touch the whole body", resulting in a large amount of circuit changes, a long development cycle, high costs, and incompatibility with the original system. For example, when the central processing unit CPU with external SDRAM needs to be replaced with a CPU with external DDR3 SDRAM, the operating system will also be replaced, and all software will be redeveloped; when the scale of the chip is large, the overall workload of redevelopment will be huge and the cost will be high.

Contents of the invention

The object of the present invention is to provide a solution to the above-mentioned problems.

To achieve the above object, the present invention provides an SDRAM bridge circuit. The circuit includes a first module, a second module and a PHY module; wherein, the first module parses the SDRAM access command sent by the controller, and the second module converts the SDRAM access command into a command acceptable to the PHY module, and the PHY module uses the The commands accepted by the PHY module access the memory, where the memory and the controller have different SDRAM types.

By designing an SDRAM bridge circuit, the present invention allows the SDRAM controller to access the DDR3 SDRAM and perform data access through the bridge circuit; compared with replacing or redeveloping the integrated SDRAM controller chip, the circuit changes are small and the development cycle is short. Short, low cost, and very good compatibility with the original system.

Description of drawings

The technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments. In the attached picture:

Fig. 1 is the schematic diagram of the SDRAM bridging circuit of the embodiment of the present invention;

FIG. 2 illustrates the interface signal situation of the first module 110;

FIG. 3 illustrates a schematic diagram of conversion performed by the second module 120;

Figure 4 is a schematic diagram of SDRAM read data transfer;

Fig. 5 is a schematic diagram of SDRAM writing data transfer;

Fig. 6 is a schematic diagram in the case of one-to-one transfer;

Fig. 7 is a schematic diagram of the transfer of the next read command affected by the long time taken by the write command processing;

Fig. 8 is a schematic diagram in the case of one-to-two transfer;

Figure 9 shows a schematic diagram of reading and writing using two sets of PHY switches;

Figure 10 is a state transition table;

Figure 11 is to increase the bit width and reduce the BL to reduce the data transmission time;

FIG. 12 is a schematic diagram of reducing bit width and increasing BL;

FIG. 13 is a schematic diagram of an SDRAM bridge circuit according to another embodiment of the present invention.

Detailed ways

FIG. 1 is a schematic diagram of an SDRAM bridge circuit according to an embodiment of the present invention. As shown in FIG. 1 , the SDRAM bridge circuit includes a first module 110 , a second module 120 and a DDR3 physical interface (hereinafter referred to as PHY) module 130 . The three modules jointly realize the process of converting SDRAM controller access commands into accessing DDR3 SDRAM memory.

The first module 110, also called the SDRAM access command analysis and data transceiving module, is responsible for analyzing the access command sent by the SDRAM controller, and transmitting and receiving signals between the external SDRAM controller. Specifically, the module 110 parses the access command, and sends the parsed access command and the data to be written to the command and data conversion module 120; at the same time, receives the read data sent by the second module 120, and sends it to the external SDRAM controller.

The second module 120, also known as the command and data conversion module, is responsible for converting the SDRAM access command and data into a format and timing acceptable to the DDR3 PHY. Specifically, the command and data conversion module 120 converts the SDRAM access command and write data into the format and timing of DDR3 PHY, and sends it to the DDR3 PHY module 130; at the same time, it receives the read data sent by the DDR3 PHY module 130, The converted data format and timing of the SDRAM controller are sent to the SDRAM access command analysis and data transceiving module 110 .

The DDR3 PHY module 130 integrates the DDR3 PHY and is responsible for controlling the DDR3 SDRAM memory. Specifically, receive commands and write data sent by the second module 120, and send them to the external DDR3 SDRAM memory; receive data read from the external DDR3 SDRAM memory, and send them to the second module 120. According to different application scenarios, one or more DDR3 PHY modules can be integrated. In the figure, the DDR3 PHY module 130 is divided into two applications: one set of DDR3 PHY and two sets of DDR3 PHY (including internal cache).

FIG. 2 schematically shows interface signals of the first module 110 . As shown in Figure 2, the first module 110 performs input sampling on all received signals from the SDRAM controller according to the synchronous channel clock CLK sent by the SDRAM controller, and outputs the transmitted signals sent to the SDRAM controller and is an SDRAM Controller prepares data for reading from DDR3 SDRAM memory.

Signals from the SDRAM controller include SDRAM control signals CKE, CS#, WE#, CAS#, RAS#, address signals A, BA, data IO mask signal DQM, and the data signal is DQ (write/read). CKE is an on-chip clock enable signal, and CS# disables or enables all input signals other than CLK, CKE and DQM. WE# is a write enable signal. CAS#, RAS# are column and row address latch signals respectively. The address signal A is the address bus, and BA is the group address selection. The DQM controls output buffering in read mode and masks input data in write mode.

The first module 110 analyzes the above-mentioned control signal according to the SDRAM truth table, and converts it into an SDRAM access command, that is, ACTIVE (activation row), READ (read), WRITE (write), PRECHARGE (precharge), REFRESH (refresh) command signal. The converted command signal is sent to the second module 120 . In addition, the data bus for writing and reading is also separated.

FIG. 3 shows a schematic diagram of conversion performed by the second module 120 . As shown in Figure 3, the second module 120 is responsible for the conversion between SDRAM access command, data and DDR3 PHY unit. In one example, according to the phase relationship between the working clock of the second module 120 and the synchronous accompanying clock CLK sent by the SDRAM controller, the access commands ACTIVE, READ, WRITE, PRECHARGE, REFRESH are converted into DDR3PHY command signals, and at the same time Transform related data. The working clock of the second module is the interface clock specified by the DDR3 PHY unit. The phase relationship between the two can be determined by collecting the jump edge of the synchronous clock CLK sent by the SDRAM controller to ensure the correctness of data collection. . Generally, the interface clock specified by the PHY unit has a higher frequency than the synchronous associated clock. The DDR3 PHY unit is an IP (intellectual property block) that provides connectivity between the memory controller and the DDR3 memory device. The PHY unit provides a standard DDR PHY interface bus on the memory interface side and an internal bus interface on the local side. The internal bus interface defines the signals and timing between the DDR3 PHY and the corresponding DDR3 SDRAM controller.

In the present invention, the SDRAM controller issues various access commands, and the SDRAM bridge circuit correctly parses and converts the access commands, so that data can be correctly written into and read from the DDR3 SDRAM memory.

Figure 4 is a schematic diagram of SDRAM read data transfer. When the SDRAM controller initiates a read operation request, the first module and the second module in the SDRAM bridge circuit convert the read operation request into a logical read command for DDR3 SDRAM, and the DDR3 PHY module reads the DDR3 SDRAM according to the logical read command . In the embodiment of the present invention, the second module 120 receives the data of the read DDR3 SDRAM sent by the DDR3 PHY module; then, the first module 110 sends the read data to the SDRAM controller to complete the reading process. In one example, the second module finishes reading DDR3 SDRAM within the agreed DDR3 side CL (CAS latency, column address strobe delay, about 6-7 PHY clocks); The read data is sent to the SDRAM controller within the agreed controller side CL (generally 2 or 3 clocks).

FIG. 5 is a schematic diagram of SDRAM writing data transfer. When the SDRAM controller initiates a write operation request, the SDRAM bridge circuit converts the write operation request into a DDR3 SDRAM write command. In addition, in burst mode, the SDRAM bridge circuit usually receives complete or partial write data before sending it to the DDR3 PHY module and then writing it into DDR3 SDRAM. Therefore, the time to complete writing DDR3 SDRAM data may be longer than the conventional SDRAM writing process, which takes up a part of the time after the SDRAM controller writes the command.

When the SDRAM controller initiates writing data and then initiates reading data, according to whether the time taken to process the DDR3 SDRAM command will affect the SDRAM read command transfer, the following two transfer methods can be generated: (1) A pair One transfer; (2) One-to-two transfer.

Fig. 6 is a schematic diagram in the case of one-to-one transfer. When the time taken to write DDR3 SDRAM command processing will not affect the transfer of the next read command of the SDRAM controller, a set of DDR3 PHY plug-in DDR3 SDRAM can complete the SDRAM controller access transfer. At this time, after the SDRAM controller issues the command to write data, it must wait a sufficient time before initiating the command to read. In another case, if the read address of the SDRAM controller can be predicted, the DDR3 SDRAM data can be read in advance, and the cache stored in the PHY module is ready. When the PHY module writes data to the DDR3 SDRAM, the PHY module sends the data stored in the cache to the SDRAM controller through the second module 120 and the first module 110 based on the read request.

Specifically, the second module 120 converts the command and data sent by the first module 110 into the command signal format and timing of DDR3PHY, and sends it to the DDR3PHY module 130, while receiving the read data sent by the DDR3PHY module 130, It is converted into the format and timing of the SDRAM controller and sent to the first module 110 .

If the write DDR3 SDRAM command takes too long to process, it will affect the transfer of the next read command of the SDRAM controller (see Figure 7). At this time, two sets of DDR3 PHY external DDR3 SDRAM and internal cache are used to complete the SDRAM controller access transfer.

Fig. 8 is a schematic diagram in the case of one-to-two handover. As shown in FIG. 8, the PHY module 130 includes two sets of DDR3 PHY units (respectively marked as 1# PHY, 2# PHY). Both 1# and 2# PHY units are externally connected to DDR3 SDRAM memory (marked as 1# DDR3 and 2# DDR3 respectively). The writing data of 1# and 2# two sets of DDR3 needs to be mirrored and synchronized.

PHY module 130 also includes an internal cache. The internal cache is always written with the data requested by the most recent write operation.

The two sets of 1# PHY and 2# PHY are transferred in turn. The internal cache is only enabled when the read address is the same as the latest write address to complete the data readout, and they are combined to complete the SDRAM controller access transfer.

When the SDRAM controller writes data, it is assumed that the 1# PHY writes first, and writes to the internal cache at the same time, and the 2# PHY is on standby, ready to accept the read command issued by the SDRAM controller at any time. If at this time (that is, while writing to 1# PHY), the SDRAM controller initiates a read operation command, if the read and write addresses are different, 2#PHY is responsible for completing the data read; if the read and write addresses are the same, the internal The cache reads previously cached data. After the writing of 1#PHY is completed, the data written into 1#PHY is written into 2#PHY to keep the synchronous mirroring of the data written into the memory by the two sets of PHY units. This avoids read transfer failures. FIG. 9 shows a schematic diagram of reading and writing using two sets of PHY switches.

During normal operation, if the read address is different from the latest write address, whichever set of 1# PHY and 2# PHY is free will be read, and if both sets are free, choose one arbitrarily; If the addresses are the same, the internal cache is read.

In one example, the second module 120 uses a state machine to control the operations of different PHYs and their connected DDR3 SDRAMs.

Figure 10 is a state transition table. As shown in the figure, when the second module is reset or the state machine enters the IDLE state from other states, the second module performs different state jumps for the state machine according to the write and read commands sent by the first module.

1) When the first module 110 sends a write operation <WRITE n> (write n) (n is an address), select 1#PHY to write to its connected 1#DDR3 (mark 100 in the figure), and at the same time The written data is stored in the internal cache (marked 101 in the figure);

2) When the write operation <WRITE n> (write n) of 1# PHY has not been completed, the first module 110 sends the read operation <READ m> (read m, that is, the read address and the write address Different), start reading 2# DDR3 connected to 2# PHY (marked 102 in the figure), and read and transfer;

3) After the 2# DDR3 reading transfer is completed, write the data of 2# DDR3 (marked 105 in the figure), write the content written in 1# DDR3 into 2# DDR3, that is, complete the data transfer of 1# and 2# DDR3 Write data mirror synchronization; after writing is completed (mark 106 in the figure), enter the IDLE state;

4) When the write operation <WRITE n> (write n) of 1# DDR3 has not been completed, the first module 110 just sends the read operation <READ n> (read n) (that is, the read address and the write address When the same), start to read the internal cache (mark 103 in the figure), and perform a read transfer; after completing the reading, enter the data writing of 2#DDR3 (105 in the figure), and complete the two sets of DDR3 of 1# and 2# The write data mirroring synchronization;

5) When the write operation <WRITE n> (write n) of 1# DDR3 is completed, the read command sent by the first module 110 has not been received yet, and 2#DDR3 data is written (mark 104 in the figure), that is Complete 1#, 2# two sets of DDR3 writing data mirror synchronization; after writing is completed (marked 106 in the figure), enter the idle <IDLE> state.

According to the SDRAM access rate, the second module selects the value of the burst transfer period and the bit width to meet different requirements.

In one embodiment, the bit width of the DDR3 SDRAM memory side can be increased, and the BL (burst transfer period) value can be reduced to reduce the data transfer time, so that the read data transfer can obtain more processing time, and the transfer can be completed correctly. catch.

Figure 11 is to increase the bit width and reduce the BL to reduce the data transmission time. As shown in FIG. 11 , for example, the data width of the SDRAM controller is 8 bits, the burst length BL=8, CL=3, and the clock frequency is 100 MHz, that is, there is 30 ns time from the READ command of the SDRAM controller to the return of data. The DDR3 SDRAM side adopts a clock rate of 800MHz, CL=10. If BL=8, the transfer cannot be completed within the 30ns required by the SDRAM controller. It is necessary to increase the bit width of the second module and the PHY module to 16 bits, and reduce the BL to 4, which reduces the data transmission time and can be used in The transfer is completed within 30ns, and the total number of data bits is the same, which is correctly implemented. This approach is suitable for scenarios with a high SDRAM access rate.

In another embodiment, in the case of satisfying the transition time, the bit width of the DDR3 SDRAM memory is reduced, the BL value is increased, and the cost is reduced. FIG. 12 is a schematic diagram of reducing bit width and increasing BL. For example, the data bit width of the SDRAM controller is 32 bits wide, BL=4, CL=3, and the clock frequency is 50MHz, that is, there is 60ns time from the READ command of the SDRAM controller to sending back the data, and the DDR3 side adopts a clock rate of 400MHz, and CL= 6. The bit width is halved to 16 bits, BL is increased to 8, plus the command conversion and data transmission time, the transfer can still be completed within 60ns required by the SDRAM controller, and the total number of data bits (bits) is the same , implemented correctly, reduces costs. This approach is suitable for scenarios with low SDRAM access rates.

FIG. 13 is a schematic diagram of an SDRAM bridge circuit according to another embodiment of the present invention. As shown in FIG. 13 , the SDRAM bridge circuit includes a third module 220 and a DDR3 PHY module 130. Compared with the SDRAM bridge circuit shown in FIG. 1 , the first module 110 and the second module 120 are replaced by a third module 220 . In the third module 220, a working clock and an enabling pulse synchronous with the SDRAM accompanying clock are provided, and the working clock is used to collect SDRAM controller signals under the control of the enabling pulse instead of directly using the SDRAM synchronous clock. The third module 220 parses the access command sent by the SDRAM controller, and completes the sending and receiving of signals with the external SDRAM controller. Specifically, the third module 220 parses the access command under the control of the high-frequency clock, and converts the parsed access command and the data to be written into a format and timing acceptable to the DDR3 PHY. The DDR3 PHY module 130 receives the command and write data sent by the third module 220, and sends it to the external DDR3 SDRAM memory; at the same time, it receives the data read from the external DDR3 SDRAM memory, and sends it to the third module 220.

In addition to the bridging method for transferring SDRAM to DDR3 SDRAM listed above, the present invention is also applicable to transferring SDRAM to DDR2 SDRAM, DDR SDRAM to DDR2 SDRAM, and DDR SDRAM to DDR3 SDRAM when the transfer time is satisfied. of bridging. As long as the access command sent by SDRAM controller or DDRPHY is converted to DDR2/DDR3 PHY, there is enough time to access DDR2/DDR3 SDRAM accordingly, and DDR2/DDR3 PHY can read DDR2/DDR3 SDRAM data in the CL agreed by SDRAM controller/DDR PHY Send it back within a certain time, and the bridge can be correctly realized.

By designing an SDRAM bridge circuit, the present invention can allow the SDRAM controller to realize access to DDR3 SDRAM and perform data access through the bridge circuit; compared with replacing or redeveloping the integrated SDRAM controller chip, the circuit changes little and is easy to develop. The cycle is short, the cost is low, and it is well compatible with the original system.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the scope of the present invention. Protection scope, within the spirit and principles of the present invention, any modification, equivalent replacement, improvement, etc., shall be included in the protection scope of the present invention.

Claims (11)

1. a SDRAM bridgt circuit is characterized in that comprising first module, second module and PHY module; Wherein, The SDRAM visit order that the first module parses controller is sent here; Second module converts the SDRAM visit order the acceptable order of into PHY module, and the PHY module is utilized the acceptable command access storer of said PHY module, and wherein storer has different SDRAM types with controller.

2. SDRAM bridgt circuit as claimed in claim 1, it is characterized in that first module controller with the road clock control under work, second module is worked down in the control of the interface clock of PHY module regulation.

3. SDRAM bridgt circuit as claimed in claim 1; It is characterized in that first module and second module merge into three module; Three module with controller with the control of the work clock of road clock synchronization under resolve visit order, and the visit order after will resolving converts the acceptable order of DDR3PHY into.

4. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that first module carries out command analysis with above-mentioned control signal according to truth table.

5. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that the PHY module comprises a PHY unit.

6. SDRAM bridgt circuit as claimed in claim 5; It is characterized in that the PHY module comprises at least one the 2nd PHY unit and buffer circuit, said second module selects a PHY unit to transfer from a PHY unit and said at least one the 2nd PHY unit.

7. SDRAM bridgt circuit as claimed in claim 6 is characterized in that second module comprises state machine, and second module is coordinated the work of a PHY unit and the 2nd PHY unit according to state machine.

8. SDRAM bridgt circuit as claimed in claim 7 is characterized in that when second module receives the SDRAM visit order of write operation, selects a PHY unit to carry out write operation, writes data simultaneously and deposits inner buffer in; When second module receives the SDRAM visit order that reads the address read operation different with writing the address and said write operation when also not accomplishing, select the 2nd PHY unit to carry out read operation.

9. SDRAM bridgt circuit as claimed in claim 7 is characterized in that when second module receives the SDRAM visit order of write operation, selects a PHY unit to carry out write operation, writes data simultaneously and deposits inner buffer in; When second module receives the SDRAM visit order that reads the address read operation identical with writing the address and said write operation when also not accomplishing, start and read inner buffer; And after completion was read, the data in the inner buffer write the 2nd PHY unit.

10. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that the access rate according to SDRAM, second module is selected burst transfer periodic quantity and bit wide.

11. like the described SDRAM bridgt circuit of one of claim 1-3, it is characterized in that controller is sdram controller or DDR PHY device, storer is DDR2 SDRAM or DDR3 SDRAM.

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